octeon_asxreg.h revision 1.1
1 /* $NetBSD: octeon_asxreg.h,v 1.1 2015/04/29 08:32:01 hikaru Exp $ */ 2 3 /* 4 * Copyright (c) 2007 Internet Initiative Japan, Inc. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 /* 30 * ASX Registers 31 */ 32 33 #ifndef _OCTEON_ASXREG_H_ 34 #define _OCTEON_ASXREG_H_ 35 36 #define ASX0_RX_PRT_EN 0x00011800b0000000ULL 37 #define ASX0_TX_PRT_EN 0x00011800b0000008ULL 38 #define ASX0_INT_REG 0x00011800b0000010ULL 39 #define ASX0_INT_EN 0x00011800b0000018ULL 40 #define ASX0_RX_CLK_SET0 0x00011800b0000020ULL 41 #define ASX0_RX_CLK_SET1 0x00011800b0000028ULL 42 #define ASX0_RX_CLK_SET2 0x00011800b0000030ULL 43 #define ASX0_PRT_LOOP 0x00011800b0000040ULL 44 #define ASX0_TX_CLK_SET0 0x00011800b0000048ULL 45 #define ASX0_TX_CLK_SET1 0x00011800b0000050ULL 46 #define ASX0_TX_CLK_SET2 0x00011800b0000058ULL 47 #define ASX0_COMP_BYP 0x00011800b0000068ULL 48 #define ASX0_TX_HI_WATER000 0x00011800b0000080ULL 49 #define ASX0_TX_HI_WATER001 0x00011800b0000088ULL 50 #define ASX0_TX_HI_WATER002 0x00011800b0000090ULL 51 #define ASX0_GMII_RX_CLK_SET 0x00011800b0000180ULL 52 #define ASX0_GMII_RX_DAT_SET 0x00011800b0000188ULL 53 #define ASX0_MII_RX_DAT_SET 0x00011800b0000190ULL 54 55 #define ASX0_BASE 0x00011800b0000000ULL 56 #define ASX0_SIZE 0x0198ULL 57 58 #define ASX0_RX_PRT_EN_OFFSET 0x0000 59 #define ASX0_TX_PRT_EN_OFFSET 0x0008 60 #define ASX0_INT_REG_OFFSET 0x0010 61 #define ASX0_INT_EN_OFFSET 0x0018 62 #define ASX0_RX_CLK_SET0_OFFSET 0x0020 63 #define ASX0_RX_CLK_SET1_OFFSET 0x0028 64 #define ASX0_RX_CLK_SET2_OFFSET 0x0030 65 #define ASX0_PRT_LOOP_OFFSET 0x0040 66 #define ASX0_TX_CLK_SET0_OFFSET 0x0048 67 #define ASX0_TX_CLK_SET1_OFFSET 0x0050 68 #define ASX0_TX_CLK_SET2_OFFSET 0x0058 69 #define ASX0_COMP_BYP_OFFSET 0x0068 70 #define ASX0_TX_HI_WATER000_OFFSET 0x0080 71 #define ASX0_TX_HI_WATER001_OFFSET 0x0088 72 #define ASX0_TX_HI_WATER002_OFFSET 0x0090 73 #define ASX0_GMII_RX_CLK_SET_OFFSET 0x0180 74 #define ASX0_GMII_RX_DAT_SET_OFFSET 0x0188 75 #define ASX0_MII_RX_DAT_SET_OFFSET 0x0190 76 77 /* XXX */ 78 79 80 /* 81 * ASX_RX_PRT_EN 82 */ 83 #define ASX0_RX_PRT_EN_63_3 0xfffffff8 84 #define ASX0_RX_PRT_EN_PRT_EN 0x00000007 85 86 /* 87 * ASX0_TX_PRT_EN 88 */ 89 #define ASX0_TX_PRT_EN_63_3 0xfffffff8 90 #define ASX0_TX_PRT_EN_PRT_EN 0x00000007 91 92 /* 93 * ASX0_INT_REG 94 */ 95 #define ASX0_INT_REG_63_11 0xfffff800 96 #define ASX0_INT_REG_TXPSH 0x00000700 97 #define ASX0_INT_REG_7 UINT32_C(0x00000080) 98 #define ASX0_INT_REG_TXPOP 0x00000070 99 #define ASX0_INT_REG_3 UINT32_C(0x00000008) 100 #define ASX0_INT_REG_OVRFLW 0x00000007 101 102 /* 103 * ASX0_INT_EN 104 */ 105 #define ASX0_INT_EN_63_11 0xfffff800 106 #define ASX0_INT_EN_TXPSH 0x00000700 107 #define ASX0_INT_EN_7 UINT32_C(0x00000080) 108 #define ASX0_INT_EN_TXPOP 0x00000070 109 #define ASX0_INT_EN_3 UINT32_C(0x00000008) 110 #define ASX0_INT_EN_OVRFLW 0x00000007 111 112 /* 113 * ASX0_RX_CLK_SET 114 */ 115 #define ASX0_RX_CLK_SET_63_5 0xffffffe0 116 #define ASX0_RX_CLK_SET_SETTING 0x0000001f 117 118 /* 119 * ASX0_RRT_LOOP 120 */ 121 #define ASX0_PRT_LOOP_63_7 0xffffff80 122 #define ASX0_PRT_LOOP_EXT_LOOP 0x00000070 123 #define ASX0_PRT_LOOP_3 UINT32_C(0x00000008) 124 #define ASX0_PRT_LOOP_PRT_LOOP 0x00000007 125 126 /* 127 * ASX0_TX_CLK_SET 128 */ 129 #define ASX0_TX_CLK_SET_63_5 0xffffffe0 130 #define ASX0_TX_CLK_SET_SETTING 0x0000001f 131 132 /* 133 * ASX0_TX_COMP_BYP 134 */ 135 #define ASX0_TX_COMP_BYP_63_9 0xfffffe00 136 #define ASX0_TX_COMP_BYP_BYPASS UINT32_C(0x00000100) 137 #define ASX0_TX_COMP_BYP_PCTL 0x000000f0 138 #define ASX0_TX_COMP_BYP_NCTL 0x0000000f 139 140 /* 141 * ASX0_TX_HI_WATER 142 */ 143 #define ASX0_TX_HI_WATER_63_3 0xfffffff8 144 #define ASX0_TX_HI_WATER_MARK 0x00000007 145 146 /* 147 * ASX0_GMXII_RX_CLK_SET 148 */ 149 #define ASX0_GMII_RX_CLK_SET_63_5 0xffffffe0 150 #define ASX0_GMII_RX_CLK_SET_SETTING 0x0000001f 151 152 /* 153 * ASX0_GMXII_RX_DAT_SET 154 */ 155 #define ASX0_GMII_RX_DAT_SET_63_5 0xffffffe0 156 #define ASX0_GMII_RX_DAT_SET_SETTING 0x0000001f 157 158 /* ---- */ 159 160 #define ASX0_RX_PRT_EN_BITS \ 161 "\177" /* new format */ \ 162 "\020" /* hex display */ \ 163 "\020" /* %016x format */ \ 164 "f\x03\x3d" "63_3\0" \ 165 "f\x00\x03" "PRT_EN\0" 166 #define ASX0_TX_PRT_EN_BITS \ 167 "\177" /* new format */ \ 168 "\020" /* hex display */ \ 169 "\020" /* %016x format */ \ 170 "f\x03\x3d" "63_3\0" \ 171 "f\x00\x03" "PRT_EN\0" 172 #define ASX0_INT_REG_BITS \ 173 "\177" /* new format */ \ 174 "\020" /* hex display */ \ 175 "\020" /* %016x format */ \ 176 "f\x0b\x35" "63_11\0" \ 177 "f\x08\x03" "TXPSH\0" \ 178 "b\x07" "7\0" \ 179 "f\x04\x03" "TXPOP\0" \ 180 "b\x03" "3\0" \ 181 "f\x00\x03" "OVRFLW\0" 182 #define ASX0_INT_EN_BITS \ 183 "\177" /* new format */ \ 184 "\020" /* hex display */ \ 185 "\020" /* %016x format */ \ 186 "f\x0b\x35" "63_11\0" \ 187 "f\x08\x03" "TXPSH\0" \ 188 "b\x07" "7\0" \ 189 "f\x04\x03" "TXPOP\0" \ 190 "b\x03" "3\0" \ 191 "f\x00\x03" "OVRFLW\0" 192 #define ASX0_RX_CLK_SET0_BITS \ 193 "\177" /* new format */ \ 194 "\020" /* hex display */ \ 195 "\020" /* %016x format */ \ 196 197 #define ASX0_RX_CLK_SET1_BITS \ 198 "\177" /* new format */ \ 199 "\020" /* hex display */ \ 200 "\020" /* %016x format */ \ 201 202 #define ASX0_RX_CLK_SET2_BITS \ 203 "\177" /* new format */ \ 204 "\020" /* hex display */ \ 205 "\020" /* %016x format */ \ 206 207 #define ASX0_PRT_LOOP_BITS \ 208 "\177" /* new format */ \ 209 "\020" /* hex display */ \ 210 "\020" /* %016x format */ \ 211 "f\x07\x39" "63_7\0" \ 212 "f\x04\x03" "EXT_LOOP\0" \ 213 "b\x03" "3\0" \ 214 "f\x00\x03" "PRT_LOOP\0" 215 #define ASX0_TX_CLK_SET0_BITS \ 216 "\177" /* new format */ \ 217 "\020" /* hex display */ \ 218 "\020" /* %016x format */ \ 219 220 #define ASX0_TX_CLK_SET1_BITS \ 221 "\177" /* new format */ \ 222 "\020" /* hex display */ \ 223 "\020" /* %016x format */ \ 224 225 #define ASX0_TX_CLK_SET2_BITS \ 226 "\177" /* new format */ \ 227 "\020" /* hex display */ \ 228 "\020" /* %016x format */ \ 229 230 #define ASX0_COMP_BYP_BITS \ 231 "\177" /* new format */ \ 232 "\020" /* hex display */ \ 233 "\020" /* %016x format */ \ 234 235 #define ASX0_TX_HI_WATER000_BITS \ 236 "\177" /* new format */ \ 237 "\020" /* hex display */ \ 238 "\020" /* %016x format */ \ 239 240 #define ASX0_TX_HI_WATER001_BITS \ 241 "\177" /* new format */ \ 242 "\020" /* hex display */ \ 243 "\020" /* %016x format */ \ 244 245 #define ASX0_TX_HI_WATER002_BITS \ 246 "\177" /* new format */ \ 247 "\020" /* hex display */ \ 248 "\020" /* %016x format */ \ 249 250 #define ASX0_GMII_RX_CLK_SET_BITS \ 251 "\177" /* new format */ \ 252 "\020" /* hex display */ \ 253 "\020" /* %016x format */ \ 254 "f\x05\x3b" "63_5\0" \ 255 "f\x00\x05" "SETTING\0" 256 #define ASX0_GMII_RX_DAT_SET_BITS \ 257 "\177" /* new format */ \ 258 "\020" /* hex display */ \ 259 "\020" /* %016x format */ \ 260 "f\x05\x3b" "63_5\0" \ 261 "f\x00\x05" "SETTING\0" 262 #define ASX0_MII_RX_DAT_SET_BITS \ 263 "\177" /* new format */ \ 264 "\020" /* hex display */ \ 265 "\020" /* %016x format */ \ 266 267 268 #endif /* _OCTEON_ASXREG_H_ */ 269
Indexes created Tue Sep 30 17:09:57 GMT 2025