octeon_cib.c revision 1.3
1 /* $NetBSD: octeon_cib.c,v 1.3 2021/01/18 02:35:49 thorpej Exp $ */ 2 3 /*- 4 * Copyright (c) 2020 Jared D. McNeill <jmcneill (at) invisible.ca> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 #include "opt_multiprocessor.h" 30 31 #include <sys/cdefs.h> 32 __KERNEL_RCSID(0, "$NetBSD: octeon_cib.c,v 1.3 2021/01/18 02:35:49 thorpej Exp $"); 33 34 #include <sys/param.h> 35 #include <sys/bus.h> 36 #include <sys/device.h> 37 #include <sys/intr.h> 38 #include <sys/systm.h> 39 #include <sys/kernel.h> 40 #include <sys/kmem.h> 41 42 #include <dev/fdt/fdtvar.h> 43 44 #include <arch/mips/cavium/octeonvar.h> 45 46 static int octeon_cib_match(device_t, cfdata_t, void *); 47 static void octeon_cib_attach(device_t, device_t, void *); 48 49 static void * octeon_cib_establish(device_t, u_int *, int, int, 50 int (*)(void *), void *, const char *); 51 static void octeon_cib_disestablish(device_t, void *); 52 static bool octeon_cib_intrstr(device_t, u_int *, char *, size_t); 53 54 static int octeon_cib_intr(void *); 55 56 struct fdtbus_interrupt_controller_func octeon_cib_funcs = { 57 .establish = octeon_cib_establish, 58 .disestablish = octeon_cib_disestablish, 59 .intrstr = octeon_cib_intrstr 60 }; 61 62 struct octeon_cib_intr { 63 bool ih_mpsafe; 64 int ih_type; 65 int (*ih_func)(void *); 66 void *ih_arg; 67 uint64_t ih_mask; 68 }; 69 70 struct octeon_cib_softc { 71 device_t sc_dev; 72 int sc_phandle; 73 bus_space_tag_t sc_bst; 74 bus_space_handle_t sc_bsh_raw; 75 bus_space_handle_t sc_bsh_en; 76 77 struct octeon_cib_intr *sc_intr; 78 u_int sc_nintr; 79 }; 80 81 #define CIB_READ_RAW(sc) \ 82 bus_space_read_8((sc)->sc_bst, (sc)->sc_bsh_raw, 0) 83 #define CIB_WRITE_RAW(sc, val) \ 84 bus_space_write_8((sc)->sc_bst, (sc)->sc_bsh_raw, 0, (val)) 85 #define CIB_READ_EN(sc) \ 86 bus_space_read_8((sc)->sc_bst, (sc)->sc_bsh_en, 0) 87 #define CIB_WRITE_EN(sc, val) \ 88 bus_space_write_8((sc)->sc_bst, (sc)->sc_bsh_en, 0, (val)) 89 90 CFATTACH_DECL_NEW(octcib, sizeof(struct octeon_cib_softc), 91 octeon_cib_match, octeon_cib_attach, NULL, NULL); 92 93 static const struct device_compatible_entry compat_data[] = { 94 { .compat = "cavium,octeon-7130-cib" }, 95 96 { 0 } 97 }; 98 99 static int 100 octeon_cib_match(device_t parent, cfdata_t cf, void *aux) 101 { 102 struct fdt_attach_args * const faa = aux; 103 104 return of_match_compat_data(faa->faa_phandle, compat_data); 105 } 106 107 static void 108 octeon_cib_attach(device_t parent, device_t self, void *aux) 109 { 110 struct octeon_cib_softc * const sc = device_private(self); 111 struct fdt_attach_args * const faa = aux; 112 const int phandle = faa->faa_phandle; 113 char intrstr[128]; 114 bus_addr_t addr; 115 bus_size_t size; 116 u_int max_bits; 117 int error; 118 void *ih; 119 120 sc->sc_dev = self; 121 sc->sc_phandle = phandle; 122 sc->sc_bst = faa->faa_bst; 123 124 if (fdtbus_get_reg(phandle, 0, &addr, &size) != 0 || 125 bus_space_map(sc->sc_bst, addr, size, 0, &sc->sc_bsh_raw) != 0) { 126 aprint_error(": couldn't map RAW register\n"); 127 return; 128 } 129 if (fdtbus_get_reg(phandle, 1, &addr, &size) != 0 || 130 bus_space_map(sc->sc_bst, addr, size, 0, &sc->sc_bsh_en) != 0) { 131 aprint_error(": couldn't map EN register\n"); 132 return; 133 } 134 135 if (!fdtbus_intr_str(phandle, 0, intrstr, sizeof(intrstr))) { 136 aprint_error(": failed to decode interrupt\n"); 137 return; 138 } 139 140 if (of_getprop_uint32(phandle, "cavium,max-bits", &max_bits) != 0) { 141 aprint_error(": missing 'cavium,max-bits' property\n"); 142 return; 143 } 144 if (max_bits == 0 || max_bits > 64) { 145 aprint_error(": 'cavium,max-bits' value out of range\n"); 146 return; 147 } 148 149 sc->sc_intr = kmem_zalloc(sizeof(*sc->sc_intr) * max_bits, KM_SLEEP); 150 sc->sc_nintr = max_bits; 151 152 error = fdtbus_register_interrupt_controller(self, phandle, 153 &octeon_cib_funcs); 154 if (error != 0) { 155 aprint_error(": couldn't register with fdtbus: %d\n", error); 156 return; 157 } 158 159 aprint_naive("\n"); 160 aprint_normal(": CIB\n"); 161 162 CIB_WRITE_EN(sc, 0); 163 CIB_WRITE_RAW(sc, ~0ULL); 164 165 ih = fdtbus_intr_establish(phandle, 0, IPL_SCHED, FDT_INTR_MPSAFE, 166 octeon_cib_intr, sc); 167 if (ih == NULL) { 168 aprint_error_dev(self, "couldn't establish interrupt on %s\n", 169 intrstr); 170 return; 171 } 172 aprint_normal_dev(self, "interrupting on %s\n", intrstr); 173 } 174 175 static void * 176 octeon_cib_establish(device_t dev, u_int *specifier, int ipl, int flags, 177 int (*func)(void *), void *arg, const char *xname) 178 { 179 struct octeon_cib_softc * const sc = device_private(dev); 180 struct octeon_cib_intr *ih; 181 uint64_t val; 182 183 /* 1st cell is the bit number in the CIB* registers */ 184 /* 2nd cell is the triggering setting */ 185 const int bit = be32toh(specifier[0]); 186 const int type = (be32toh(specifier[1]) & 0x3) ? IST_EDGE : IST_LEVEL; 187 188 if (bit > sc->sc_nintr) { 189 aprint_error_dev(dev, "bit %d out of range\n", bit); 190 return NULL; 191 } 192 193 ih = &sc->sc_intr[bit]; 194 ih->ih_mpsafe = (flags & FDT_INTR_MPSAFE) != 0; 195 ih->ih_type = type; 196 ih->ih_func = func; 197 ih->ih_arg = arg; 198 ih->ih_mask = __BIT(bit); 199 200 val = CIB_READ_EN(sc); 201 val |= ih->ih_mask; 202 CIB_WRITE_EN(sc, val); 203 204 return ih; 205 } 206 207 static void 208 octeon_cib_disestablish(device_t dev, void *ih_cookie) 209 { 210 struct octeon_cib_softc * const sc = device_private(dev); 211 struct octeon_cib_intr *ih = ih_cookie; 212 uint64_t val; 213 214 val = CIB_READ_EN(sc); 215 val &= ~ih->ih_mask; 216 CIB_WRITE_EN(sc, val); 217 } 218 219 static bool 220 octeon_cib_intrstr(device_t dev, u_int *specifier, char *buf, 221 size_t buflen) 222 { 223 /* 1st cell is the bit number in the CIB* registers */ 224 const int bit = be32toh(specifier[0]); 225 226 snprintf(buf, buflen, "%s intr %d", device_xname(dev), bit); 227 228 return true; 229 } 230 231 static int 232 octeon_cib_intr(void *priv) 233 { 234 struct octeon_cib_softc * const sc = priv; 235 struct octeon_cib_intr *ih; 236 uint64_t pend; 237 int n, rv = 0; 238 239 pend = CIB_READ_RAW(sc); 240 pend &= CIB_READ_EN(sc); 241 242 while ((n = ffs64(pend)) != 0) { 243 ih = &sc->sc_intr[n - 1]; 244 KASSERT(ih->ih_mask == __BIT(n - 1)); 245 246 if (ih->ih_type == IST_EDGE) 247 CIB_WRITE_RAW(sc, ih->ih_mask); /* ack */ 248 249 #ifdef MULTIPROCESSOR 250 if (!ih->ih_mpsafe) { 251 KERNEL_LOCK(1, NULL); 252 rv |= ih->ih_func(ih->ih_arg); 253 KERNEL_UNLOCK_ONE(NULL); 254 } else 255 #endif 256 rv |= ih->ih_func(ih->ih_arg); 257 258 pend &= ~ih->ih_mask; 259 } 260 261 return rv; 262 } 263
Indexes created Sun Sep 21 20:09:37 GMT 2025