octeon_gmxreg.h revision 1.1
1 /* $NetBSD: octeon_gmxreg.h,v 1.1 2015/04/29 08:32:01 hikaru Exp $ */ 2 3 /* 4 * Copyright (c) 2007 Internet Initiative Japan, Inc. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 /* 30 * GMX Registers 31 */ 32 33 #ifndef _OCTEON_GMXREG_H_ 34 #define _OCTEON_GMXREG_H_ 35 36 #define GMX0_RX0_INT_REG 0x000 37 #define GMX0_RX0_INT_EN 0x008 38 #define GMX0_PRT0_CFG 0x010 39 #define GMX0_RX0_FRM_CTL 0x018 40 #define GMX0_RX0_FRM_CHK 0x020 41 #define GMX0_RX0_FRM_MIN 0x028 42 #define GMX0_RX0_FRM_MAX 0x030 43 #define GMX0_RX0_JABBER 0x038 44 #define GMX0_RX0_DECISION 0x040 45 #define GMX0_RX0_UDD_SKP 0x048 46 #define GMX0_RX0_STATS_CTL 0x050 47 #define GMX0_RX0_IFG 0x058 48 #define GMX0_RX0_RX_INBND 0x060 49 #define GMX0_RX0_STATS_PKTS 0x080 50 #define GMX0_RX0_STATS_OCTS 0x088 51 #define GMX0_RX0_STATS_PKTS_CTL 0x090 52 #define GMX0_RX0_STATS_OCTS_CTL 0x098 53 #define GMX0_RX0_STATS_PKTS_DMAC 0x0a0 54 #define GMX0_RX0_STATS_OCTS_DMAC 0x0a8 55 #define GMX0_RX0_STATS_PKTS_DRP 0x0b0 56 #define GMX0_RX0_STATS_OCTS_DRP 0x0b8 57 #define GMX0_RX0_STATS_PKTS_BAD 0x0c0 58 #define GMX0_RX0_ADR_CTL 0x100 59 #define GMX0_RX0_ADR_CAM_EN 0x108 60 #define GMX0_RX0_ADR_CAM0 0x180 61 #define GMX0_RX0_ADR_CAM1 0x188 62 #define GMX0_RX0_ADR_CAM2 0x190 63 #define GMX0_RX0_ADR_CAM3 0x198 64 #define GMX0_RX0_ADR_CAM4 0x1a0 65 #define GMX0_RX0_ADR_CAM5 0x1a8 66 #define GMX0_TX0_CLK 0x208 67 #define GMX0_TX0_THRESH 0x210 68 #define GMX0_TX0_APPEND 0x218 69 #define GMX0_TX0_SLOT 0x220 70 #define GMX0_TX0_BURST 0x228 71 #define GMX0_SMAC0 0x230 72 #define GMX0_TX0_PAUSE_PKT_TIME 0x238 73 #define GMX0_TX0_MIN_PKT 0x240 74 #define GMX0_TX0_PAUSE_PKT_INTERVAL 0x248 75 #define GMX0_TX0_SOFT_PAUSE 0x250 76 #define GMX0_TX0_PAUSE_TOGO 0x258 77 #define GMX0_TX0_PAUSE_ZERO 0x260 78 #define GMX0_TX0_STATS_CTL 0x268 79 #define GMX0_TX0_CTL 0x270 80 #define GMX0_TX0_STAT0 0x280 81 #define GMX0_TX0_STAT1 0x288 82 #define GMX0_TX0_STAT2 0x290 83 #define GMX0_TX0_STAT3 0x298 84 #define GMX0_TX0_STAT4 0x2a0 85 #define GMX0_TX0_STAT5 0x2a8 86 #define GMX0_TX0_STAT6 0x2b0 87 #define GMX0_TX0_STAT7 0x2b8 88 #define GMX0_TX0_STAT8 0x2c0 89 #define GMX0_TX0_STAT9 0x2c8 90 #define GMX0_BIST0 0x400 91 #define GMX0_RX_PRTS 0x410 92 #define GMX0_RX_BP_DROP0 0x420 93 #define GMX0_RX_BP_DROP1 0x428 94 #define GMX0_RX_BP_DROP2 0x430 95 #define GMX0_RX_BP_ON0 0x440 96 #define GMX0_RX_BP_ON1 0x448 97 #define GMX0_RX_BP_ON2 0x450 98 #define GMX0_RX_BP_OFF0 0x460 99 #define GMX0_RX_BP_OFF1 0x468 100 #define GMX0_RX_BP_OFF2 0x470 101 #define GMX0_TX_PRTS 0x480 102 #define GMX0_TX_IFG 0x488 103 #define GMX0_TX_JAM 0x490 104 #define GMX0_TX_COL_ATTEMPT 0x498 105 #define GMX0_TX_PAUSE_PKT_DMAC 0x4a0 106 #define GMX0_TX_PAUSE_PKT_TYPE 0x4a8 107 #define GMX0_TX_OVR_BP 0x4c8 108 #define GMX0_TX_BP 0x4d0 109 #define GMX0_TX_CORRUPT 0x4d8 110 #define GMX0_RX_PRT_INFO 0x4e8 111 #define GMX0_TX_LFSR 0x4f8 112 #define GMX0_TX_INT_REG 0x500 113 #define GMX0_TX_INT_EN 0x508 114 #define GMX0_NXA_ADR 0x510 115 #define GMX0_BAD_REG 0x518 116 #define GMX0_STAT_BP 0x520 117 #define GMX0_TX_CLK_MSK0 0x780 118 #define GMX0_TX_CLK_MSK1 0x788 119 #define GMX0_RX_TX_STATUS 0x7e8 120 #define GMX0_INF_MODE 0x7f8 121 122 /* -------------------------------------------------------------------------- */ 123 124 /* GMX Interrupt Registers */ 125 126 #define RXN_INT_REG_XXX_63_19 UINT64_C(0xfffffffffff80000) 127 #define RXN_INT_REG_PHY_DUPX UINT64_C(0x0000000000040000) 128 #define RXN_INT_REG_PHY_SPD UINT64_C(0x0000000000020000) 129 #define RXN_INT_REG_PHY_LINK UINT64_C(0x0000000000010000) 130 #define RXN_INT_REG_IFGERR UINT64_C(0x0000000000008000) 131 #define RXN_INT_REG_COLDET UINT64_C(0x0000000000004000) 132 #define RXN_INT_REG_FALERR UINT64_C(0x0000000000002000) 133 #define RXN_INT_REG_RSVERR UINT64_C(0x0000000000001000) 134 #define RXN_INT_REG_PCTERR UINT64_C(0x0000000000000800) 135 #define RXN_INT_REG_OVRERR UINT64_C(0x0000000000000400) 136 #define RXN_INT_REG_NIBERR UINT64_C(0x0000000000000200) 137 #define RXN_INT_REG_SKPERR UINT64_C(0x0000000000000100) 138 #define RXN_INT_REG_RCVERR UINT64_C(0x0000000000000080) 139 #define RXN_INT_REG_LENERR UINT64_C(0x0000000000000040) 140 #define RXN_INT_REG_ALNERR UINT64_C(0x0000000000000020) 141 #define RXN_INT_REG_FCSERR UINT64_C(0x0000000000000010) 142 #define RXN_INT_REG_JABBER UINT64_C(0x0000000000000008) 143 #define RXN_INT_REG_MAXERR UINT64_C(0x0000000000000004) 144 #define RXN_INT_REG_CAREXT UINT64_C(0x0000000000000002) 145 #define RXN_INT_REG_MINERR UINT64_C(0x0000000000000001) 146 147 /* GMX Interrupt-Enable Registers */ 148 149 #define RXN_INT_EN_XXX_63_19 UINT64_C(0xfffffffffff80000) 150 #define RXN_INT_EN_PHY_DUPX UINT64_C(0x0000000000040000) 151 #define RXN_INT_EN_PHY_SPD UINT64_C(0x0000000000020000) 152 #define RXN_INT_EN_PHY_LINK UINT64_C(0x0000000000010000) 153 #define RXN_INT_EN_IFGERR UINT64_C(0x0000000000008000) 154 #define RXN_INT_EN_COLDET UINT64_C(0x0000000000004000) 155 #define RXN_INT_EN_FALERR UINT64_C(0x0000000000002000) 156 #define RXN_INT_EN_RSVERR UINT64_C(0x0000000000001000) 157 #define RXN_INT_EN_PCTERR UINT64_C(0x0000000000000800) 158 #define RXN_INT_EN_OVRERR UINT64_C(0x0000000000000400) 159 #define RXN_INT_EN_NIBERR UINT64_C(0x0000000000000200) 160 #define RXN_INT_EN_SKPERR UINT64_C(0x0000000000000100) 161 #define RXN_INT_EN_RCVERR UINT64_C(0x0000000000000080) 162 #define RXN_INT_EN_LENERR UINT64_C(0x0000000000000040) 163 #define RXN_INT_EN_ALNERR UINT64_C(0x0000000000000020) 164 #define RXN_INT_EN_FCSERR UINT64_C(0x0000000000000010) 165 #define RXN_INT_EN_JABBER UINT64_C(0x0000000000000008) 166 #define RXN_INT_EN_MAXERR UINT64_C(0x0000000000000004) 167 #define RXN_INT_EN_CAREXT UINT64_C(0x0000000000000002) 168 #define RXN_INT_EN_MINERR UINT64_C(0x0000000000000001) 169 170 /* GMX Port Configuration Registers */ 171 172 #define PRTN_CFG_XXX_63_4 UINT64_C(0xfffffffffffffff0) 173 #define PRTN_CFG_SLOTTIME UINT64_C(0x0000000000000008) 174 #define PRTN_CFG_DUPLEX UINT64_C(0x0000000000000004) 175 #define PRTN_CFG_SPEED UINT64_C(0x0000000000000002) 176 #define PRTN_CFG_EN UINT64_C(0x0000000000000001) 177 178 /* Frame Control Registers */ 179 180 #define RXN_FRM_CTL_XXX_63_11 UINT64_C(0xfffffffffffff800) 181 #define RXN_FRM_CTL_NULL_DIS UINT64_C(0x0000000000000400) 182 #define RXN_FRM_CTL_PRE_ALIGN UINT64_C(0x0000000000000200) 183 #define RXN_FRM_CTL_PAD_LEN UINT64_C(0x0000000000000100) 184 #define RXN_FRM_CTL_VLAN_LEN UINT64_C(0x0000000000000080) 185 #define RXN_FRM_CTL_PRE_FREE UINT64_C(0x0000000000000040) 186 #define RXN_FRM_CTL_CTL_SMAC UINT64_C(0x0000000000000020) 187 #define RXN_FRM_CTL_CTL_MCST UINT64_C(0x0000000000000010) 188 #define RXN_FRM_CTL_CTL_BCK UINT64_C(0x0000000000000008) 189 #define RXN_FRM_CTL_CTL_DRP UINT64_C(0x0000000000000004) 190 #define RXN_FRM_CTL_PRE_STRP UINT64_C(0x0000000000000002) 191 #define RXN_FRM_CTL_PRE_CHK UINT64_C(0x0000000000000001) 192 193 /* Frame Check Registers */ 194 195 #define RXN_FRM_CKK_XXX_63_10 UINT64_C(0xfffffffffffffc00) 196 #define RXN_FRM_CHK_NIBERR UINT64_C(0x0000000000000200) 197 #define RXN_FRM_CHK_SKPERR UINT64_C(0x0000000000000100) 198 #define RXN_FRM_CHK_RCVERR UINT64_C(0x0000000000000080) 199 #define RXN_FRM_CHK_LENERR UINT64_C(0x0000000000000040) 200 #define RXN_FRM_CHK_ALNERR UINT64_C(0x0000000000000020) 201 #define RXN_FRM_CHK_FCSERR UINT64_C(0x0000000000000010) 202 #define RXN_FRM_CHK_JABBER UINT64_C(0x0000000000000008) 203 #define RXN_FRM_CHK_MAXERR UINT64_C(0x0000000000000004) 204 #define RXN_FRM_CHK_CAREXT UINT64_C(0x0000000000000002) 205 #define RXN_FRM_CHK_MINERR UINT64_C(0x0000000000000001) 206 207 /* Frame Minimum-Length Registers */ 208 209 #define RXN_RRM_MIN_XXX_63_16 UINT64_C(0xffffffffffff0000) 210 #define RXN_RRM_MIN_LEN UINT64_C(0x000000000000ffff) 211 212 /* Frame Maximun-Length Registers */ 213 214 #define RXN_RRM_MAX_XXX_63_16 UINT64_C(0xffffffffffff0000) 215 #define RXN_RRM_MAX_LEN UINT64_C(0x000000000000ffff) 216 217 /* GMX Maximun Packet-Size Registers */ 218 219 #define RXN_JABBER_XXX_63_16 UINT64_C(0xffffffffffff0000) 220 #define RXN_JABBER_CNT UINT64_C(0x000000000000ffff) 221 222 /* GMX Packet Decision Registers */ 223 224 #define RXN_DECISION_XXX_63_5 UINT64_C(0xffffffffffffffe0) 225 #define RXN_DECISION_CNT UINT64_C(0x000000000000001f) 226 227 /* GMX User-Defined Data Skip Registers */ 228 229 #define RXN_UDD_SKP_XXX_63_9 UINT64_C(0xfffffffffffffe00) 230 #define RXN_UDD_SKP_FCSSEL UINT64_C(0x0000000000000100) 231 #define RXN_UDD_SKP_XXX_7 UINT64_C(0x0000000000000080) 232 #define RXN_UDD_SKP_LEN UINT64_C(0x000000000000007f) 233 234 /* GMX RX Statistics Control Registers */ 235 236 #define RXN_STATS_CTL_XXX_63_1 UINT64_C(0xfffffffffffffffe) 237 #define RXN_STATS_CTL_RD_CLR UINT64_C(0x0000000000000001) 238 239 /* GMX Minimun Interface-Gap Cycles Registers */ 240 241 #define RXN_IFG_XXX_63_4 UINT64_C(0xfffffffffffffff0) 242 #define RXN_IFG_IFG UINT64_C(0x000000000000000f) 243 244 /* InBand Link Status Registers */ 245 246 #define RXN_RX_INBND_XXX_63_4 UINT64_C(0xfffffffffffffff0) 247 #define RXN_RX_INBND_DUPLEX UINT64_C(0x0000000000000008) 248 #define RXN_RX_INBND_DUPLEX_SHIFT 3 249 #define RXN_RX_INBND_DUPLEX_HALF (0ULL << RXN_RX_INBND_DUPLEX_SHIFT) 250 #define RXN_RX_INBND_DUPLEX_FULL (1ULL << RXN_RX_INBND_DUPLEX_SHIFT) 251 #define RXN_RX_INBND_SPEED UINT64_C(0x0000000000000006) 252 #define RXN_RX_INBND_SPEED_SHIFT 1 253 #define RXN_RX_INBND_SPEED_2_5 (0ULL << RXN_RX_INBND_SPEED_SHIFT) 254 #define RXN_RX_INBND_SPEED_25 (1ULL << RXN_RX_INBND_SPEED_SHIFT) 255 #define RXN_RX_INBND_SPEED_125 (2ULL << RXN_RX_INBND_SPEED_SHIFT) 256 #define RXN_RX_INBND_SPEED_XXX_3 (3ULL << RXN_RX_INBND_SPEED_SHIFT) 257 #define RXN_RX_INBND_STATUS UINT64_C(0x0000000000000001) 258 259 /* GMX RX Good Packets Registers */ 260 261 #define RXN_STATS_PKTS_XXX_63_32 UINT64_C(0xffffffff00000000) 262 #define RXN_STATS_PKTS_CNT UINT64_C(0x00000000ffffffff) 263 264 /* GMX RX Good Packets Octet Registers */ 265 266 #define RXN_STATS_OCTS_XXX_63_48 UINT64_C(0xffff000000000000) 267 #define RXN_STATS_OCTS_CNT UINT64_C(0x0000ffffffffffff) 268 269 /* GMX RX Pause Packets Registers */ 270 271 #define RXN_STATS_PKTS_CTL_XXX_63_32 UINT64_C(0xffffffff00000000) 272 #define RXN_STATS_PKTS_CTL_CNT UINT64_C(0x00000000ffffffff) 273 274 /* GMX RX Pause Packets Octet Registers */ 275 276 #define RXN_STATS_OCTS_CTL_XXX_63_48 UINT64_C(0xffff000000000000) 277 #define RXN_STATS_OCTS_CTL_CNT UINT64_C(0x0000ffffffffffff) 278 279 /* GMX RX DMAC Packets Registers */ 280 281 #define RXN_STATS_PKTS_DMAC_XXX_63_32 UINT64_C(0xffffffff00000000) 282 #define RXN_STATS_PKTS_DMAC_CNT UINT64_C(0x00000000ffffffff) 283 284 /* GMX RX DMAC Packets Octet Registers */ 285 286 #define RXN_STATS_OCTS_DMAC_XXX_63_48 UINT64_C(0xffff000000000000) 287 #define RXN_STATS_OCTS_DMAC_CNT UINT64_C(0x0000ffffffffffff) 288 289 /* GMX RX Overflow Packets Registers */ 290 291 #define RXN_STATS_PKTS_DRP_XXX_63_48 UINT64_C(0xffffffff00000000) 292 #define RXN_STATS_PKTS_DRP_CNT UINT64_C(0x00000000ffffffff) 293 294 /* GMX RX Overflow Packets Octet Registers */ 295 296 #define RXN_STATS_OCTS_DRP_XXX_63_48 UINT64_C(0xffff000000000000) 297 #define RXN_STATS_OCTS_DRP_CNT UINT64_C(0x0000ffffffffffff) 298 299 /* GMX RX Bad Packets Registers */ 300 301 #define RXN_STATS_PKTS_BAD_XXX_63_48 UINT64_C(0xffffffff00000000) 302 #define RXN_STATS_PKTS_BAD_CNT UINT64_C(0x00000000ffffffff) 303 304 /* Address-Filtering Control Registers */ 305 306 #define RXN_ADR_CTL_XXX_63_4 UINT64_C(0xfffffffffffffff0) 307 #define RXN_ADR_CTL_CAM_MODE UINT64_C(0x0000000000000008) 308 #define RXN_ADR_CTL_CAM_MODE_SHIFT 3 309 #define RXN_ADR_CTL_CAM_MODE_REJECT (0ULL << RXN_ADR_CTL_CAM_MODE_SHIFT) 310 #define RXN_ADR_CTL_CAM_MODE_ACCEPT (1ULL << RXN_ADR_CTL_CAM_MODE_SHIFT) 311 #define RXN_ADR_CTL_MCST UINT64_C(0x0000000000000006) 312 #define RXN_ADR_CTL_MCST_SHIFT 1 313 #define RXN_ADR_CTL_MCST_AFCAM (0ULL << RXN_ADR_CTL_MCST_SHIFT) 314 #define RXN_ADR_CTL_MCST_REJECT (1ULL << RXN_ADR_CTL_MCST_SHIFT) 315 #define RXN_ADR_CTL_MCST_ACCEPT (2ULL << RXN_ADR_CTL_MCST_SHIFT) 316 #define RXN_ADR_CTL_MCST_XXX_3 (3ULL << RXN_ADR_CTL_MCST_SHIFT) 317 #define RXN_ADR_CTL_BCST UINT64_C(0x0000000000000001) 318 319 /* Address-Filtering Control Enable Registers */ 320 321 #define RXN_ADR_CAM_EN_XXX_63_8 UINT64_C(0xffffffffffffff00) 322 #define RXN_ADR_CAM_EN_EN UINT64_C(0x00000000000000ff) 323 324 /* Address-Filtering CAM Control Registers */ 325 #define RXN_ADR_CAMN_ADR UINT64_C(0xffffffffffffffff) 326 327 /* GMX TX Clock Generation Registers */ 328 329 #define TXN_CLK_XXX_63_6 UINT64_C(0xffffffffffffffc0) 330 #define TXN_CLK_CLK_CNT UINT64_C(0x000000000000003f) 331 332 /* TX Threshold Registers */ 333 334 #define TXN_THRESH_XXX_63_6 UINT64_C(0xffffffffffffffc0) 335 #define TXN_THRESH_CNT UINT64_C(0x000000000000003f) 336 337 /* TX Append Control Registers */ 338 339 #define TXN_APPEND_XXX_63_4 UINT64_C(0xfffffffffffffff0) 340 #define TXN_APPEND_FORCE_FCS UINT64_C(0x0000000000000008) 341 #define TXN_APPEND_FCS UINT64_C(0x0000000000000004) 342 #define TXN_APPEND_PAD UINT64_C(0x0000000000000002) 343 #define TXN_APPEND_PREAMBLE UINT64_C(0x0000000000000001) 344 345 /* TX Slottime Counter Registers */ 346 347 #define TXN_SLOT_XXX_63_10 UINT64_C(0xfffffffffffffc00) 348 #define TXN_SLOT_SLOT UINT64_C(0x00000000000003ff) 349 350 /* TX Burst-Counter Registers */ 351 352 #define TXN_BURST_XXX_63_16 UINT64_C(0xffffffffffff0000) 353 #define TXN_BURST_BURST UINT64_C(0x000000000000ffff) 354 355 /* RGMII SMAC Registers */ 356 357 #define SMACN_XXX_63_48 UINT64_C(0xffff000000000000) 358 #define SMACN_SMAC UINT64_C(0x0000ffffffffffff) 359 360 /* TX Pause Packet Pause-Time Registers */ 361 362 #define TXN_PAUSE_PKT_TIME_XXX_63_16 UINT64_C(0xffffffffffff0000) 363 #define TXN_PAUSE_PKT_TIME_TIME UINT64_C(0x000000000000ffff) 364 365 /* RGMII TX Minimum-Size-Packet Registers */ 366 367 #define TXN_MIN_PKT_XXX_63_8 UINT64_C(0xffffffffffffff00) 368 #define TXN_MIN_PKT_MIN_SIZE UINT64_C(0x00000000000000ff) 369 370 /* TX Pause-Packet Transmission-Interval Registers */ 371 372 #define TXN_PAUSE_PKT_INTERVAL_XXX_63_16 UINT64_C(0xffffffffffff0000) 373 #define TXN_PAUSE_PKT_INTERVAL_INTERVAL UINT64_C(0x000000000000ffff) 374 375 /* TX Software-Pause Registers */ 376 377 #define TXN_SOFT_PAUSE_XXX_63_16 UINT64_C(0xffffffffffff0000) 378 #define TXN_SOFT_PAUSE_TIME UINT64_C(0x000000000000ffff) 379 380 /* TX Time-to-Backpressure Registers */ 381 382 #define TXN_PAUSE_TOGO_XXX_63_16 UINT64_C(0xffffffffffff0000) 383 #define TXN_PAUSE_TOGO_TIME UINT64_C(0x000000000000ffff) 384 385 /* TX Pause-Zero-Enable Registers */ 386 387 #define TXN_PAUSE_ZERO_XXX_63_1 UINT64_C(0xfffffffffffffffe) 388 #define TXN_PAUSE_ZERO_SEND UINT64_C(0x0000000000000001) 389 390 /* GMX TX Statistics Control Registers */ 391 392 #define TXN_STATS_CTL_XXX_63_1 UINT64_C(0xfffffffffffffffe) 393 #define TXN_STATS_CTL_RD_CLR UINT64_C(0x0000000000000001) 394 395 /* GMX TX Transmit Control Registers */ 396 397 #define TXN_CTL_XXX_63_2 UINT64_C(0xfffffffffffffffc) 398 #define TXN_CTL_XSDEF_EN UINT64_C(0x0000000000000002) 399 #define TXN_CTL_XSCOL_EN UINT64_C(0x0000000000000001) 400 401 /* Transmit Statistics Registers 0 */ 402 403 #define TXN_STAT0_XSDEF UINT64_C(0xffffffff00000000) 404 #define TXN_STAT0_XSCOL UINT64_C(0x00000000ffffffff) 405 406 /* Transmit Statistics Registers 1 */ 407 408 #define TXN_STAT1_SCOL UINT64_C(0xffffffff00000000) 409 #define TXN_STAT1_MSCOL UINT64_C(0x00000000ffffffff) 410 411 /* Transmit Statistics Registers 2 */ 412 413 #define TXN_STAT2_XXX_63_48 UINT64_C(0xffff000000000000) 414 #define TXN_STAT2_OCTS UINT64_C(0x0000ffffffffffff) 415 416 /* Transmit Statistics Registers 3 */ 417 418 #define TXN_STAT3_XXX_63_48 UINT64_C(0xffffffff00000000) 419 #define TXN_STAT3_PKTS UINT64_C(0x00000000ffffffff) 420 421 /* Transmit Statistics Registers 4 */ 422 423 #define TXN_STAT4_HIST1 UINT64_C(0xffffffff00000000) 424 #define TXN_STAT4_HIST0 UINT64_C(0x00000000ffffffff) 425 426 /* Transmit Statistics Registers 5 */ 427 428 #define TXN_STAT5_HIST3 UINT64_C(0xffffffff00000000) 429 #define TXN_STAT5_HIST2 UINT64_C(0x00000000ffffffff) 430 431 /* Transmit Statistics Registers 6 */ 432 433 #define TXN_STAT6_HIST5 UINT64_C(0xffffffff00000000) 434 #define TXN_STAT6_HIST4 UINT64_C(0x00000000ffffffff) 435 436 /* Transmit Statistics Registers 7 */ 437 438 #define TXN_STAT7_HIST7 UINT64_C(0xffffffff00000000) 439 #define TXN_STAT7_HIST6 UINT64_C(0x00000000ffffffff) 440 441 /* Transmit Statistics Registers 8 */ 442 443 #define TXN_STAT8_MCST UINT64_C(0xffffffff00000000) 444 #define TXN_STAT8_BCST UINT64_C(0x00000000ffffffff) 445 446 /* Transmit Statistics Register 9 */ 447 448 #define TXN_STAT9_UNDFLW UINT64_C(0xffffffff00000000) 449 #define TXN_STAT9_CTL UINT64_C(0x00000000ffffffff) 450 451 /* BMX BIST Results Register */ 452 453 #define BIST_XXX_63_10 UINT64_C(0xfffffffffffffc00) 454 #define BIST_STATUS UINT64_C(0x00000000000003ff) 455 456 /* RX Ports Register */ 457 458 #define RX_PRTS_XXX_63_3 UINT64_C(0xfffffffffffffff8) 459 #define RX_PRTS_PRTS UINT64_C(0x0000000000000007) 460 461 /* RX FIFO Packet-Drop Registers */ 462 463 #define RX_BP_DROPN_XXX_63_6 UINT64_C(0xffffffffffffffc0) 464 #define RX_BP_DROPN_MARK UINT64_C(0x000000000000003f) 465 466 /* RX Backpressure On Registers */ 467 468 #define RX_BP_ONN_XXX_63_9 UINT64_C(0xfffffffffffffe00) 469 #define RX_BP_ONN_MARK UINT64_C(0x00000000000001ff) 470 471 /* RX Backpressure Off Registers */ 472 473 #define RX_BP_OFFN_XXX_63_6 UINT64_C(0xffffffffffffffc0) 474 #define RX_BP_OFFN_MARK UINT64_C(0x000000000000003f) 475 476 /* TX Ports Register */ 477 478 #define TX_PRTS_XXX_63_5 UINT64_C(0xffffffffffffffe0) 479 #define TX_PRTS_PRTS UINT64_C(0x000000000000001f) 480 481 /* TX Interframe Gap Register */ 482 483 #define TX_IFG_XXX_63_8 UINT64_C(0xffffffffffffff00) 484 #define TX_IFG_IFG2 UINT64_C(0x00000000000000f0) 485 #define TX_IFG_IFG1 UINT64_C(0x000000000000000f) 486 487 /* TX Jam Pattern Register */ 488 489 #define TX_JAM_XXX_63_8 UINT64_C(0xffffffffffffff00) 490 #define TX_JAM_JAM UINT64_C(0x00000000000000ff) 491 492 /* TX Collision Attempts Before Dropping Frame Register */ 493 494 #define TX_COL_ATTEMPT_XXX_63_5 UINT64_C(0xffffffffffffffe0) 495 #define TX_COL_ATTEMPT_LIMIT UINT64_C(0x000000000000001f) 496 497 /* TX Pause-Packet DMAC-Field Register */ 498 499 #define TX_PAUSE_PKT_DMAC_XXX_63_48 UINT64_C(0xffff000000000000) 500 #define TX_PAUSE_PKT_DMAC_DMAC UINT64_C(0x0000ffffffffffff) 501 502 /* TX Pause Packet Type Field Register */ 503 504 #define TX_PAUSE_PKT_TYPE_XXX_63_16 UINT64_C(0xffffffffffff0000) 505 #define TX_PAUSE_PKT_TYPE_TYPE UINT64_C(0x000000000000ffff) 506 507 /* TX Override Backpressure Register */ 508 509 #define TX_OVR_BP_XXX_63_12 UINT64_C(0xfffffffffffff000) 510 #define TX_OVR_BP_XXX_11 UINT64_C(0x0000000000000800) 511 #define TX_OVR_BP_EN UINT64_C(0x0000000000000700) 512 #define TX_OVR_BP_EN_SHIFT 8 513 #define TX_OVR_BP_XXX_7 UINT64_C(0x0000000000000080) 514 #define TX_OVR_BP_BP UINT64_C(0x0000000000000070) 515 #define TX_OVR_BP_BP_SHIFT 4 516 #define TX_OVR_BP_XXX_3 UINT64_C(0x0000000000000008) 517 #define TX_OVR_BP_IGN_FULL UINT64_C(0x0000000000000007) 518 #define TX_OVR_BP_IGN_FULL_SHIFT 0 519 520 /* TX Override Backpressure Register */ 521 522 #define TX_OVR_BP_XXX_63_12 UINT64_C(0xfffffffffffff000) 523 #define TX_OVR_BP_XXX_11 UINT64_C(0x0000000000000800) 524 #define TX_OVR_BP_EN UINT64_C(0x0000000000000700) 525 #define TX_OVR_BP_XXX_7 UINT64_C(0x0000000000000080) 526 #define TX_OVR_BP_BP UINT64_C(0x0000000000000070) 527 #define TX_OVR_BP_XXX_3 UINT64_C(0x0000000000000008) 528 #define TX_OVR_BP_IGN_FULL UINT64_C(0x0000000000000007) 529 530 /* TX Backpressure Status Register */ 531 532 #define TX_BP_SR_XXX_63_3 UINT64_C(0xfffffffffffffff8) 533 #define TX_BP_SR_BP UINT64_C(0x0000000000000007) 534 535 /* TX Corrupt Packets Register */ 536 537 #define TX_CORRUPT_XXX_63_3 UINT64_C(0xfffffffffffffff8) 538 #define TX_CORRUPT_CORRUPT UINT64_C(0x0000000000000007) 539 540 /* RX Port State Information Register */ 541 542 #define RX_PRT_INFO_XXX_63_19 UINT64_C(0xfffffffffff80000) 543 #define RX_PRT_INFO_DROP UINT64_C(0x0000000000070000) 544 #define RX_PRT_INFO_XXX_15_3 UINT64_C(0x000000000000fff8) 545 #define RX_PRT_INFO_COMMIT UINT64_C(0x0000000000000007) 546 547 /* TX LFSR Register */ 548 549 #define TX_LFSR_XXX_63_16 UINT64_C(0xffffffffffff0000) 550 #define TX_LFSR_LFSR UINT64_C(0x000000000000ffff) 551 552 /* TX Interrupt Register */ 553 554 #define TX_INT_REG_XXX_63_20 UINT64_C(0xfffffffffff00000) 555 #define TX_INT_REG_XXX_19 UINT64_C(0x0000000000080000) 556 #define TX_INT_REG_LATE_COL UINT64_C(0x0000000000070000) 557 #define TX_INT_REG_XXX_15 UINT64_C(0x0000000000008000) 558 #define TX_INT_REG_XSDEF UINT64_C(0x0000000000007000) 559 #define TX_INT_REG_XXX_11 UINT64_C(0x0000000000000800) 560 #define TX_INT_REG_XSCOL UINT64_C(0x0000000000000700) 561 #define TX_INT_REG_XXX_7_5 UINT64_C(0x00000000000000e0) 562 #define TX_INT_REG_UNDFLW UINT64_C(0x000000000000001c) 563 #define TX_INT_REG_XXX_1 UINT64_C(0x0000000000000002) 564 #define TX_INT_REG_PKO_NXA UINT64_C(0x0000000000000001) 565 566 /* TX Interrupt Register */ 567 568 #define TX_INT_EN_XXX_63_20 UINT64_C(0xfffffffffff00000) 569 #define TX_INT_EN_XXX_19 UINT64_C(0x0000000000080000) 570 #define TX_INT_EN_LATE_COL UINT64_C(0x0000000000070000) 571 #define TX_INT_EN_XXX_15 UINT64_C(0x0000000000008000) 572 #define TX_INT_EN_XSDEF UINT64_C(0x0000000000007000) 573 #define TX_INT_EN_XXX_11 UINT64_C(0x0000000000000800) 574 #define TX_INT_EN_XSCOL UINT64_C(0x0000000000000700) 575 #define TX_INT_EN_XXX_7_5 UINT64_C(0x00000000000000e0) 576 #define TX_INT_EN_UNDFLW UINT64_C(0x000000000000001c) 577 #define TX_INT_EN_XXX_1 UINT64_C(0x0000000000000002) 578 #define TX_INT_EN_PKO_NXA UINT64_C(0x0000000000000001) 579 580 /* Address-out-of-Range Error Register */ 581 582 #define NXA_ADR_XXX_63_6 UINT64_C(0xffffffffffffffc0) 583 #define NXA_ADR_PRT UINT64_C(0x000000000000003f) 584 585 /* GMX Miscellaneous Error Register */ 586 587 #define BAD_REG_XXX_63_31 UINT64_C(0xffffffff80000000) 588 #define BAD_REG_INB_NXA UINT64_C(0x0000000078000000) 589 #define BAD_REG_STATOVR UINT64_C(0x0000000004000000) 590 #define BAD_REG_XXX_25 UINT64_C(0x0000000002000000) 591 #define BAD_REG_LOSTSTAT UINT64_C(0x0000000001c00000) 592 #define BAD_REG_XXX_21_18 UINT64_C(0x00000000003c0000) 593 #define BAD_REG_XXX_17_5 UINT64_C(0x000000000003ffe0) 594 #define BAD_REG_OUT_OVR UINT64_C(0x000000000000001c) 595 #define BAD_REG_XXX_1_0 UINT64_C(0x0000000000000003) 596 597 /* GMX Backpressure Statistics Register */ 598 599 #define STAT_BP_XXX_63_17 UINT64_C(0xfffffffffffe0000) 600 #define STAT_BP_BP UINT64_C(0x0000000000010000) 601 #define STAT_BP_CNT UINT64_C(0x000000000000ffff) 602 603 /* Mode Change Mask Registers */ 604 605 #define TX_CLK_MSKN_XXX_63_1 UINT64_C(0xfffffffffffffffe) 606 #define TX_CLK_MSKN_MSK UINT64_C(0x0000000000000001) 607 608 /* GMX RX/TX Status Register */ 609 610 #define RX_TX_STATUS_XXX_63_7 UINT64_C(0xffffffffffffff80) 611 #define RX_TX_STATUS_TX UINT64_C(0x0000000000000070) 612 #define RX_TX_STATUS_XXX_3 UINT64_C(0x0000000000000008) 613 #define RX_TX_STATUS_RX UINT64_C(0x0000000000000007) 614 615 /* Interface Mode Register */ 616 617 #define INF_MODE_XXX_63_3 UINT64_C(0xfffffffffffffff8) 618 #define INF_MODE_P0MII UINT64_C(0x0000000000000004) 619 #define INF_MODE_EN UINT64_C(0x0000000000000002) 620 #define INF_MODE_TYPE UINT64_C(0x0000000000000001) 621 622 /* -------------------------------------------------------------------------- */ 623 624 /* for bus_space(9) */ 625 626 #define GMX_IF_NUNITS 1 627 #define GMX_PORT_NUNITS 3 628 629 #define GMX0_BASE_PORT0 0x0001180008000000ULL 630 #define GMX0_BASE_PORT1 0x0001180008000800ULL 631 #define GMX0_BASE_PORT2 0x0001180008001000ULL 632 #define GMX0_BASE_PORT_SIZE 0x00800 633 #define GMX0_BASE_IF0 0x0001180008000000ULL 634 #define GMX0_BASE_IF_SIZE (GMX0_BASE_PORT_SIZE * GMX_PORT_NUNITS) 635 636 /* for snprintb(9) */ 637 638 #define RXN_INT_REG_BITS \ 639 "\177" /* new format */ \ 640 "\020" /* hex display */ \ 641 "\020" /* %016x format */ \ 642 "b\x12" "PHY_DUPX\0" \ 643 "b\x11" "PHY_SPD\0" \ 644 "b\x10" "PHY_LINK\0" \ 645 "b\x0f" "IFGERR\0" \ 646 "b\x0e" "COLDET\0" \ 647 "b\x0d" "FALERR\0" \ 648 "b\x0c" "RSVERR\0" \ 649 "b\x0b" "PCTERR\0" \ 650 "b\x0a" "OVRERR\0" \ 651 "b\x09" "NIBERR\0" \ 652 "b\x08" "SKPERR\0" \ 653 "b\x07" "RCVERR\0" \ 654 "b\x06" "LENERR\0" \ 655 "b\x05" "ALNERR\0" \ 656 "b\x04" "FCSERR\0" \ 657 "b\x03" "JABBER\0" \ 658 "b\x02" "MAXERR\0" \ 659 "b\x01" "CAREXT\0" \ 660 "b\x00" "MINERR\0" 661 #define RXN_INT_EN_BITS \ 662 "\177" /* new format */ \ 663 "\020" /* hex display */ \ 664 "\020" /* %016x format */ \ 665 "b\x12" "PHY_DUPX\0" \ 666 "b\x11" "PHY_SPD\0" \ 667 "b\x10" "PHY_LINK\0" \ 668 "b\x0f" "IFGERR\0" \ 669 "b\x0e" "COLDET\0" \ 670 "b\x0d" "FALERR\0" \ 671 "b\x0c" "RSVERR\0" \ 672 "b\x0b" "PCTERR\0" \ 673 "b\x0a" "OVRERR\0" \ 674 "b\x09" "NIBERR\0" \ 675 "b\x08" "SKPERR\0" \ 676 "b\x07" "RCVERR\0" \ 677 "b\x06" "LENERR\0" \ 678 "b\x05" "ALNERR\0" \ 679 "b\x04" "FCSERR\0" \ 680 "b\x03" "JABBER\0" \ 681 "b\x02" "MAXERR\0" \ 682 "b\x01" "CAREXT\0" \ 683 "b\x00" "MINERR\0" 684 #define PRTN_CFG_BITS \ 685 "\177" /* new format */ \ 686 "\020" /* hex display */ \ 687 "\020" /* %016x format */ \ 688 "b\x03" "SLOTTIME\0" \ 689 "b\x02" "DUPLEX\0" \ 690 "b\x01" "SPEED\0" \ 691 "b\x00" "EN\0" 692 #define RXN_FRM_CTL_BITS \ 693 "\177" /* new format */ \ 694 "\020" /* hex display */ \ 695 "\020" /* %016x format */ \ 696 "b\x0a" "NULL_DIS\0" \ 697 "b\x09" "PRE_ALIGN\0" \ 698 "b\x08" "PAD_LEN\0" \ 699 "b\x07" "VLAN_LEN\0" \ 700 "b\x06" "PRE_FREE\0" \ 701 "b\x05" "CTL_SMAC\0" \ 702 "b\x04" "CTL_MCST\0" \ 703 "b\x03" "CTL_BCK\0" \ 704 "b\x02" "CTL_DRP\0" \ 705 "b\x01" "PRE_STRP\0" \ 706 "b\x00" "PRE_CHK\0" 707 #define RXN_FRM_CHK_BITS \ 708 "\177" /* new format */ \ 709 "\020" /* hex display */ \ 710 "\020" /* %016x format */ \ 711 "b\x09" "NIBERR\0" \ 712 "b\x08" "SKPERR\0" \ 713 "b\x07" "RCVERR\0" \ 714 "b\x06" "LENERR\0" \ 715 "b\x05" "ALNERR\0" \ 716 "b\x04" "FCSERR\0" \ 717 "b\x03" "JABBER\0" \ 718 "b\x02" "MAXERR\0" \ 719 "b\x01" "CAREXT\0" \ 720 "b\x00" "MINERR\0" 721 /* RXN_FRM_MIN */ 722 /* RXN_FRM_MAX */ 723 #define RXN_JABBER_BITS \ 724 "\177" /* new format */ \ 725 "\020" /* hex display */ \ 726 "\020" /* %016x format */ \ 727 "f\x00\x10" "CNT\0" 728 #define RXN_DECISION_BITS \ 729 "\177" /* new format */ \ 730 "\020" /* hex display */ \ 731 "\020" /* %016x format */ \ 732 "f\x00\x05" "CNT\0" 733 #define RXN_UDD_SKP_BITS \ 734 "\177" /* new format */ \ 735 "\020" /* hex display */ \ 736 "\020" /* %016x format */ \ 737 "b\x08" "FCSSEL\0" \ 738 "f\x00\x07" "LEN\0" 739 #define RXN_STATS_CTL_BITS \ 740 "\177" /* new format */ \ 741 "\020" /* hex display */ \ 742 "\020" /* %016x format */ \ 743 "b\x00" "RD_CLR\0" 744 #define RXN_IFG_BITS \ 745 "\177" /* new format */ \ 746 "\020" /* hex display */ \ 747 "\020" /* %016x format */ \ 748 "f\x00\x04" "IFG\0" 749 #define RXN_RX_INBND_BITS \ 750 "\177" /* new format */ \ 751 "\020" /* hex display */ \ 752 "\020" /* %016x format */ \ 753 "b\x03" "DUPLEX\0" \ 754 "f\x01\x02" "SPEED\0" \ 755 "b\x00" "STATUS\0" 756 #define RXN_STATS_PKTS_BITS \ 757 "\177" /* new format */ \ 758 "\020" /* hex display */ \ 759 "\020" /* %016x format */ \ 760 "f\x00\x20" "CNT\0" 761 #define RXN_STATS_OCTS_BITS \ 762 "\177" /* new format */ \ 763 "\020" /* hex display */ \ 764 "\020" /* %016x format */ \ 765 "f\x00\x30" "CNT\0" 766 #define RXN_STATS_PKTS_CTL_BITS \ 767 "\177" /* new format */ \ 768 "\020" /* hex display */ \ 769 "\020" /* %016x format */ \ 770 "f\x00\x20" "CNT\0" 771 #define RXN_STATS_OCTS_CTL_BITS \ 772 "\177" /* new format */ \ 773 "\020" /* hex display */ \ 774 "\020" /* %016x format */ \ 775 "f\x00\x30" "CNT\0" 776 #define RXN_STATS_PKTS_DMAC_BITS \ 777 "\177" /* new format */ \ 778 "\020" /* hex display */ \ 779 "\020" /* %016x format */ \ 780 "f\x00\x20" "CNT\0" 781 #define RXN_STATS_OCTS_DMAC_BITS \ 782 "\177" /* new format */ \ 783 "\020" /* hex display */ \ 784 "\020" /* %016x format */ \ 785 "f\x00\x30" "CNT\0" 786 #define RXN_STATS_PKTS_DRP_BITS \ 787 "\177" /* new format */ \ 788 "\020" /* hex display */ \ 789 "\020" /* %016x format */ \ 790 "f\x00\x20" "CNT\0" 791 #define RXN_STATS_OCTS_DRP_BITS \ 792 "\177" /* new format */ \ 793 "\020" /* hex display */ \ 794 "\020" /* %016x format */ \ 795 "f\x00\x30" "CNT\0" 796 #define RXN_STATS_PKTS_BAD_BITS \ 797 "\177" /* new format */ \ 798 "\020" /* hex display */ \ 799 "\020" /* %016x format */ \ 800 "f\x00\x20" "CNT\0" 801 #define RXN_ADR_CTL_BITS \ 802 "\177" /* new format */ \ 803 "\020" /* hex display */ \ 804 "\020" /* %016x format */ \ 805 "b\x03" "CAM_MODE\0" \ 806 "f\x01\x02" "MCST\0" \ 807 "b\x00" "BCST\0" 808 #define RXN_ADR_CAM_EN_BITS \ 809 "\177" /* new format */ \ 810 "\020" /* hex display */ \ 811 "\020" /* %016x format */ \ 812 "f\x00\x08" "EN\0" 813 /* RXN_ADR_CAM0 */ 814 /* RXN_ADR_CAM1 */ 815 /* RXN_ADR_CAM2 */ 816 /* RXN_ADR_CAM3 */ 817 /* RXN_ADR_CAM4 */ 818 /* RXN_ADR_CAM5 */ 819 #define TXN_CLK_BITS \ 820 "\177" /* new format */ \ 821 "\020" /* hex display */ \ 822 "\020" /* %016x format */ \ 823 "f\x00\x06" "CLK_CNT\0" 824 #define TXN_THRESH_BITS \ 825 "\177" /* new format */ \ 826 "\020" /* hex display */ \ 827 "\020" /* %016x format */ \ 828 "f\x00\x06" "CNT\0" 829 #define TXN_APPEND_BITS \ 830 "\177" /* new format */ \ 831 "\020" /* hex display */ \ 832 "\020" /* %016x format */ \ 833 "b\x03" "FORCE_FCS\0" \ 834 "b\x02" "FCS\0" \ 835 "b\x01" "PAD\0" \ 836 "b\x00" "PREAMBLE\0" 837 #define TXN_SLOT_BITS \ 838 "\177" /* new format */ \ 839 "\020" /* hex display */ \ 840 "\020" /* %016x format */ \ 841 "f\x00\x0a" "SLOT\0" 842 #define TXN_BURST_BITS \ 843 "\177" /* new format */ \ 844 "\020" /* hex display */ \ 845 "\020" /* %016x format */ \ 846 "f\x00\x10" "BURST\0" 847 /* SMAC0 */ 848 #define TXN_PAUSE_PKT_TIME_BITS \ 849 "\177" /* new format */ \ 850 "\020" /* hex display */ \ 851 "\020" /* %016x format */ \ 852 "f\x00\x10" "TIME\0" 853 #define TXN_MIN_PKT_BITS \ 854 "\177" /* new format */ \ 855 "\020" /* hex display */ \ 856 "\020" /* %016x format */ \ 857 "f\x00\x08" "MIN_SIZE\0" 858 #define TXN_PAUSE_PKT_INTERVAL_BITS \ 859 "\177" /* new format */ \ 860 "\020" /* hex display */ \ 861 "\020" /* %016x format */ \ 862 "f\x00\x10" "INTERVAL\0" 863 #define TXN_SOFT_PAUSE_BITS \ 864 "\177" /* new format */ \ 865 "\020" /* hex display */ \ 866 "\020" /* %016x format */ \ 867 "f\x00\x10" "TIME\0" 868 #define TXN_PAUSE_TOGO_BITS \ 869 "\177" /* new format */ \ 870 "\020" /* hex display */ \ 871 "\020" /* %016x format */ \ 872 "f\x00\x10" "TIME\0" 873 #define TXN_PAUSE_ZERO_BITS \ 874 "\177" /* new format */ \ 875 "\020" /* hex display */ \ 876 "\020" /* %016x format */ \ 877 "b\x00" "SEND\0" 878 #define TXN_STATS_CTL_BITS \ 879 "\177" /* new format */ \ 880 "\020" /* hex display */ \ 881 "\020" /* %016x format */ \ 882 "b\x00" "RD_CLR\0" 883 #define TXN_CTL_BITS \ 884 "\177" /* new format */ \ 885 "\020" /* hex display */ \ 886 "\020" /* %016x format */ \ 887 "b\x01" "XSDEF_EN\0" \ 888 "b\x00" "XSCOL_EN\0" 889 #define TXN_STAT0_BITS \ 890 "\177" /* new format */ \ 891 "\020" /* hex display */ \ 892 "\020" /* %016x format */ \ 893 "f\x20\x20" "XSDEF\0" \ 894 "f\x00\x20" "XSCOL\0" 895 #define TXN_STAT1_BITS \ 896 "\177" /* new format */ \ 897 "\020" /* hex display */ \ 898 "\020" /* %016x format */ \ 899 "f\x20\x20" "SCOL\0" \ 900 "f\x00\x20" "MSCOL\0" 901 #define TXN_STAT2_BITS \ 902 "\177" /* new format */ \ 903 "\020" /* hex display */ \ 904 "\020" /* %016x format */ \ 905 "f\x00\x30" "OCTS\0" 906 #define TXN_STAT3_BITS \ 907 "\177" /* new format */ \ 908 "\020" /* hex display */ \ 909 "\020" /* %016x format */ \ 910 "f\x00\x20" "PKTS\0" 911 #define TXN_STAT4_BITS \ 912 "\177" /* new format */ \ 913 "\020" /* hex display */ \ 914 "\020" /* %016x format */ \ 915 "f\x20\x20" "HIST1\0" \ 916 "f\x00\x20" "HIST0\0" 917 #define TXN_STAT5_BITS \ 918 "\177" /* new format */ \ 919 "\020" /* hex display */ \ 920 "\020" /* %016x format */ \ 921 "f\x20\x20" "HIST3\0" \ 922 "f\x00\x20" "HIST2\0" 923 #define TXN_STAT6_BITS \ 924 "\177" /* new format */ \ 925 "\020" /* hex display */ \ 926 "\020" /* %016x format */ \ 927 "f\x20\x20" "HIST5\0" \ 928 "f\x00\x20" "HIST4\0" 929 #define TXN_STAT7_BITS \ 930 "\177" /* new format */ \ 931 "\020" /* hex display */ \ 932 "\020" /* %016x format */ \ 933 "f\x20\x20" "HIST7\0" \ 934 "f\x00\x20" "HIST6\0" 935 #define TXN_STAT8_BITS \ 936 "\177" /* new format */ \ 937 "\020" /* hex display */ \ 938 "\020" /* %016x format */ \ 939 "f\x20\x20" "MCST\0" \ 940 "f\x00\x20" "BCST\0" 941 #define TXN_STAT9_BITS \ 942 "\177" /* new format */ \ 943 "\020" /* hex display */ \ 944 "\020" /* %016x format */ \ 945 "f\x20\x20" "UNDFLW\0" \ 946 "f\x00\x20" "CTL\0" 947 /* BIST0 */ 948 #define RX_PRTS_BITS \ 949 "\177" /* new format */ \ 950 "\020" /* hex display */ \ 951 "\020" /* %016x format */ \ 952 "f\x00\x03" "PRTS\0" 953 #define RX_BP_DROPN_BITS \ 954 "\177" /* new format */ \ 955 "\020" /* hex display */ \ 956 "\020" /* %016x format */ \ 957 "f\x00\x06" "MARK\0" 958 #define RX_BP_ONN_BITS \ 959 "\177" /* new format */ \ 960 "\020" /* hex display */ \ 961 "\020" /* %016x format */ \ 962 "f\x00\x09" "MARK\0" 963 #define RX_BP_OFFN_BITS \ 964 "\177" /* new format */ \ 965 "\020" /* hex display */ \ 966 "\020" /* %016x format */ \ 967 "f\x00\x06" "MARK\0" 968 #define TX_PRTS_BITS \ 969 "\177" /* new format */ \ 970 "\020" /* hex display */ \ 971 "\020" /* %016x format */ \ 972 "f\x00\x05" "PRTS\0" 973 #define TX_IFG_BITS \ 974 "\177" /* new format */ \ 975 "\020" /* hex display */ \ 976 "\020" /* %016x format */ \ 977 "f\x04\x04" "IFG2\0" \ 978 "f\x00\x04" "IFG1\0" 979 #define TX_JAM_BITS \ 980 "\177" /* new format */ \ 981 "\020" /* hex display */ \ 982 "\020" /* %016x format */ \ 983 "f\x00\x08" "JAM\0" 984 #define TX_COL_ATTEMPT_BITS \ 985 "\177" /* new format */ \ 986 "\020" /* hex display */ \ 987 "\020" /* %016x format */ \ 988 "f\x00\x05" "LIMIT\0" 989 #define TX_PAUSE_PKT_DMAC_BITS \ 990 "\177" /* new format */ \ 991 "\020" /* hex display */ \ 992 "\020" /* %016x format */ \ 993 "f\x00\x30" "DMAC\0" 994 #define TX_PAUSE_PKT_TYPE_BITS \ 995 "\177" /* new format */ \ 996 "\020" /* hex display */ \ 997 "\020" /* %016x format */ \ 998 "f\x00\x10" "TYPE\0" 999 #define TX_OVR_BP_BITS \ 1000 "\177" /* new format */ \ 1001 "\020" /* hex display */ \ 1002 "\020" /* %016x format */ \ 1003 "f\x08\x03" "EN\0" \ 1004 "f\x04\x03" "BP\0" \ 1005 "f\x00\x03" "IGN_FULL\0" 1006 #define TX_BP_BITS \ 1007 "\177" /* new format */ \ 1008 "\020" /* hex display */ \ 1009 "\020" /* %016x format */ \ 1010 "f\x00\x03" "SR_BP\0" 1011 #define TX_CORRUPT_BITS \ 1012 "\177" /* new format */ \ 1013 "\020" /* hex display */ \ 1014 "\020" /* %016x format */ \ 1015 "f\x00\x03" "CORRUPT\0" 1016 #define RX_PRT_INFO_BITS \ 1017 "\177" /* new format */ \ 1018 "\020" /* hex display */ \ 1019 "\020" /* %016x format */ \ 1020 "f\x10\x03" "DROP\0" \ 1021 "f\x00\x03" "COMMIT\0" 1022 #define TX_LFSR_BITS \ 1023 "\177" /* new format */ \ 1024 "\020" /* hex display */ \ 1025 "\020" /* %016x format */ \ 1026 "f\x00\x10" "LFSR\0" 1027 #define TX_INT_REG_BITS \ 1028 "\177" /* new format */ \ 1029 "\020" /* hex display */ \ 1030 "\020" /* %016x format */ \ 1031 "f\x10\x03" "LATE_COL\0" \ 1032 "f\x0c\x03" "XSDEF\0" \ 1033 "f\x08\x03" "XSCOL\0" \ 1034 "f\x02\x03" "UNDFLW\0" \ 1035 "b\x00" "PKO_NXA\0" 1036 #define TX_INT_EN_BITS \ 1037 "\177" /* new format */ \ 1038 "\020" /* hex display */ \ 1039 "\020" /* %016x format */ \ 1040 "f\x10\x03" "LATE_COL\0" \ 1041 "f\x0c\x03" "XSDEF\0" \ 1042 "f\x08\x03" "XSCOL\0" \ 1043 "f\x02\x03" "UNDFLW\0" \ 1044 "b\x00" "PKO_NXA\0" 1045 #define NXA_ADR_BITS \ 1046 "\177" /* new format */ \ 1047 "\020" /* hex display */ \ 1048 "\020" /* %016x format */ \ 1049 "f\x00\x06" "PRT\0" 1050 #define BAD_REG_BITS \ 1051 "\177" /* new format */ \ 1052 "\020" /* hex display */ \ 1053 "\020" /* %016x format */ \ 1054 "f\x1b\x04" "INB_NXA\0" \ 1055 "b\x1a" "STATOVR\0" \ 1056 "f\x16\x03" "LOSTSTAT\0" \ 1057 "f\x02\x03" "OUT_OVR\0" 1058 #define STAT_BP_BITS \ 1059 "\177" /* new format */ \ 1060 "\020" /* hex display */ \ 1061 "\020" /* %016x format */ \ 1062 "b\x10" "BP\0" \ 1063 "f\x00\x10" "CNT\0" 1064 #define TX_CLK_MSKN_BITS \ 1065 "\177" /* new format */ \ 1066 "\020" /* hex display */ \ 1067 "\020" /* %016x format */ \ 1068 "b\x00" "MSK\0" 1069 #define RX_TX_STATUS_BITS \ 1070 "\177" /* new format */ \ 1071 "\020" /* hex display */ \ 1072 "\020" /* %016x format */ \ 1073 "f\x04\x03" "TX\0" \ 1074 "f\x00\x03" "RX\0" 1075 #define INF_MODE_BITS \ 1076 "\177" /* new format */ \ 1077 "\020" /* hex display */ \ 1078 "\020" /* %016x format */ \ 1079 "b\x02" "P0MII\0" \ 1080 "b\x01" "EN\0" \ 1081 "b\x00" "TYPE\0" 1082 1083 #define GMX0_RX0_INT_REG_BITS RXN_INT_REG_BITS 1084 #define GMX0_RX0_INT_EN_BITS RXN_INT_EN_BITS 1085 #define GMX0_PRT0_CFG_BITS PRTN_CFG_BITS 1086 #define GMX0_RX0_FRM_CTL_BITS RXN_FRM_CTL_BITS 1087 #define GMX0_RX0_FRM_CHK_BITS RXN_FRM_CHK_BITS 1088 #define GMX0_RX0_FRM_MIN_BITS NULL//RXN_FRM_MIN_BITS 1089 #define GMX0_RX0_FRM_MAX_BITS NULL//RXN_FRM_MAX_BITS 1090 #define GMX0_RX0_JABBER_BITS RXN_JABBER_BITS 1091 #define GMX0_RX0_DECISION_BITS RXN_DECISION_BITS 1092 #define GMX0_RX0_UDD_SKP_BITS RXN_UDD_SKP_BITS 1093 #define GMX0_RX0_STATS_CTL_BITS RXN_STATS_CTL_BITS 1094 #define GMX0_RX0_IFG_BITS RXN_IFG_BITS 1095 #define GMX0_RX0_RX_INBND_BITS RXN_RX_INBND_BITS 1096 #define GMX0_RX0_STATS_PKTS_BITS RXN_STATS_PKTS_BITS 1097 #define GMX0_RX0_STATS_OCTS_BITS RXN_STATS_OCTS_BITS 1098 #define GMX0_RX0_STATS_PKTS_CTL_BITS RXN_STATS_PKTS_CTL_BITS 1099 #define GMX0_RX0_STATS_OCTS_CTL_BITS RXN_STATS_OCTS_CTL_BITS 1100 #define GMX0_RX0_STATS_PKTS_DMAC_BITS RXN_STATS_PKTS_DMAC_BITS 1101 #define GMX0_RX0_STATS_OCTS_DMAC_BITS RXN_STATS_OCTS_DMAC_BITS 1102 #define GMX0_RX0_STATS_PKTS_DRP_BITS RXN_STATS_PKTS_DRP_BITS 1103 #define GMX0_RX0_STATS_OCTS_DRP_BITS RXN_STATS_OCTS_DRP_BITS 1104 #define GMX0_RX0_STATS_PKTS_BAD_BITS RXN_STATS_PKTS_BAD_BITS 1105 #define GMX0_RX0_ADR_CTL_BITS RXN_ADR_CTL_BITS 1106 #define GMX0_RX0_ADR_CAM_EN_BITS RXN_ADR_CAM_EN_BITS 1107 #define GMX0_RX0_ADR_CAM0_BITS NULL//RXN_ADR_CAM0_BITS 1108 #define GMX0_RX0_ADR_CAM1_BITS NULL//RXN_ADR_CAM1_BITS 1109 #define GMX0_RX0_ADR_CAM2_BITS NULL//RXN_ADR_CAM2_BITS 1110 #define GMX0_RX0_ADR_CAM3_BITS NULL//RXN_ADR_CAM3_BITS 1111 #define GMX0_RX0_ADR_CAM4_BITS NULL//RXN_ADR_CAM4_BITS 1112 #define GMX0_RX0_ADR_CAM5_BITS NULL//RXN_ADR_CAM5_BITS 1113 #define GMX0_TX0_CLK_BITS TXN_CLK_BITS 1114 #define GMX0_TX0_THRESH_BITS TXN_THRESH_BITS 1115 #define GMX0_TX0_APPEND_BITS TXN_APPEND_BITS 1116 #define GMX0_TX0_SLOT_BITS TXN_SLOT_BITS 1117 #define GMX0_TX0_BURST_BITS TXN_BURST_BITS 1118 #define GMX0_SMAC0_BITS NULL//SMAC0_BITS 1119 #define GMX0_TX0_PAUSE_PKT_TIME_BITS TXN_PAUSE_PKT_TIME_BITS 1120 #define GMX0_TX0_MIN_PKT_BITS TXN_MIN_PKT_BITS 1121 #define GMX0_TX0_PAUSE_PKT_INTERVAL_BITS TXN_PAUSE_PKT_INTERVAL_BITS 1122 #define GMX0_TX0_SOFT_PAUSE_BITS TXN_SOFT_PAUSE_BITS 1123 #define GMX0_TX0_PAUSE_TOGO_BITS TXN_PAUSE_TOGO_BITS 1124 #define GMX0_TX0_PAUSE_ZERO_BITS TXN_PAUSE_ZERO_BITS 1125 #define GMX0_TX0_STATS_CTL_BITS TXN_STATS_CTL_BITS 1126 #define GMX0_TX0_CTL_BITS TXN_CTL_BITS 1127 #define GMX0_TX0_STAT0_BITS TXN_STAT0_BITS 1128 #define GMX0_TX0_STAT1_BITS TXN_STAT1_BITS 1129 #define GMX0_TX0_STAT2_BITS TXN_STAT2_BITS 1130 #define GMX0_TX0_STAT3_BITS TXN_STAT3_BITS 1131 #define GMX0_TX0_STAT4_BITS TXN_STAT4_BITS 1132 #define GMX0_TX0_STAT5_BITS TXN_STAT5_BITS 1133 #define GMX0_TX0_STAT6_BITS TXN_STAT6_BITS 1134 #define GMX0_TX0_STAT7_BITS TXN_STAT7_BITS 1135 #define GMX0_TX0_STAT8_BITS TXN_STAT8_BITS 1136 #define GMX0_TX0_STAT9_BITS TXN_STAT9_BITS 1137 #define GMX0_BIST0_BITS NULL//BIST0_BITS 1138 #define GMX0_RX_PRTS_BITS RX_PRTS_BITS 1139 #define GMX0_RX_BP_DROP0_BITS RX_BP_DROPN_BITS 1140 #define GMX0_RX_BP_ON0_BITS RX_BP_ONN_BITS 1141 #define GMX0_RX_BP_OFF0_BITS RX_BP_OFFN_BITS 1142 #define GMX0_RX_BP_DROP1_BITS RX_BP_DROPN_BITS 1143 #define GMX0_RX_BP_ON1_BITS RX_BP_ONN_BITS 1144 #define GMX0_RX_BP_OFF1_BITS RX_BP_OFFN_BITS 1145 #define GMX0_RX_BP_DROP2_BITS RX_BP_DROPN_BITS 1146 #define GMX0_RX_BP_ON2_BITS RX_BP_ONN_BITS 1147 #define GMX0_RX_BP_OFF2_BITS RX_BP_OFFN_BITS 1148 #define GMX0_TX_PRTS_BITS TX_PRTS_BITS 1149 #define GMX0_TX_IFG_BITS TX_IFG_BITS 1150 #define GMX0_TX_JAM_BITS TX_JAM_BITS 1151 #define GMX0_TX_COL_ATTEMPT_BITS TX_COL_ATTEMPT_BITS 1152 #define GMX0_TX_PAUSE_PKT_DMAC_BITS TX_PAUSE_PKT_DMAC_BITS 1153 #define GMX0_TX_PAUSE_PKT_TYPE_BITS TX_PAUSE_PKT_TYPE_BITS 1154 #define GMX0_TX_OVR_BP_BITS TX_OVR_BP_BITS 1155 #define GMX0_TX_BP_BITS TX_BP_BITS 1156 #define GMX0_TX_CORRUPT_BITS TX_CORRUPT_BITS 1157 #define GMX0_RX_PRT_INFO_BITS RX_PRT_INFO_BITS 1158 #define GMX0_TX_LFSR_BITS TX_LFSR_BITS 1159 #define GMX0_TX_INT_REG_BITS TX_INT_REG_BITS 1160 #define GMX0_TX_INT_EN_BITS TX_INT_EN_BITS 1161 #define GMX0_NXA_ADR_BITS NXA_ADR_BITS 1162 #define GMX0_BAD_REG_BITS BAD_REG_BITS 1163 #define GMX0_STAT_BP_BITS STAT_BP_BITS 1164 #define GMX0_TX_CLK_MSK0_BITS TX_CLK_MSKN_BITS 1165 #define GMX0_TX_CLK_MSK1_BITS TX_CLK_MSKN_BITS 1166 #define GMX0_TX_CLK_MSK2_BITS TX_CLK_MSKN_BITS 1167 #define GMX0_RX_TX_STATUS_BITS RX_TX_STATUS_BITS 1168 #define GMX0_INF_MODE_BITS INF_MODE_BITS 1169 1170 #endif /* _OCTEON_GMXREG_H_ */ 1171
Indexes created Mon Sep 29 21:09:56 GMT 2025