octeon_ipd.c revision 1.2.2.2
1 1.2.2.2 skrll /* $NetBSD: octeon_ipd.c,v 1.2.2.2 2015/06/06 14:40:01 skrll Exp $ */ 2 1.2.2.2 skrll 3 1.2.2.2 skrll /* 4 1.2.2.2 skrll * Copyright (c) 2007 Internet Initiative Japan, Inc. 5 1.2.2.2 skrll * All rights reserved. 6 1.2.2.2 skrll * 7 1.2.2.2 skrll * Redistribution and use in source and binary forms, with or without 8 1.2.2.2 skrll * modification, are permitted provided that the following conditions 9 1.2.2.2 skrll * are met: 10 1.2.2.2 skrll * 1. Redistributions of source code must retain the above copyright 11 1.2.2.2 skrll * notice, this list of conditions and the following disclaimer. 12 1.2.2.2 skrll * 2. Redistributions in binary form must reproduce the above copyright 13 1.2.2.2 skrll * notice, this list of conditions and the following disclaimer in the 14 1.2.2.2 skrll * documentation and/or other materials provided with the distribution. 15 1.2.2.2 skrll * 16 1.2.2.2 skrll * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 17 1.2.2.2 skrll * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 1.2.2.2 skrll * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 1.2.2.2 skrll * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 20 1.2.2.2 skrll * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 1.2.2.2 skrll * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 1.2.2.2 skrll * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 1.2.2.2 skrll * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 1.2.2.2 skrll * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 1.2.2.2 skrll * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 1.2.2.2 skrll * SUCH DAMAGE. 27 1.2.2.2 skrll */ 28 1.2.2.2 skrll 29 1.2.2.2 skrll #include <sys/cdefs.h> 30 1.2.2.2 skrll __KERNEL_RCSID(0, "$NetBSD: octeon_ipd.c,v 1.2.2.2 2015/06/06 14:40:01 skrll Exp $"); 31 1.2.2.2 skrll 32 1.2.2.2 skrll #include "opt_octeon.h" 33 1.2.2.2 skrll 34 1.2.2.2 skrll #include "opt_octeon.h" 35 1.2.2.2 skrll 36 1.2.2.2 skrll #include <sys/param.h> 37 1.2.2.2 skrll #include <sys/systm.h> 38 1.2.2.2 skrll #include <sys/malloc.h> 39 1.2.2.2 skrll #include <sys/mbuf.h> 40 1.2.2.2 skrll #include <mips/locore.h> 41 1.2.2.2 skrll #include <mips/cavium/octeonvar.h> 42 1.2.2.2 skrll #include <mips/cavium/dev/octeon_ciureg.h> 43 1.2.2.2 skrll #include <mips/cavium/dev/octeon_fpavar.h> 44 1.2.2.2 skrll #include <mips/cavium/dev/octeon_pipreg.h> 45 1.2.2.2 skrll #include <mips/cavium/dev/octeon_ipdreg.h> 46 1.2.2.2 skrll #include <mips/cavium/dev/octeon_ipdvar.h> 47 1.2.2.2 skrll 48 1.2.2.2 skrll #include <netinet/in.h> 49 1.2.2.2 skrll #include <netinet/in_systm.h> 50 1.2.2.2 skrll #include <netinet/ip.h> 51 1.2.2.2 skrll 52 1.2.2.2 skrll #define IP_OFFSET(data, word2) \ 53 1.2.2.2 skrll ((uintptr_t)(data) + (uintptr_t)((word2 & PIP_WQE_WORD2_IP_OFFSET) >> PIP_WQE_WORD2_IP_OFFSET_SHIFT)) 54 1.2.2.2 skrll 55 1.2.2.2 skrll #ifdef OCTEON_ETH_DEBUG 56 1.2.2.2 skrll void octeon_ipd_intr_evcnt_attach(struct octeon_ipd_softc *); 57 1.2.2.2 skrll void octeon_ipd_intr_rml(void *); 58 1.2.2.2 skrll int octeon_ipd_intr_drop(void *); 59 1.2.2.2 skrll 60 1.2.2.2 skrll void octeon_ipd_dump(void); 61 1.2.2.2 skrll 62 1.2.2.2 skrll static void *octeon_ipd_intr_drop_ih; 63 1.2.2.2 skrll struct evcnt octeon_ipd_intr_drop_evcnt = 64 1.2.2.2 skrll EVCNT_INITIALIZER(EVCNT_TYPE_INTR, NULL, "octeon", 65 1.2.2.2 skrll "ipd drop intr"); 66 1.2.2.2 skrll EVCNT_ATTACH_STATIC(octeon_ipd_intr_drop_evcnt); 67 1.2.2.2 skrll 68 1.2.2.2 skrll struct octeon_ipd_softc *__octeon_ipd_softc[3/* XXX */]; 69 1.2.2.2 skrll #endif 70 1.2.2.2 skrll 71 1.2.2.2 skrll /* XXX */ 72 1.2.2.2 skrll void 73 1.2.2.2 skrll octeon_ipd_init(struct octeon_ipd_attach_args *aa, 74 1.2.2.2 skrll struct octeon_ipd_softc **rsc) 75 1.2.2.2 skrll { 76 1.2.2.2 skrll struct octeon_ipd_softc *sc; 77 1.2.2.2 skrll int status; 78 1.2.2.2 skrll 79 1.2.2.2 skrll sc = malloc(sizeof(*sc), M_DEVBUF, M_WAITOK | M_ZERO); 80 1.2.2.2 skrll if (sc == NULL) 81 1.2.2.2 skrll panic("can't allocate memory: %s", __func__); 82 1.2.2.2 skrll 83 1.2.2.2 skrll sc->sc_port = aa->aa_port; 84 1.2.2.2 skrll sc->sc_regt = aa->aa_regt; 85 1.2.2.2 skrll sc->sc_first_mbuff_skip = aa->aa_first_mbuff_skip; 86 1.2.2.2 skrll sc->sc_not_first_mbuff_skip = aa->aa_not_first_mbuff_skip; 87 1.2.2.2 skrll 88 1.2.2.2 skrll status = bus_space_map(sc->sc_regt, IPD_BASE, IPD_SIZE, 0, 89 1.2.2.2 skrll &sc->sc_regh); 90 1.2.2.2 skrll if (status != 0) 91 1.2.2.2 skrll panic("can't map %s space", "ipd register"); 92 1.2.2.2 skrll 93 1.2.2.2 skrll *rsc = sc; 94 1.2.2.2 skrll 95 1.2.2.2 skrll #ifdef OCTEON_ETH_DEBUG 96 1.2.2.2 skrll octeon_ipd_int_enable(sc, 1); 97 1.2.2.2 skrll octeon_ipd_intr_evcnt_attach(sc); 98 1.2.2.2 skrll if (octeon_ipd_intr_drop_ih == NULL) 99 1.2.2.2 skrll octeon_ipd_intr_drop_ih = octeon_intr_establish( 100 1.2.2.2 skrll ffs64(CIU_INTX_SUM0_IPD_DRP) - 1, IPL_NET, 101 1.2.2.2 skrll octeon_ipd_intr_drop, NULL); 102 1.2.2.2 skrll __octeon_ipd_softc[sc->sc_port] = sc; 103 1.2.2.2 skrll #endif /* OCTEON_ETH_DEBUG */ 104 1.2.2.2 skrll } 105 1.2.2.2 skrll 106 1.2.2.2 skrll #define _IPD_RD8(sc, off) \ 107 1.2.2.2 skrll bus_space_read_8((sc)->sc_regt, (sc)->sc_regh, (off)) 108 1.2.2.2 skrll #define _IPD_WR8(sc, off, v) \ 109 1.2.2.2 skrll bus_space_write_8((sc)->sc_regt, (sc)->sc_regh, (off), (v)) 110 1.2.2.2 skrll 111 1.2.2.2 skrll int 112 1.2.2.2 skrll octeon_ipd_enable(struct octeon_ipd_softc *sc) 113 1.2.2.2 skrll { 114 1.2.2.2 skrll uint64_t ctl_status; 115 1.2.2.2 skrll 116 1.2.2.2 skrll ctl_status = _IPD_RD8(sc, IPD_CTL_STATUS_OFFSET); 117 1.2.2.2 skrll SET(ctl_status, IPD_CTL_STATUS_IPD_EN); 118 1.2.2.2 skrll _IPD_WR8(sc, IPD_CTL_STATUS_OFFSET, ctl_status); 119 1.2.2.2 skrll 120 1.2.2.2 skrll return 0; 121 1.2.2.2 skrll } 122 1.2.2.2 skrll 123 1.2.2.2 skrll int 124 1.2.2.2 skrll octeon_ipd_config(struct octeon_ipd_softc *sc) 125 1.2.2.2 skrll { 126 1.2.2.2 skrll uint64_t first_mbuff_skip; 127 1.2.2.2 skrll uint64_t not_first_mbuff_skip; 128 1.2.2.2 skrll uint64_t packet_mbuff_size; 129 1.2.2.2 skrll uint64_t first_next_ptr_back; 130 1.2.2.2 skrll uint64_t second_next_ptr_back; 131 1.2.2.2 skrll uint64_t sqe_fpa_queue; 132 1.2.2.2 skrll uint64_t ctl_status; 133 1.2.2.2 skrll 134 1.2.2.2 skrll /* XXX XXX XXX */ 135 1.2.2.2 skrll first_mbuff_skip = 0; 136 1.2.2.2 skrll SET(first_mbuff_skip, (sc->sc_first_mbuff_skip / 8) & IPD_1ST_MBUFF_SKIP_SZ); 137 1.2.2.2 skrll _IPD_WR8(sc, IPD_1ST_MBUFF_SKIP_OFFSET, first_mbuff_skip); 138 1.2.2.2 skrll /* XXX XXX XXX */ 139 1.2.2.2 skrll 140 1.2.2.2 skrll /* XXX XXX XXX */ 141 1.2.2.2 skrll not_first_mbuff_skip = 0; 142 1.2.2.2 skrll SET(not_first_mbuff_skip, (sc->sc_not_first_mbuff_skip / 8) & 143 1.2.2.2 skrll IPD_NOT_1ST_MBUFF_SKIP_SZ); 144 1.2.2.2 skrll _IPD_WR8(sc, IPD_NOT_1ST_MBUFF_SKIP_OFFSET, not_first_mbuff_skip); 145 1.2.2.2 skrll /* XXX XXX XXX */ 146 1.2.2.2 skrll 147 1.2.2.2 skrll packet_mbuff_size = 0; 148 1.2.2.2 skrll SET(packet_mbuff_size, (FPA_RECV_PKT_POOL_SIZE / 8) & 149 1.2.2.2 skrll IPD_PACKET_MBUFF_SIZE_MB_SIZE); 150 1.2.2.2 skrll _IPD_WR8(sc, IPD_PACKET_MBUFF_SIZE_OFFSET, packet_mbuff_size); 151 1.2.2.2 skrll 152 1.2.2.2 skrll first_next_ptr_back = 0; 153 1.2.2.2 skrll SET(first_next_ptr_back, (sc->sc_first_mbuff_skip / 128) & IPD_1ST_NEXT_PTR_BACK_BACK); 154 1.2.2.2 skrll _IPD_WR8(sc, IPD_1ST_NEXT_PTR_BACK_OFFSET, first_next_ptr_back); 155 1.2.2.2 skrll 156 1.2.2.2 skrll second_next_ptr_back = 0; 157 1.2.2.2 skrll SET(second_next_ptr_back, (sc->sc_not_first_mbuff_skip / 128) & 158 1.2.2.2 skrll IPD_2ND_NEXT_PTR_BACK_BACK); 159 1.2.2.2 skrll _IPD_WR8(sc, IPD_2ND_NEXT_PTR_BACK_OFFSET, second_next_ptr_back); 160 1.2.2.2 skrll 161 1.2.2.2 skrll sqe_fpa_queue = 0; 162 1.2.2.2 skrll SET(sqe_fpa_queue, FPA_WQE_POOL & IPD_WQE_FPA_QUEUE_WQE_QUE); 163 1.2.2.2 skrll _IPD_WR8(sc, IPD_WQE_FPA_QUEUE_OFFSET, sqe_fpa_queue); 164 1.2.2.2 skrll 165 1.2.2.2 skrll ctl_status = _IPD_RD8(sc, IPD_CTL_STATUS_OFFSET); 166 1.2.2.2 skrll CLR(ctl_status, IPD_CTL_STATUS_OPC_MODE); 167 1.2.2.2 skrll SET(ctl_status, IPD_CTL_STATUS_OPC_MODE_ALL); 168 1.2.2.2 skrll SET(ctl_status, IPD_CTL_STATUS_PBP_EN); 169 1.2.2.2 skrll 170 1.2.2.2 skrll /* 171 1.2.2.2 skrll * XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX 172 1.2.2.2 skrll * from SDK 173 1.2.2.2 skrll * SET(ctl_status, IPD_CTL_STATUS_LEN_M8); 174 1.2.2.2 skrll * XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX 175 1.2.2.2 skrll */ 176 1.2.2.2 skrll 177 1.2.2.2 skrll _IPD_WR8(sc, IPD_CTL_STATUS_OFFSET, ctl_status); 178 1.2.2.2 skrll 179 1.2.2.2 skrll return 0; 180 1.2.2.2 skrll } 181 1.2.2.2 skrll 182 1.2.2.2 skrll /* 183 1.2.2.2 skrll * octeon work queue entry offload 184 1.2.2.2 skrll * L3 error & L4 error 185 1.2.2.2 skrll */ 186 1.2.2.2 skrll void 187 1.2.2.2 skrll octeon_ipd_offload(uint64_t word2, void *data, int *rcflags) 188 1.2.2.2 skrll { 189 1.2.2.2 skrll int cflags; 190 1.2.2.2 skrll 191 1.2.2.2 skrll if (ISSET(word2, PIP_WQE_WORD2_IP_NI)) 192 1.2.2.2 skrll return; 193 1.2.2.2 skrll 194 1.2.2.2 skrll cflags = 0; 195 1.2.2.2 skrll 196 1.2.2.2 skrll if (!ISSET(word2, PIP_WQE_WORD2_IP_V6)) 197 1.2.2.2 skrll SET(cflags, M_CSUM_IPv4); 198 1.2.2.2 skrll 199 1.2.2.2 skrll if (ISSET(word2, PIP_WQE_WORD2_IP_TU)) { 200 1.2.2.2 skrll SET(cflags, 201 1.2.2.2 skrll !ISSET(word2, PIP_WQE_WORD2_IP_V6) ? 202 1.2.2.2 skrll (M_CSUM_TCPv4 | M_CSUM_UDPv4) : 203 1.2.2.2 skrll (M_CSUM_TCPv6 | M_CSUM_UDPv6)); 204 1.2.2.2 skrll } 205 1.2.2.2 skrll 206 1.2.2.2 skrll /* check L3 (IP) error */ 207 1.2.2.2 skrll if (ISSET(word2, PIP_WQE_WORD2_IP_IE)) { 208 1.2.2.2 skrll struct ip *ip; 209 1.2.2.2 skrll 210 1.2.2.2 skrll switch (word2 & PIP_WQE_WORD2_IP_OPECODE) { 211 1.2.2.2 skrll case IPD_WQE_L3_V4_CSUM_ERR: 212 1.2.2.2 skrll /* CN31XX Pass 1.1 Errata */ 213 1.2.2.2 skrll ip = (struct ip *)(IP_OFFSET(data, word2)); 214 1.2.2.2 skrll if (ip->ip_hl == 5) 215 1.2.2.2 skrll SET(cflags, M_CSUM_IPv4_BAD); 216 1.2.2.2 skrll break; 217 1.2.2.2 skrll default: 218 1.2.2.2 skrll break; 219 1.2.2.2 skrll } 220 1.2.2.2 skrll } 221 1.2.2.2 skrll 222 1.2.2.2 skrll /* check L4 (UDP / TCP) error */ 223 1.2.2.2 skrll if (ISSET(word2, PIP_WQE_WORD2_IP_LE)) { 224 1.2.2.2 skrll switch (word2 & PIP_WQE_WORD2_IP_OPECODE) { 225 1.2.2.2 skrll case IPD_WQE_L4_CSUM_ERR: 226 1.2.2.2 skrll SET(cflags, M_CSUM_TCP_UDP_BAD); 227 1.2.2.2 skrll break; 228 1.2.2.2 skrll default: 229 1.2.2.2 skrll break; 230 1.2.2.2 skrll } 231 1.2.2.2 skrll } 232 1.2.2.2 skrll 233 1.2.2.2 skrll *rcflags = cflags; 234 1.2.2.2 skrll } 235 1.2.2.2 skrll 236 1.2.2.2 skrll int 237 1.2.2.2 skrll octeon_ipd_red(struct octeon_ipd_softc *sc, uint64_t pass_thr, uint64_t drop_thr) 238 1.2.2.2 skrll { 239 1.2.2.2 skrll #if defined(OCTEON_ETH_IPD_RED) 240 1.2.2.2 skrll /* 241 1.2.2.2 skrll * no receive problem workaround. 242 1.2.2.2 skrll * if not set IPD RED pramaters, 243 1.2.2.2 skrll * may become unable to receive packet 244 1.2.2.2 skrll * on media mismatch environment 245 1.2.2.2 skrll * of self media 100-half duplex. 246 1.2.2.2 skrll */ 247 1.2.2.2 skrll uint64_t red_marks; 248 1.2.2.2 skrll uint64_t red_param; 249 1.2.2.2 skrll uint64_t red_port; 250 1.2.2.2 skrll 251 1.2.2.2 skrll red_marks = drop_thr << 32 /* XXX */ | pass_thr; 252 1.2.2.2 skrll _IPD_WR8(sc, IPD_QOS0_RED_MARKS_OFFSET, red_marks); 253 1.2.2.2 skrll _IPD_WR8(sc, IPD_QOS1_RED_MARKS_OFFSET, red_marks); 254 1.2.2.2 skrll _IPD_WR8(sc, IPD_QOS2_RED_MARKS_OFFSET, red_marks); 255 1.2.2.2 skrll _IPD_WR8(sc, IPD_QOS3_RED_MARKS_OFFSET, red_marks); 256 1.2.2.2 skrll _IPD_WR8(sc, IPD_QOS4_RED_MARKS_OFFSET, red_marks); 257 1.2.2.2 skrll _IPD_WR8(sc, IPD_QOS5_RED_MARKS_OFFSET, red_marks); 258 1.2.2.2 skrll _IPD_WR8(sc, IPD_QOS6_RED_MARKS_OFFSET, red_marks); 259 1.2.2.2 skrll _IPD_WR8(sc, IPD_QOS7_RED_MARKS_OFFSET, red_marks); 260 1.2.2.2 skrll red_param = 261 1.2.2.2 skrll ((255ull << 24 /* XXX */) / (pass_thr - drop_thr)) | 262 1.2.2.2 skrll 1ull << 32 /* XXX */ | 263 1.2.2.2 skrll 255ull << 40 /* XXX */ | 264 1.2.2.2 skrll 1ull << 48 /* XXX */; 265 1.2.2.2 skrll _IPD_WR8(sc, IPD_RED_QUE0_PARAM_OFFSET, red_param); 266 1.2.2.2 skrll _IPD_WR8(sc, IPD_RED_QUE1_PARAM_OFFSET, red_param); 267 1.2.2.2 skrll _IPD_WR8(sc, IPD_RED_QUE2_PARAM_OFFSET, red_param); 268 1.2.2.2 skrll _IPD_WR8(sc, IPD_RED_QUE3_PARAM_OFFSET, red_param); 269 1.2.2.2 skrll _IPD_WR8(sc, IPD_RED_QUE4_PARAM_OFFSET, red_param); 270 1.2.2.2 skrll _IPD_WR8(sc, IPD_RED_QUE5_PARAM_OFFSET, red_param); 271 1.2.2.2 skrll _IPD_WR8(sc, IPD_RED_QUE6_PARAM_OFFSET, red_param); 272 1.2.2.2 skrll _IPD_WR8(sc, IPD_RED_QUE7_PARAM_OFFSET, red_param); 273 1.2.2.2 skrll 274 1.2.2.2 skrll _IPD_WR8(sc, IPD_BP_PRT_RED_END_OFFSET, 0); 275 1.2.2.2 skrll 276 1.2.2.2 skrll red_port = 0xfffffffffull | 277 1.2.2.2 skrll 10000ull << 36 /* XXX */ | 278 1.2.2.2 skrll 10000ull << 50 /* XXX */; 279 1.2.2.2 skrll _IPD_WR8(sc, IPD_RED_PORT_ENABLE_OFFSET, red_port); 280 1.2.2.2 skrll #endif 281 1.2.2.2 skrll 282 1.2.2.2 skrll return 0; 283 1.2.2.2 skrll } 284 1.2.2.2 skrll 285 1.2.2.2 skrll void 286 1.2.2.2 skrll octeon_ipd_sub_port_fcs(struct octeon_ipd_softc *sc, int enable) 287 1.2.2.2 skrll { 288 1.2.2.2 skrll uint64_t sub_port_fcs; 289 1.2.2.2 skrll 290 1.2.2.2 skrll sub_port_fcs = _IPD_RD8(sc, IPD_SUB_PORT_FCS_OFFSET); 291 1.2.2.2 skrll if (enable == 0) 292 1.2.2.2 skrll CLR(sub_port_fcs, 1 << sc->sc_port); 293 1.2.2.2 skrll else 294 1.2.2.2 skrll SET(sub_port_fcs, 1 << sc->sc_port); 295 1.2.2.2 skrll _IPD_WR8(sc, IPD_SUB_PORT_FCS_OFFSET, sub_port_fcs); 296 1.2.2.2 skrll } 297 1.2.2.2 skrll 298 1.2.2.2 skrll #ifdef OCTEON_ETH_DEBUG 299 1.2.2.2 skrll int octeon_ipd_intr_rml_verbose; 300 1.2.2.2 skrll struct evcnt octeon_ipd_intr_evcnt; 301 1.2.2.2 skrll 302 1.2.2.2 skrll static const struct octeon_evcnt_entry octeon_ipd_intr_evcnt_entries[] = { 303 1.2.2.2 skrll #define _ENTRY(name, type, parent, descr) \ 304 1.2.2.2 skrll OCTEON_EVCNT_ENTRY(struct octeon_ipd_softc, name, type, parent, descr) 305 1.2.2.2 skrll _ENTRY(ipdbpsub, MISC, NULL, "ipd backpressure subtract"), 306 1.2.2.2 skrll _ENTRY(ipdprcpar3, MISC, NULL, "ipd parity error 127:96"), 307 1.2.2.2 skrll _ENTRY(ipdprcpar2, MISC, NULL, "ipd parity error 95:64"), 308 1.2.2.2 skrll _ENTRY(ipdprcpar1, MISC, NULL, "ipd parity error 63:32"), 309 1.2.2.2 skrll _ENTRY(ipdprcpar0, MISC, NULL, "ipd parity error 31:0"), 310 1.2.2.2 skrll #undef _ENTRY 311 1.2.2.2 skrll }; 312 1.2.2.2 skrll 313 1.2.2.2 skrll void 314 1.2.2.2 skrll octeon_ipd_intr_evcnt_attach(struct octeon_ipd_softc *sc) 315 1.2.2.2 skrll { 316 1.2.2.2 skrll OCTEON_EVCNT_ATTACH_EVCNTS(sc, octeon_ipd_intr_evcnt_entries, "ipd0"); 317 1.2.2.2 skrll } 318 1.2.2.2 skrll 319 1.2.2.2 skrll void 320 1.2.2.2 skrll octeon_ipd_intr_rml(void *arg) 321 1.2.2.2 skrll { 322 1.2.2.2 skrll int i; 323 1.2.2.2 skrll 324 1.2.2.2 skrll octeon_ipd_intr_evcnt.ev_count++; 325 1.2.2.2 skrll for (i = 0; i < 3/* XXX */; i++) { 326 1.2.2.2 skrll struct octeon_ipd_softc *sc; 327 1.2.2.2 skrll uint64_t reg; 328 1.2.2.2 skrll 329 1.2.2.2 skrll sc = __octeon_ipd_softc[i]; 330 1.2.2.2 skrll KASSERT(sc != NULL); 331 1.2.2.2 skrll reg = octeon_ipd_int_summary(sc); 332 1.2.2.2 skrll if (octeon_ipd_intr_rml_verbose) 333 1.2.2.2 skrll printf("%s: IPD_INT_SUM=0x%016" PRIx64 "\n", __func__, reg); 334 1.2.2.2 skrll if (reg & IPD_INT_SUM_BP_SUB) 335 1.2.2.2 skrll OCTEON_EVCNT_INC(sc, ipdbpsub); 336 1.2.2.2 skrll if (reg & IPD_INT_SUM_PRC_PAR3) 337 1.2.2.2 skrll OCTEON_EVCNT_INC(sc, ipdprcpar3); 338 1.2.2.2 skrll if (reg & IPD_INT_SUM_PRC_PAR2) 339 1.2.2.2 skrll OCTEON_EVCNT_INC(sc, ipdprcpar2); 340 1.2.2.2 skrll if (reg & IPD_INT_SUM_PRC_PAR1) 341 1.2.2.2 skrll OCTEON_EVCNT_INC(sc, ipdprcpar1); 342 1.2.2.2 skrll if (reg & IPD_INT_SUM_PRC_PAR0) 343 1.2.2.2 skrll OCTEON_EVCNT_INC(sc, ipdprcpar0); 344 1.2.2.2 skrll } 345 1.2.2.2 skrll } 346 1.2.2.2 skrll 347 1.2.2.2 skrll void 348 1.2.2.2 skrll octeon_ipd_int_enable(struct octeon_ipd_softc *sc, int enable) 349 1.2.2.2 skrll { 350 1.2.2.2 skrll uint64_t ipd_int_xxx = 0; 351 1.2.2.2 skrll 352 1.2.2.2 skrll SET(ipd_int_xxx, 353 1.2.2.2 skrll IPD_INT_SUM_BP_SUB | 354 1.2.2.2 skrll IPD_INT_SUM_PRC_PAR3 | 355 1.2.2.2 skrll IPD_INT_SUM_PRC_PAR2 | 356 1.2.2.2 skrll IPD_INT_SUM_PRC_PAR1 | 357 1.2.2.2 skrll IPD_INT_SUM_PRC_PAR0); 358 1.2.2.2 skrll _IPD_WR8(sc, IPD_INT_SUM_OFFSET, ipd_int_xxx); 359 1.2.2.2 skrll _IPD_WR8(sc, IPD_INT_ENB_OFFSET, enable ? ipd_int_xxx : 0); 360 1.2.2.2 skrll } 361 1.2.2.2 skrll 362 1.2.2.2 skrll uint64_t 363 1.2.2.2 skrll octeon_ipd_int_summary(struct octeon_ipd_softc *sc) 364 1.2.2.2 skrll { 365 1.2.2.2 skrll uint64_t summary; 366 1.2.2.2 skrll 367 1.2.2.2 skrll summary = _IPD_RD8(sc, IPD_INT_SUM_OFFSET); 368 1.2.2.2 skrll _IPD_WR8(sc, IPD_INT_SUM_OFFSET, summary); 369 1.2.2.2 skrll return summary; 370 1.2.2.2 skrll } 371 1.2.2.2 skrll 372 1.2.2.2 skrll int 373 1.2.2.2 skrll octeon_ipd_intr_drop(void *arg) 374 1.2.2.2 skrll { 375 1.2.2.2 skrll octeon_write_csr(CIU_INT0_SUM0, CIU_INTX_SUM0_IPD_DRP); 376 1.2.2.2 skrll octeon_ipd_intr_drop_evcnt.ev_count++; 377 1.2.2.2 skrll return (1); 378 1.2.2.2 skrll } 379 1.2.2.2 skrll 380 1.2.2.2 skrll #define _ENTRY(x) { #x, x##_BITS, x##_OFFSET } 381 1.2.2.2 skrll 382 1.2.2.2 skrll struct octeon_ipd_dump_reg { 383 1.2.2.2 skrll const char *name; 384 1.2.2.2 skrll const char *format; 385 1.2.2.2 skrll size_t offset; 386 1.2.2.2 skrll }; 387 1.2.2.2 skrll 388 1.2.2.2 skrll static const struct octeon_ipd_dump_reg octeon_ipd_dump_regs[] = { 389 1.2.2.2 skrll _ENTRY(IPD_1ST_MBUFF_SKIP), 390 1.2.2.2 skrll _ENTRY(IPD_NOT_1ST_MBUFF_SKIP), 391 1.2.2.2 skrll _ENTRY(IPD_PACKET_MBUFF_SIZE), 392 1.2.2.2 skrll _ENTRY(IPD_CTL_STATUS), 393 1.2.2.2 skrll _ENTRY(IPD_WQE_FPA_QUEUE), 394 1.2.2.2 skrll _ENTRY(IPD_PORT0_BP_PAGE_CNT), 395 1.2.2.2 skrll _ENTRY(IPD_PORT1_BP_PAGE_CNT), 396 1.2.2.2 skrll _ENTRY(IPD_PORT2_BP_PAGE_CNT), 397 1.2.2.2 skrll _ENTRY(IPD_PORT32_BP_PAGE_CNT), 398 1.2.2.2 skrll _ENTRY(IPD_SUB_PORT_BP_PAGE_CNT), 399 1.2.2.2 skrll _ENTRY(IPD_1ST_NEXT_PTR_BACK), 400 1.2.2.2 skrll _ENTRY(IPD_2ND_NEXT_PTR_BACK), 401 1.2.2.2 skrll _ENTRY(IPD_INT_ENB), 402 1.2.2.2 skrll _ENTRY(IPD_INT_SUM), 403 1.2.2.2 skrll _ENTRY(IPD_SUB_PORT_FCS), 404 1.2.2.2 skrll _ENTRY(IPD_QOS0_RED_MARKS), 405 1.2.2.2 skrll _ENTRY(IPD_QOS1_RED_MARKS), 406 1.2.2.2 skrll _ENTRY(IPD_QOS2_RED_MARKS), 407 1.2.2.2 skrll _ENTRY(IPD_QOS3_RED_MARKS), 408 1.2.2.2 skrll _ENTRY(IPD_QOS4_RED_MARKS), 409 1.2.2.2 skrll _ENTRY(IPD_QOS5_RED_MARKS), 410 1.2.2.2 skrll _ENTRY(IPD_QOS6_RED_MARKS), 411 1.2.2.2 skrll _ENTRY(IPD_QOS7_RED_MARKS), 412 1.2.2.2 skrll _ENTRY(IPD_PORT_BP_COUNTERS_PAIR0), 413 1.2.2.2 skrll _ENTRY(IPD_PORT_BP_COUNTERS_PAIR1), 414 1.2.2.2 skrll _ENTRY(IPD_PORT_BP_COUNTERS_PAIR2), 415 1.2.2.2 skrll _ENTRY(IPD_PORT_BP_COUNTERS_PAIR32), 416 1.2.2.2 skrll _ENTRY(IPD_RED_PORT_ENABLE), 417 1.2.2.2 skrll _ENTRY(IPD_RED_QUE0_PARAM), 418 1.2.2.2 skrll _ENTRY(IPD_RED_QUE1_PARAM), 419 1.2.2.2 skrll _ENTRY(IPD_RED_QUE2_PARAM), 420 1.2.2.2 skrll _ENTRY(IPD_RED_QUE3_PARAM), 421 1.2.2.2 skrll _ENTRY(IPD_RED_QUE4_PARAM), 422 1.2.2.2 skrll _ENTRY(IPD_RED_QUE5_PARAM), 423 1.2.2.2 skrll _ENTRY(IPD_RED_QUE6_PARAM), 424 1.2.2.2 skrll _ENTRY(IPD_RED_QUE7_PARAM), 425 1.2.2.2 skrll _ENTRY(IPD_PTR_COUNT), 426 1.2.2.2 skrll _ENTRY(IPD_BP_PRT_RED_END), 427 1.2.2.2 skrll _ENTRY(IPD_QUE0_FREE_PAGE_CNT), 428 1.2.2.2 skrll _ENTRY(IPD_CLK_COUNT), 429 1.2.2.2 skrll _ENTRY(IPD_PWP_PTR_FIFO_CTL), 430 1.2.2.2 skrll _ENTRY(IPD_PRC_HOLD_PTR_FIFO_CTL), 431 1.2.2.2 skrll _ENTRY(IPD_PRC_PORT_PTR_FIFO_CTL), 432 1.2.2.2 skrll _ENTRY(IPD_PKT_PTR_VALID), 433 1.2.2.2 skrll _ENTRY(IPD_WQE_PTR_VALID), 434 1.2.2.2 skrll _ENTRY(IPD_BIST_STATUS), 435 1.2.2.2 skrll }; 436 1.2.2.2 skrll 437 1.2.2.2 skrll void 438 1.2.2.2 skrll octeon_ipd_dump(void) 439 1.2.2.2 skrll { 440 1.2.2.2 skrll struct octeon_ipd_softc *sc; 441 1.2.2.2 skrll const struct octeon_ipd_dump_reg *reg; 442 1.2.2.2 skrll uint64_t tmp; 443 1.2.2.2 skrll char buf[512]; 444 1.2.2.2 skrll int i; 445 1.2.2.2 skrll 446 1.2.2.2 skrll sc = __octeon_ipd_softc[0]; 447 1.2.2.2 skrll for (i = 0; i < (int)__arraycount(octeon_ipd_dump_regs); i++) { 448 1.2.2.2 skrll reg = &octeon_ipd_dump_regs[i]; 449 1.2.2.2 skrll tmp = _IPD_RD8(sc, reg->offset); 450 1.2.2.2 skrll if (reg->format == NULL) { 451 1.2.2.2 skrll snprintf(buf, sizeof(buf), "%16" PRIx64, tmp); 452 1.2.2.2 skrll } else { 453 1.2.2.2 skrll snprintb(buf, sizeof(buf), reg->format, tmp); 454 1.2.2.2 skrll } 455 1.2.2.2 skrll printf("%-32s: %s\n", reg->name, buf); 456 1.2.2.2 skrll } 457 1.2.2.2 skrll } 458 1.2.2.2 skrll #endif /* OCTEON_ETH_DEBUG */ 459
Indexes created Tue Sep 30 20:09:53 GMT 2025