octeon_ipd.c revision 1.3
1 /* $NetBSD: octeon_ipd.c,v 1.3 2020/05/31 06:27:06 simonb Exp $ */ 2 3 /* 4 * Copyright (c) 2007 Internet Initiative Japan, Inc. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 __KERNEL_RCSID(0, "$NetBSD: octeon_ipd.c,v 1.3 2020/05/31 06:27:06 simonb Exp $"); 31 32 #include "opt_octeon.h" 33 34 #include "opt_octeon.h" 35 36 #include <sys/param.h> 37 #include <sys/systm.h> 38 #include <sys/malloc.h> 39 #include <sys/mbuf.h> 40 #include <mips/locore.h> 41 #include <mips/cavium/octeonvar.h> 42 #include <mips/cavium/dev/octeon_ciureg.h> 43 #include <mips/cavium/dev/octeon_fpavar.h> 44 #include <mips/cavium/dev/octeon_pipreg.h> 45 #include <mips/cavium/dev/octeon_ipdreg.h> 46 #include <mips/cavium/dev/octeon_ipdvar.h> 47 48 #include <netinet/in.h> 49 #include <netinet/in_systm.h> 50 #include <netinet/ip.h> 51 52 #define IP_OFFSET(data, word2) \ 53 ((uintptr_t)(data) + (uintptr_t)((word2 & PIP_WQE_WORD2_IP_OFFSET) >> PIP_WQE_WORD2_IP_OFFSET_SHIFT)) 54 55 #ifdef CNMAC_DEBUG 56 void octipd_intr_evcnt_attach(struct octipd_softc *); 57 void octipd_intr_rml(void *); 58 int octipd_intr_drop(void *); 59 60 void octipd_dump(void); 61 62 static void *octipd_intr_drop_ih; 63 struct evcnt octipd_intr_drop_evcnt = 64 EVCNT_INITIALIZER(EVCNT_TYPE_INTR, NULL, "octeon", 65 "ipd drop intr"); 66 EVCNT_ATTACH_STATIC(octipd_intr_drop_evcnt); 67 68 struct octipd_softc *__octipd_softc[3/* XXX */]; 69 #endif 70 71 /* XXX */ 72 void 73 octipd_init(struct octipd_attach_args *aa, struct octipd_softc **rsc) 74 { 75 struct octipd_softc *sc; 76 int status; 77 78 sc = malloc(sizeof(*sc), M_DEVBUF, M_WAITOK | M_ZERO); 79 if (sc == NULL) 80 panic("can't allocate memory: %s", __func__); 81 82 sc->sc_port = aa->aa_port; 83 sc->sc_regt = aa->aa_regt; 84 sc->sc_first_mbuff_skip = aa->aa_first_mbuff_skip; 85 sc->sc_not_first_mbuff_skip = aa->aa_not_first_mbuff_skip; 86 87 status = bus_space_map(sc->sc_regt, IPD_BASE, IPD_SIZE, 0, 88 &sc->sc_regh); 89 if (status != 0) 90 panic("can't map %s space", "ipd register"); 91 92 *rsc = sc; 93 94 #ifdef CNMAC_DEBUG 95 octipd_int_enable(sc, 1); 96 octipd_intr_evcnt_attach(sc); 97 if (octipd_intr_drop_ih == NULL) 98 octipd_intr_drop_ih = octeon_intr_establish( 99 ffs64(CIU_INTX_SUM0_IPD_DRP) - 1, IPL_NET, 100 octipd_intr_drop, NULL); 101 __octipd_softc[sc->sc_port] = sc; 102 #endif /* CNMAC_DEBUG */ 103 } 104 105 #define _IPD_RD8(sc, off) \ 106 bus_space_read_8((sc)->sc_regt, (sc)->sc_regh, (off)) 107 #define _IPD_WR8(sc, off, v) \ 108 bus_space_write_8((sc)->sc_regt, (sc)->sc_regh, (off), (v)) 109 110 int 111 octipd_enable(struct octipd_softc *sc) 112 { 113 uint64_t ctl_status; 114 115 ctl_status = _IPD_RD8(sc, IPD_CTL_STATUS_OFFSET); 116 SET(ctl_status, IPD_CTL_STATUS_IPD_EN); 117 _IPD_WR8(sc, IPD_CTL_STATUS_OFFSET, ctl_status); 118 119 return 0; 120 } 121 122 int 123 octipd_config(struct octipd_softc *sc) 124 { 125 uint64_t first_mbuff_skip; 126 uint64_t not_first_mbuff_skip; 127 uint64_t packet_mbuff_size; 128 uint64_t first_next_ptr_back; 129 uint64_t second_next_ptr_back; 130 uint64_t sqe_fpa_queue; 131 uint64_t ctl_status; 132 133 /* XXX XXX XXX */ 134 first_mbuff_skip = 0; 135 SET(first_mbuff_skip, (sc->sc_first_mbuff_skip / 8) & IPD_1ST_MBUFF_SKIP_SZ); 136 _IPD_WR8(sc, IPD_1ST_MBUFF_SKIP_OFFSET, first_mbuff_skip); 137 /* XXX XXX XXX */ 138 139 /* XXX XXX XXX */ 140 not_first_mbuff_skip = 0; 141 SET(not_first_mbuff_skip, (sc->sc_not_first_mbuff_skip / 8) & 142 IPD_NOT_1ST_MBUFF_SKIP_SZ); 143 _IPD_WR8(sc, IPD_NOT_1ST_MBUFF_SKIP_OFFSET, not_first_mbuff_skip); 144 /* XXX XXX XXX */ 145 146 packet_mbuff_size = 0; 147 SET(packet_mbuff_size, (FPA_RECV_PKT_POOL_SIZE / 8) & 148 IPD_PACKET_MBUFF_SIZE_MB_SIZE); 149 _IPD_WR8(sc, IPD_PACKET_MBUFF_SIZE_OFFSET, packet_mbuff_size); 150 151 first_next_ptr_back = 0; 152 SET(first_next_ptr_back, (sc->sc_first_mbuff_skip / 128) & IPD_1ST_NEXT_PTR_BACK_BACK); 153 _IPD_WR8(sc, IPD_1ST_NEXT_PTR_BACK_OFFSET, first_next_ptr_back); 154 155 second_next_ptr_back = 0; 156 SET(second_next_ptr_back, (sc->sc_not_first_mbuff_skip / 128) & 157 IPD_2ND_NEXT_PTR_BACK_BACK); 158 _IPD_WR8(sc, IPD_2ND_NEXT_PTR_BACK_OFFSET, second_next_ptr_back); 159 160 sqe_fpa_queue = 0; 161 SET(sqe_fpa_queue, FPA_WQE_POOL & IPD_WQE_FPA_QUEUE_WQE_QUE); 162 _IPD_WR8(sc, IPD_WQE_FPA_QUEUE_OFFSET, sqe_fpa_queue); 163 164 ctl_status = _IPD_RD8(sc, IPD_CTL_STATUS_OFFSET); 165 CLR(ctl_status, IPD_CTL_STATUS_OPC_MODE); 166 SET(ctl_status, IPD_CTL_STATUS_OPC_MODE_ALL); 167 SET(ctl_status, IPD_CTL_STATUS_PBP_EN); 168 169 /* 170 * XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX 171 * from SDK 172 * SET(ctl_status, IPD_CTL_STATUS_LEN_M8); 173 * XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX 174 */ 175 176 _IPD_WR8(sc, IPD_CTL_STATUS_OFFSET, ctl_status); 177 178 return 0; 179 } 180 181 /* 182 * octeon work queue entry offload 183 * L3 error & L4 error 184 */ 185 void 186 octipd_offload(uint64_t word2, void *data, int *rcflags) 187 { 188 int cflags; 189 190 if (ISSET(word2, PIP_WQE_WORD2_IP_NI)) 191 return; 192 193 cflags = 0; 194 195 if (!ISSET(word2, PIP_WQE_WORD2_IP_V6)) 196 SET(cflags, M_CSUM_IPv4); 197 198 if (ISSET(word2, PIP_WQE_WORD2_IP_TU)) { 199 SET(cflags, 200 !ISSET(word2, PIP_WQE_WORD2_IP_V6) ? 201 (M_CSUM_TCPv4 | M_CSUM_UDPv4) : 202 (M_CSUM_TCPv6 | M_CSUM_UDPv6)); 203 } 204 205 /* check L3 (IP) error */ 206 if (ISSET(word2, PIP_WQE_WORD2_IP_IE)) { 207 struct ip *ip; 208 209 switch (word2 & PIP_WQE_WORD2_IP_OPECODE) { 210 case IPD_WQE_L3_V4_CSUM_ERR: 211 /* CN31XX Pass 1.1 Errata */ 212 ip = (struct ip *)(IP_OFFSET(data, word2)); 213 if (ip->ip_hl == 5) 214 SET(cflags, M_CSUM_IPv4_BAD); 215 break; 216 default: 217 break; 218 } 219 } 220 221 /* check L4 (UDP / TCP) error */ 222 if (ISSET(word2, PIP_WQE_WORD2_IP_LE)) { 223 switch (word2 & PIP_WQE_WORD2_IP_OPECODE) { 224 case IPD_WQE_L4_CSUM_ERR: 225 SET(cflags, M_CSUM_TCP_UDP_BAD); 226 break; 227 default: 228 break; 229 } 230 } 231 232 *rcflags = cflags; 233 } 234 235 int 236 octipd_red(struct octipd_softc *sc, uint64_t pass_thr, uint64_t drop_thr) 237 { 238 #if defined(CNMAC_IPD_RED) 239 /* 240 * no receive problem workaround. 241 * if not set IPD RED pramaters, 242 * may become unable to receive packet 243 * on media mismatch environment 244 * of self media 100-half duplex. 245 */ 246 uint64_t red_marks; 247 uint64_t red_param; 248 uint64_t red_port; 249 250 red_marks = drop_thr << 32 /* XXX */ | pass_thr; 251 _IPD_WR8(sc, IPD_QOS0_RED_MARKS_OFFSET, red_marks); 252 _IPD_WR8(sc, IPD_QOS1_RED_MARKS_OFFSET, red_marks); 253 _IPD_WR8(sc, IPD_QOS2_RED_MARKS_OFFSET, red_marks); 254 _IPD_WR8(sc, IPD_QOS3_RED_MARKS_OFFSET, red_marks); 255 _IPD_WR8(sc, IPD_QOS4_RED_MARKS_OFFSET, red_marks); 256 _IPD_WR8(sc, IPD_QOS5_RED_MARKS_OFFSET, red_marks); 257 _IPD_WR8(sc, IPD_QOS6_RED_MARKS_OFFSET, red_marks); 258 _IPD_WR8(sc, IPD_QOS7_RED_MARKS_OFFSET, red_marks); 259 red_param = 260 ((255ull << 24 /* XXX */) / (pass_thr - drop_thr)) | 261 1ull << 32 /* XXX */ | 262 255ull << 40 /* XXX */ | 263 1ull << 48 /* XXX */; 264 _IPD_WR8(sc, IPD_RED_QUE0_PARAM_OFFSET, red_param); 265 _IPD_WR8(sc, IPD_RED_QUE1_PARAM_OFFSET, red_param); 266 _IPD_WR8(sc, IPD_RED_QUE2_PARAM_OFFSET, red_param); 267 _IPD_WR8(sc, IPD_RED_QUE3_PARAM_OFFSET, red_param); 268 _IPD_WR8(sc, IPD_RED_QUE4_PARAM_OFFSET, red_param); 269 _IPD_WR8(sc, IPD_RED_QUE5_PARAM_OFFSET, red_param); 270 _IPD_WR8(sc, IPD_RED_QUE6_PARAM_OFFSET, red_param); 271 _IPD_WR8(sc, IPD_RED_QUE7_PARAM_OFFSET, red_param); 272 273 _IPD_WR8(sc, IPD_BP_PRT_RED_END_OFFSET, 0); 274 275 red_port = 0xfffffffffull | 276 10000ull << 36 /* XXX */ | 277 10000ull << 50 /* XXX */; 278 _IPD_WR8(sc, IPD_RED_PORT_ENABLE_OFFSET, red_port); 279 #endif 280 281 return 0; 282 } 283 284 void 285 octipd_sub_port_fcs(struct octipd_softc *sc, int enable) 286 { 287 uint64_t sub_port_fcs; 288 289 sub_port_fcs = _IPD_RD8(sc, IPD_SUB_PORT_FCS_OFFSET); 290 if (enable == 0) 291 CLR(sub_port_fcs, 1 << sc->sc_port); 292 else 293 SET(sub_port_fcs, 1 << sc->sc_port); 294 _IPD_WR8(sc, IPD_SUB_PORT_FCS_OFFSET, sub_port_fcs); 295 } 296 297 #ifdef CNMAC_DEBUG 298 int octipd_intr_rml_verbose; 299 struct evcnt octipd_intr_evcnt; 300 301 static const struct octeon_evcnt_entry octipd_intr_evcnt_entries[] = { 302 #define _ENTRY(name, type, parent, descr) \ 303 OCTEON_EVCNT_ENTRY(struct octipd_softc, name, type, parent, descr) 304 _ENTRY(ipdbpsub, MISC, NULL, "ipd backpressure subtract"), 305 _ENTRY(ipdprcpar3, MISC, NULL, "ipd parity error 127:96"), 306 _ENTRY(ipdprcpar2, MISC, NULL, "ipd parity error 95:64"), 307 _ENTRY(ipdprcpar1, MISC, NULL, "ipd parity error 63:32"), 308 _ENTRY(ipdprcpar0, MISC, NULL, "ipd parity error 31:0"), 309 #undef _ENTRY 310 }; 311 312 void 313 octipd_intr_evcnt_attach(struct octipd_softc *sc) 314 { 315 OCTEON_EVCNT_ATTACH_EVCNTS(sc, octipd_intr_evcnt_entries, "ipd0"); 316 } 317 318 void 319 octipd_intr_rml(void *arg) 320 { 321 int i; 322 323 octipd_intr_evcnt.ev_count++; 324 for (i = 0; i < 3/* XXX */; i++) { 325 struct octipd_softc *sc; 326 uint64_t reg; 327 328 sc = __octipd_softc[i]; 329 KASSERT(sc != NULL); 330 reg = octipd_int_summary(sc); 331 if (octipd_intr_rml_verbose) 332 printf("%s: IPD_INT_SUM=0x%016" PRIx64 "\n", __func__, reg); 333 if (reg & IPD_INT_SUM_BP_SUB) 334 OCTEON_EVCNT_INC(sc, ipdbpsub); 335 if (reg & IPD_INT_SUM_PRC_PAR3) 336 OCTEON_EVCNT_INC(sc, ipdprcpar3); 337 if (reg & IPD_INT_SUM_PRC_PAR2) 338 OCTEON_EVCNT_INC(sc, ipdprcpar2); 339 if (reg & IPD_INT_SUM_PRC_PAR1) 340 OCTEON_EVCNT_INC(sc, ipdprcpar1); 341 if (reg & IPD_INT_SUM_PRC_PAR0) 342 OCTEON_EVCNT_INC(sc, ipdprcpar0); 343 } 344 } 345 346 void 347 octipd_int_enable(struct octipd_softc *sc, int enable) 348 { 349 uint64_t ipd_int_xxx = 0; 350 351 SET(ipd_int_xxx, 352 IPD_INT_SUM_BP_SUB | 353 IPD_INT_SUM_PRC_PAR3 | 354 IPD_INT_SUM_PRC_PAR2 | 355 IPD_INT_SUM_PRC_PAR1 | 356 IPD_INT_SUM_PRC_PAR0); 357 _IPD_WR8(sc, IPD_INT_SUM_OFFSET, ipd_int_xxx); 358 _IPD_WR8(sc, IPD_INT_ENB_OFFSET, enable ? ipd_int_xxx : 0); 359 } 360 361 uint64_t 362 octipd_int_summary(struct octipd_softc *sc) 363 { 364 uint64_t summary; 365 366 summary = _IPD_RD8(sc, IPD_INT_SUM_OFFSET); 367 _IPD_WR8(sc, IPD_INT_SUM_OFFSET, summary); 368 return summary; 369 } 370 371 int 372 octipd_intr_drop(void *arg) 373 { 374 octeon_write_csr(CIU_INT0_SUM0, CIU_INTX_SUM0_IPD_DRP); 375 octipd_intr_drop_evcnt.ev_count++; 376 return (1); 377 } 378 379 #define _ENTRY(x) { #x, x##_BITS, x##_OFFSET } 380 381 struct octipd_dump_reg { 382 const char *name; 383 const char *format; 384 size_t offset; 385 }; 386 387 static const struct octipd_dump_reg octipd_dump_regs[] = { 388 _ENTRY(IPD_1ST_MBUFF_SKIP), 389 _ENTRY(IPD_NOT_1ST_MBUFF_SKIP), 390 _ENTRY(IPD_PACKET_MBUFF_SIZE), 391 _ENTRY(IPD_CTL_STATUS), 392 _ENTRY(IPD_WQE_FPA_QUEUE), 393 _ENTRY(IPD_PORT0_BP_PAGE_CNT), 394 _ENTRY(IPD_PORT1_BP_PAGE_CNT), 395 _ENTRY(IPD_PORT2_BP_PAGE_CNT), 396 _ENTRY(IPD_PORT32_BP_PAGE_CNT), 397 _ENTRY(IPD_SUB_PORT_BP_PAGE_CNT), 398 _ENTRY(IPD_1ST_NEXT_PTR_BACK), 399 _ENTRY(IPD_2ND_NEXT_PTR_BACK), 400 _ENTRY(IPD_INT_ENB), 401 _ENTRY(IPD_INT_SUM), 402 _ENTRY(IPD_SUB_PORT_FCS), 403 _ENTRY(IPD_QOS0_RED_MARKS), 404 _ENTRY(IPD_QOS1_RED_MARKS), 405 _ENTRY(IPD_QOS2_RED_MARKS), 406 _ENTRY(IPD_QOS3_RED_MARKS), 407 _ENTRY(IPD_QOS4_RED_MARKS), 408 _ENTRY(IPD_QOS5_RED_MARKS), 409 _ENTRY(IPD_QOS6_RED_MARKS), 410 _ENTRY(IPD_QOS7_RED_MARKS), 411 _ENTRY(IPD_PORT_BP_COUNTERS_PAIR0), 412 _ENTRY(IPD_PORT_BP_COUNTERS_PAIR1), 413 _ENTRY(IPD_PORT_BP_COUNTERS_PAIR2), 414 _ENTRY(IPD_PORT_BP_COUNTERS_PAIR32), 415 _ENTRY(IPD_RED_PORT_ENABLE), 416 _ENTRY(IPD_RED_QUE0_PARAM), 417 _ENTRY(IPD_RED_QUE1_PARAM), 418 _ENTRY(IPD_RED_QUE2_PARAM), 419 _ENTRY(IPD_RED_QUE3_PARAM), 420 _ENTRY(IPD_RED_QUE4_PARAM), 421 _ENTRY(IPD_RED_QUE5_PARAM), 422 _ENTRY(IPD_RED_QUE6_PARAM), 423 _ENTRY(IPD_RED_QUE7_PARAM), 424 _ENTRY(IPD_PTR_COUNT), 425 _ENTRY(IPD_BP_PRT_RED_END), 426 _ENTRY(IPD_QUE0_FREE_PAGE_CNT), 427 _ENTRY(IPD_CLK_COUNT), 428 _ENTRY(IPD_PWP_PTR_FIFO_CTL), 429 _ENTRY(IPD_PRC_HOLD_PTR_FIFO_CTL), 430 _ENTRY(IPD_PRC_PORT_PTR_FIFO_CTL), 431 _ENTRY(IPD_PKT_PTR_VALID), 432 _ENTRY(IPD_WQE_PTR_VALID), 433 _ENTRY(IPD_BIST_STATUS), 434 }; 435 436 void 437 octipd_dump(void) 438 { 439 struct octipd_softc *sc; 440 const struct octipd_dump_reg *reg; 441 uint64_t tmp; 442 char buf[512]; 443 int i; 444 445 sc = __octipd_softc[0]; 446 for (i = 0; i < (int)__arraycount(octipd_dump_regs); i++) { 447 reg = &octipd_dump_regs[i]; 448 tmp = _IPD_RD8(sc, reg->offset); 449 if (reg->format == NULL) { 450 snprintf(buf, sizeof(buf), "%16" PRIx64, tmp); 451 } else { 452 snprintb(buf, sizeof(buf), reg->format, tmp); 453 } 454 printf("%-32s: %s\n", reg->name, buf); 455 } 456 } 457 #endif /* CNMAC_DEBUG */ 458
Indexes created Fri Sep 26 20:09:58 GMT 2025