octeon_ipdreg.h revision 1.1
1 /* $NetBSD: octeon_ipdreg.h,v 1.1 2015/04/29 08:32:01 hikaru Exp $ */ 2 3 /* 4 * Copyright (c) 2007 Internet Initiative Japan, Inc. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 /* 30 * IPD Registers 31 */ 32 33 #ifndef _OCTEON_IPDREG_H_ 34 #define _OCTEON_IPDREG_H_ 35 36 #define IPD_1ST_MBUFF_SKIP 0x00014f0000000000ULL 37 #define IPD_NOT_1ST_MBUFF_SKIP 0x00014f0000000008ULL 38 #define IPD_PACKET_MBUFF_SIZE 0x00014f0000000010ULL 39 #define IPD_CTL_STATUS 0x00014f0000000018ULL 40 #define IPD_WQE_FPA_QUEUE 0x00014f0000000020ULL 41 #define IPD_PORT0_BP_PAGE_CNT 0x00014f0000000028ULL 42 #define IPD_PORT1_BP_PAGE_CNT 0x00014f0000000030ULL 43 #define IPD_PORT2_BP_PAGE_CNT 0x00014f0000000038ULL 44 #define IPD_PORT32_BP_PAGE_CNT 0x00014f0000000128ULL 45 #define IPD_SUB_PORT_BP_PAGE_CNT 0x00014f0000000148ULL 46 #define IPD_1ST_NEXT_PTR_BACK 0x00014f0000000150ULL 47 #define IPD_2ND_NEXT_PTR_BACK 0x00014f0000000158ULL 48 #define IPD_INT_ENB 0x00014f0000000160ULL 49 #define IPD_INT_SUM 0x00014f0000000168ULL 50 #define IPD_SUB_PORT_FCS 0x00014f0000000170ULL 51 #define IPD_QOS0_RED_MARKS 0x00014f0000000178ULL 52 #define IPD_QOS1_RED_MARKS 0x00014f0000000180ULL 53 #define IPD_QOS2_RED_MARKS 0x00014f0000000188ULL 54 #define IPD_QOS3_RED_MARKS 0x00014f0000000190ULL 55 #define IPD_QOS4_RED_MARKS 0x00014f0000000198ULL 56 #define IPD_QOS5_RED_MARKS 0x00014f00000001a0ULL 57 #define IPD_QOS6_RED_MARKS 0x00014f00000001a8ULL 58 #define IPD_QOS7_RED_MARKS 0x00014f00000001b0ULL 59 #define IPD_PORT_BP_COUNTERS_PAIR0 0x00014f00000001b8ULL 60 #define IPD_PORT_BP_COUNTERS_PAIR1 0x00014f00000001c0ULL 61 #define IPD_PORT_BP_COUNTERS_PAIR2 0x00014f00000001c8ULL 62 #define IPD_PORT_BP_COUNTERS_PAIR32 0x00014f00000002b8ULL 63 #define IPD_RED_PORT_ENABLE 0x00014f00000002d8ULL 64 #define IPD_RED_QUE0_PARAM 0x00014f00000002e0ULL 65 #define IPD_RED_QUE1_PARAM 0x00014f00000002e8ULL 66 #define IPD_RED_QUE2_PARAM 0x00014f00000002f0ULL 67 #define IPD_RED_QUE3_PARAM 0x00014f00000002f8ULL 68 #define IPD_RED_QUE4_PARAM 0x00014f0000000300ULL 69 #define IPD_RED_QUE5_PARAM 0x00014f0000000308ULL 70 #define IPD_RED_QUE6_PARAM 0x00014f0000000310ULL 71 #define IPD_RED_QUE7_PARAM 0x00014f0000000318ULL 72 #define IPD_PTR_COUNT 0x00014f0000000320ULL 73 #define IPD_BP_PRT_RED_END 0x00014f0000000328ULL 74 #define IPD_QUE0_FREE_PAGE_CNT 0x00014f0000000330ULL 75 #define IPD_CLK_COUNT 0x00014f0000000338ULL 76 #define IPD_PWP_PTR_FIFO_CTL 0x00014f0000000340ULL 77 #define IPD_PRC_HOLD_PTR_FIFO_CTL 0x00014f0000000348ULL 78 #define IPD_PRC_PORT_PTR_FIFO_CTL 0x00014f0000000350ULL 79 #define IPD_PKT_PTR_VALID 0x00014f0000000358ULL 80 #define IPD_WQE_PTR_VALID 0x00014f0000000360ULL 81 #define IPD_BIST_STATUS 0x00014f00000007f8ULL 82 83 #define IPD_BASE 0x00014f0000000000ULL 84 #define IPD_SIZE 0x800ULL 85 86 #define IPD_1ST_MBUFF_SKIP_OFFSET 0x0ULL 87 #define IPD_NOT_1ST_MBUFF_SKIP_OFFSET 0x8ULL 88 #define IPD_PACKET_MBUFF_SIZE_OFFSET 0x10ULL 89 #define IPD_CTL_STATUS_OFFSET 0x18ULL 90 #define IPD_WQE_FPA_QUEUE_OFFSET 0x20ULL 91 #define IPD_PORT0_BP_PAGE_CNT_OFFSET 0x28ULL 92 #define IPD_PORT1_BP_PAGE_CNT_OFFSET 0x30ULL 93 #define IPD_PORT2_BP_PAGE_CNT_OFFSET 0x38ULL 94 #define IPD_PORT32_BP_PAGE_CNT_OFFSET 0x128ULL 95 #define IPD_SUB_PORT_BP_PAGE_CNT_OFFSET 0x148ULL 96 #define IPD_1ST_NEXT_PTR_BACK_OFFSET 0x150ULL 97 #define IPD_2ND_NEXT_PTR_BACK_OFFSET 0x158ULL 98 #define IPD_INT_ENB_OFFSET 0x160ULL 99 #define IPD_INT_SUM_OFFSET 0x168ULL 100 #define IPD_SUB_PORT_FCS_OFFSET 0x170ULL 101 #define IPD_QOS0_RED_MARKS_OFFSET 0x178ULL 102 #define IPD_QOS1_RED_MARKS_OFFSET 0x180ULL 103 #define IPD_QOS2_RED_MARKS_OFFSET 0x188ULL 104 #define IPD_QOS3_RED_MARKS_OFFSET 0x190ULL 105 #define IPD_QOS4_RED_MARKS_OFFSET 0x198ULL 106 #define IPD_QOS5_RED_MARKS_OFFSET 0x1a0ULL 107 #define IPD_QOS6_RED_MARKS_OFFSET 0x1a8ULL 108 #define IPD_QOS7_RED_MARKS_OFFSET 0x1b0ULL 109 #define IPD_PORT_BP_COUNTERS_PAIR0_OFFSET 0x1b8ULL 110 #define IPD_PORT_BP_COUNTERS_PAIR1_OFFSET 0x1c0ULL 111 #define IPD_PORT_BP_COUNTERS_PAIR2_OFFSET 0x1c8ULL 112 #define IPD_PORT_BP_COUNTERS_PAIR32_OFFSET 0x2b8ULL 113 #define IPD_RED_PORT_ENABLE_OFFSET 0x2d8ULL 114 #define IPD_RED_QUE0_PARAM_OFFSET 0x2e0ULL 115 #define IPD_RED_QUE1_PARAM_OFFSET 0x2e8ULL 116 #define IPD_RED_QUE2_PARAM_OFFSET 0x2f0ULL 117 #define IPD_RED_QUE3_PARAM_OFFSET 0x2f8ULL 118 #define IPD_RED_QUE4_PARAM_OFFSET 0x300ULL 119 #define IPD_RED_QUE5_PARAM_OFFSET 0x308ULL 120 #define IPD_RED_QUE6_PARAM_OFFSET 0x310ULL 121 #define IPD_RED_QUE7_PARAM_OFFSET 0x318ULL 122 #define IPD_PTR_COUNT_OFFSET 0x320ULL 123 #define IPD_BP_PRT_RED_END_OFFSET 0x328ULL 124 #define IPD_QUE0_FREE_PAGE_CNT_OFFSET 0x330ULL 125 #define IPD_CLK_COUNT_OFFSET 0x338ULL 126 #define IPD_PWP_PTR_FIFO_CTL_OFFSET 0x340ULL 127 #define IPD_PRC_HOLD_PTR_FIFO_CTL_OFFSET 0x348ULL 128 #define IPD_PRC_PORT_PTR_FIFO_CTL_OFFSET 0x350ULL 129 #define IPD_PKT_PTR_VALID_OFFSET 0x358ULL 130 #define IPD_WQE_PTR_VALID_OFFSET 0x360ULL 131 #define IPD_BIST_STATUS_OFFSET 0x7f8ULL 132 133 /* ----- */ 134 /* 135 * Work Queue Entry Format (for input packet) 136 */ 137 138 /* 139 * word 2 140 * Work-Queue Entry format; Word2 Cases 141 */ 142 /* RAWFULL */ 143 #define IPD_WQE_WORD2_RAW_BUFS UINT64_C(0xff00000000000000) 144 #define IPD_WQE_WORD2_RAW_WORD UINT64_C(0x00ffffffffffffff) 145 146 /* is IP */ 147 #define IPD_WQE_WORD2_IP_BUFS UINT64_C(0xff00000000000000) 148 #define IPD_WQE_WORD2_IP_IPOFF UINT64_C(0x00ff000000000000) 149 #define IPD_WQE_WORD2_IP_VV UINT64_C(0x0000800000000000) 150 #define IPD_WQE_WORD2_IP_VS UINT64_C(0x0000400000000000) 151 #define IPD_WQE_WORD2_IP_45 UINT64_C(0x0000200000000000) 152 #define IPD_WQE_WORD2_IP_VC UINT64_C(0x0000100000000000) 153 #define IPD_WQE_WORD2_IP_VLANID UINT64_C(0x00000fff00000000) 154 #define IPD_WQE_WORD2_IP_31_20 UINT64_C(0x00000000fff00000) 155 #define IPD_WQE_WORD2_IP_CO UINT64_C(0x0000000000080000) 156 #define IPD_WQE_WORD2_IP_TU UINT64_C(0x0000000000040000) 157 #define IPD_WQE_WORD2_IP_SE UINT64_C(0x0000000000020000) 158 #define IPD_WQE_WORD2_IP_V6 UINT64_C(0x0000000000010000) 159 #define IPD_WQE_WORD2_IP_15 UINT64_C(0x0000000000008000) 160 #define IPD_WQE_WORD2_IP_LE UINT64_C(0x0000000000004000) 161 #define IPD_WQE_WORD2_IP_FR UINT64_C(0x0000000000002000) 162 #define IPD_WQE_WORD2_IP_IE UINT64_C(0x0000000000001000) 163 #define IPD_WQE_WORD2_IP_B UINT64_C(0x0000000000000800) 164 #define IPD_WQE_WORD2_IP_M UINT64_C(0x0000000000000400) 165 #define IPD_WQE_WORD2_IP_NI UINT64_C(0x0000000000000200) 166 #define IPD_WQE_WORD2_IP_RE UINT64_C(0x0000000000000100) 167 #define IPD_WQE_WORD2_IP_OPCODE UINT64_C(0x00000000000000ff) 168 169 /* All other */ 170 #define IPD_WQE_WORD2_OTH_BUFS UINT64_C(0xff00000000000000) 171 #define IPD_WQE_WORD2_OTH_55_48 UINT64_C(0x00ff000000000000) 172 #define IPD_WQE_WORD2_OTH_VV UINT64_C(0x0000800000000000) 173 #define IPD_WQE_WORD2_OTH_VS UINT64_C(0x0000400000000000) 174 #define IPD_WQE_WORD2_OTH_45 UINT64_C(0x0000200000000000) 175 #define IPD_WQE_WORD2_OTH_VC UINT64_C(0x0000100000000000) 176 #define IPD_WQE_WORD2_OTH_VLANID UINT64_C(0x00000fff00000000) 177 #define IPD_WQE_WORD2_OTH_31_14 UINT64_C(0x00000000ffffc000) 178 #define IPD_WQE_WORD2_OTH_IR UINT64_C(0x0000000000002000) 179 #define IPD_WQE_WORD2_OTH_IA UINT64_C(0x0000000000001000) 180 #define IPD_WQE_WORD2_OTH_B UINT64_C(0x0000000000000800) 181 #define IPD_WQE_WORD2_OTH_M UINT64_C(0x0000000000000400) 182 #define IPD_WQE_WORD2_OTH_NI UINT64_C(0x0000000000000200) 183 #define IPD_WQE_WORD2_OTH_RE UINT64_C(0x0000000000000100) 184 #define IPD_WQE_WORD2_OTH_OPCODE UINT64_C(0x00000000000000ff) 185 186 /* 187 * word 3 188 */ 189 #define IPD_WQE_WORD3_63 UINT64_C(0x8000000000000000) 190 #define IPD_WQE_WORD3_BACK UINT64_C(0x7800000000000000) 191 #define IPD_WQE_WORD3_58_56 UINT64_C(0x0700000000000000) 192 #define IPD_WQE_WORD3_SIZE UINT64_C(0x00ffff0000000000) 193 #define IPD_WQE_WORD3_ADDR UINT64_C(0x000000ffffffffff) 194 195 /* 196 * IPD_1ST_MBUFF_SKIP 197 */ 198 #define IPD_1ST_MBUFF_SKIP_63_6 UINT64_C(0xffffffffffffffc0) 199 #define IPD_1ST_MBUFF_SKIP_SZ UINT64_C(0x000000000000003f) 200 201 /* 202 * IPD_NOT_1ST_MBUFF_SKIP 203 */ 204 #define IPD_NOT_1ST_MBUFF_SKIP_63_6 UINT64_C(0xffffffffffffffc0) 205 #define IPD_NOT_1ST_MBUFF_SKIP_SZ UINT64_C(0x000000000000003f) 206 207 /* 208 * IPD_PACKET_MBUFF_SIZE 209 */ 210 #define IPD_PACKET_MBUFF_SIZE_63_12 UINT64_C(0xfffffffffffff000) 211 #define IPD_PACKET_MBUFF_SIZE_MB_SIZE UINT64_C(0x0000000000000fff) 212 213 /* 214 * IPD_CTL_STATUS 215 */ 216 #define IPD_CTL_STATUS_63_10 UINT64_C(0xfffffffffffffc00) 217 #define IPD_CTL_STATUS_LEN_M8 UINT64_C(0x0000000000000200) 218 #define IPD_CTL_STATUS_RESET UINT64_C(0x0000000000000100) 219 #define IPD_CTL_STATUS_ADDPKT UINT64_C(0x0000000000000080) 220 #define IPD_CTL_STATUS_NADDBUF UINT64_C(0x0000000000000040) 221 #define IPD_CTL_STATUS_PKT_LEND UINT64_C(0x0000000000000020) 222 #define IPD_CTL_STATUS_WQE_LEND UINT64_C(0x0000000000000010) 223 #define IPD_CTL_STATUS_PBP_EN UINT64_C(0x0000000000000008) 224 #define IPD_CTL_STATUS_OPC_MODE UINT64_C(0x0000000000000006) 225 #define IPD_CTL_STATUS_OPC_MODE_SHIFT 1 226 #define IPD_CTL_STATUS_OPC_MODE_NONE (0ULL << IPD_CTL_STATUS_OPC_MODE_SHIFT) 227 #define IPD_CTL_STATUS_OPC_MODE_ALL (1ULL << IPD_CTL_STATUS_OPC_MODE_SHIFT) 228 #define IPD_CTL_STATUS_OPC_MODE_ONE (2ULL << IPD_CTL_STATUS_OPC_MODE_SHIFT) 229 #define IPD_CTL_STATUS_OPC_MODE_TWO (3ULL << IPD_CTL_STATUS_OPC_MODE_SHIFT) 230 #define IPD_CTL_STATUS_IPD_EN UINT64_C(0x0000000000000001) 231 232 /* 233 * IPD_WQE_FPA_QUEUE 234 */ 235 #define IPD_WQE_FPA_QUEUE_63_3 UINT64_C(0xfffffffffffffff8) 236 #define IPD_WQE_FPA_QUEUE_WQE_QUE UINT64_C(0x0000000000000007) 237 238 /* 239 * IPD_PORTN_BP_PAGE_CNT 240 */ 241 #define IPD_PORTN_BP_PAGE_CNT_63_18 UINT64_C(0xfffffffffffc0000) 242 #define IPD_PORTN_BP_PAGE_CNT_BP_ENB UINT64_C(0x0000000000020000) 243 #define IPD_PORTN_BP_PAGE_CNT_PAGE_CNT UINT64_C(0x000000000001ffff) 244 245 /* 246 * IPD_SUB_PORT_BP_PAGE_CNT 247 */ 248 #define IPD_SUB_PORT_BP_PAGE_CNT_63_18 UINT64_C(0xffffffff80000000) 249 #define IPD_SUB_PORT_BP_PAGE_CNT_PORT UINT64_C(0x000000007e000000) 250 #define IPD_SUB_PORT_BP_PAGE_CNT_PAGE_CNT UINT64_C(0x0000000001ffffff) 251 252 /* 253 * IPD_1ST_NEXT_PTR_BACK 254 */ 255 #define IPD_1ST_NEXT_PTR_BACK_63_4 UINT64_C(0xfffffffffffffff0) 256 #define IPD_1ST_NEXT_PTR_BACK_BACK UINT64_C(0x000000000000000f) 257 258 /* 259 * IPD_2ND_NEXT_PTR_BACK 260 */ 261 #define IPD_2ND_NEXT_PTR_BACK_63_4 UINT64_C(0xfffffffffffffff0) 262 #define IPD_2ND_NEXT_PTR_BACK_BACK UINT64_C(0x000000000000000f) 263 264 /* 265 * IPD_INT_ENB 266 */ 267 #define IPD_INT_ENB_63_4 UINT64_C(0xffffffffffffffe0) 268 #define IPD_INT_ENB_BP_SUB UINT64_C(0x0000000000000010) 269 #define IPD_INT_ENB_PRC_PAR3 UINT64_C(0x0000000000000008) 270 #define IPD_INT_ENB_PRC_PAR2 UINT64_C(0x0000000000000004) 271 #define IPD_INT_ENB_PRC_PAR1 UINT64_C(0x0000000000000002) 272 #define IPD_INT_ENB_PRC_PAR0 UINT64_C(0x0000000000000001) 273 274 /* 275 * IPD_INT_SUM 276 */ 277 #define IPD_INT_SUM_63_4 UINT64_C(0xffffffffffffffe0) 278 #define IPD_INT_SUM_BP_SUB UINT64_C(0x0000000000000010) 279 #define IPD_INT_SUM_PRC_PAR3 UINT64_C(0x0000000000000008) 280 #define IPD_INT_SUM_PRC_PAR2 UINT64_C(0x0000000000000004) 281 #define IPD_INT_SUM_PRC_PAR1 UINT64_C(0x0000000000000002) 282 #define IPD_INT_SUM_PRC_PAR0 UINT64_C(0x0000000000000001) 283 284 /* 285 * IPD_SUB_PORT_FCS 286 */ 287 #define IPD_SUB_PORT_FCS_63_3 UINT64_C(0xfffffffffffffff8) 288 #define IPD_SUB_PORT_FCS_PORT_BIT UINT64_C(0x0000000000000007) 289 290 /* 291 * IPD_QOSN_RED_MARKS 292 */ 293 #define IPD_QOSN_READ_MARKS_DROP UINT64_C(0xffffffff00000000) 294 #define IPD_QOSN_READ_MARKS_PASS UINT64_C(0x00000000ffffffff) 295 296 /* 297 * IPD_PORT_BP_COUNTERS_PAIRN 298 */ 299 #define IPD_PORT_BP_COUNTERS_PAIRN_63_25 UINT64_C(0xfffffffffe000000) 300 #define IPD_PORT_BP_COUNTERS_PAIRN_CNT_VAL UINT64_C(0x0000000001ffffff) 301 302 /* 303 * IPD_RED_PORT_ENABLE 304 */ 305 #define IPD_RED_PORT_ENABLE_PRB_DLY UINT64_C(0xfffc000000000000) 306 #define IPD_RED_PORT_ENABLE_AVG_DLY UINT64_C(0x0003fff000000000) 307 #define IPD_RED_PORT_ENABLE_PRT_ENB UINT64_C(0x0000000fffffffff) 308 309 /* 310 * IPD_RED_QUEN_PARAM 311 */ 312 #define IPD_RED_QUEN_PARAM_63_49 UINT64_C(0xfffe000000000000) 313 #define IPD_RED_QUEN_PARAM_USE_PCNT UINT64_C(0x0001000000000000) 314 #define IPD_RED_QUEN_PARAM_NEW_CON UINT64_C(0x0000ff0000000000) 315 #define IPD_RED_QUEN_PARAM_AVG_CON UINT64_C(0x000000ff00000000) 316 #define IPD_RED_QUEN_PARAM_PRB_CON UINT64_C(0x00000000ffffffff) 317 318 /* 319 * IPD_PTR_COUNT 320 */ 321 #define IPD_PTR_COUNT_63_19 UINT64_C(0xfffffffffff80000) 322 #define IPD_PTR_COUNT_PKTV_CNT UINT64_C(0x0000000000040000) 323 #define IPD_PTR_COUNT_WQEV_CNT UINT64_C(0x0000000000020000) 324 #define IPD_PTR_COUNT_PFIF_CNT UINT64_C(0x000000000001c000) 325 #define IPD_PTR_COUNT_PKT_PCNT UINT64_C(0x0000000000003f80) 326 #define IPD_PTR_COUNT_WQE_PCNT UINT64_C(0x000000000000007f) 327 328 /* 329 * IPD_BP_PRT_RED_END 330 */ 331 #define IPD_BP_PRT_RED_END_63_36 UINT64_C(0xfffffff000000000) 332 #define IPD_BP_PRT_RED_END_PRT_ENB UINT64_C(0x0000000fffffffff) 333 334 /* 335 * IPD_QUE0_FREE_PAGE_CNT 336 */ 337 #define IPD_QUE0_FREE_PAGE_CNT_63_32 UINT64_C(0xffffffff00000000) 338 #define IPD_QUE0_FREE_PAGE_CNT_Q0_PCNT UINT64_C(0x00000000ffffffff) 339 340 /* 341 * IPD_CLK_COUNT 342 */ 343 #define IPD_CLK_COUNT_CLK_CNT UINT64_C(0xffffffffffffffff) 344 345 /* 346 * IPD_PWP_PTR_FIFO_CTL 347 */ 348 #define IPD_PWP_PTR_FIFO_CTL_63_61 UINT64_C(0xe000000000000000) 349 #define IPD_PWP_PTR_FIFO_CTL_MAX_CNTS UINT64_C(0x1fc0000000000000) 350 #define IPD_PWP_PTR_FIFO_CTL_WRADDR UINT64_C(0x003fc00000000000) 351 #define IPD_PWP_PTR_FIFO_CTL_PRADDR UINT64_C(0x00003fc000000000) 352 #define IPD_PWP_PTR_FIFO_CTL_PTR UINT64_C(0x0000003ffffffe00) 353 #define IPD_PWP_PTR_FIFO_CTL_CENA UINT64_C(0x0000000000000100) 354 #define IPD_PWP_PTR_FIFO_CTL_RADDR UINT64_C(0x00000000000000ff) 355 356 /* 357 * IPD_PRC_HOLD_PTR_FIFO_CTL 358 */ 359 #define IPD_PRC_HOLD_PTR_FIFO_CTL_63_39 UINT64_C(0xffffff8000000000) 360 #define IPD_PRC_HOLD_PTR_FIFO_CTL_MAX_PTR UINT64_C(0x0000007000000000) 361 #define IPD_PRC_HOLD_PTR_FIFO_CTL_PRADDR UINT64_C(0x0000000e00000000) 362 #define IPD_PRC_HOLD_PTR_FIFO_CTL_PTR UINT64_C(0x00000001fffffff0) 363 #define IPD_PRC_HOLD_PTR_FIFO_CTL_CENA UINT64_C(0x0000000000000008) 364 #define IPD_PRC_HOLD_PTR_FIFO_CTL_RADDR UINT64_C(0x0000000000000007) 365 366 /* 367 * IPD_PRC_PORT_PTR_FIFO_CTL 368 */ 369 #define IPD_PRC_PORT_PTR_FIFO_CTL_63_44 UINT64_C(0xfffff00000000000) 370 #define IPD_PRC_PORT_PTR_FIFO_CTL_MAX_PTR UINT64_C(0x00000fe000000000) 371 #define IPD_PRC_PORT_PTR_FIFO_CTL_PTR UINT64_C(0x0000001fffffff00) 372 #define IPD_PRC_PORT_PTR_FIFO_CTL_CENA UINT64_C(0x0000000000000080) 373 #define IPD_PRC_PORT_PTR_FIFO_CTL_RADDR UINT64_C(0x000000000000007f) 374 375 /* 376 * IPD_PKT_PTR_VALID 377 */ 378 #define IPD_PKT_PTR_VALID_63_29 UINT64_C(0xffffffffe0000000) 379 #define IPD_PKT_PTR_VALID_PTR UINT64_C(0x000000001fffffff) 380 381 /* 382 * IPD_WQE_PTR_VALID 383 */ 384 #define IPD_WQE_PTR_VALID_63_29 UINT64_C(0xffffffffe0000000) 385 #define IPD_WQE_PTR_VALID_PTR UINT64_C(0x000000001fffffff) 386 387 /* 388 * IPD_BIST_STATUS 389 */ 390 #define IPD_BIST_STATUS_63_29 UINT64_C(0xffffffffffff0000) 391 #define IPD_BIST_STATUS_PWQ_WQED UINT64_C(0x0000000000008000) 392 #define IPD_BIST_STATUS_PWQ_WP1 UINT64_C(0x0000000000004000) 393 #define IPD_BIST_STATUS_PWQ_POW UINT64_C(0x0000000000002000) 394 #define IPD_BIST_STATUS_IPQ_PBE1 UINT64_C(0x0000000000001000) 395 #define IPD_BIST_STATUS_IPQ_PBE0 UINT64_C(0x0000000000000800) 396 #define IPD_BIST_STATUS_PBM3 UINT64_C(0x0000000000000400) 397 #define IPD_BIST_STATUS_PBM2 UINT64_C(0x0000000000000200) 398 #define IPD_BIST_STATUS_PBM1 UINT64_C(0x0000000000000100) 399 #define IPD_BIST_STATUS_PBM0 UINT64_C(0x0000000000000080) 400 #define IPD_BIST_STATUS_PBM_WORD UINT64_C(0x0000000000000040) 401 #define IPD_BIST_STATUS_PWQ1 UINT64_C(0x0000000000000020) 402 #define IPD_BIST_STATUS_PWQ0 UINT64_C(0x0000000000000010) 403 #define IPD_BIST_STATUS_PRC_OFF UINT64_C(0x0000000000000008) 404 #define IPD_BIST_STATUS_IPD_OLD UINT64_C(0x0000000000000004) 405 #define IPD_BIST_STATUS_IPD_NEW UINT64_C(0x0000000000000002) 406 #define IPD_BIST_STATUS_PWP UINT64_C(0x0000000000000001) 407 408 /* 409 * word2[Opcode] 410 */ 411 /* L3 (IP) error */ 412 #define IPD_WQE_L3_NOT_IP 1 413 #define IPD_WQE_L3_V4_CSUM_ERR 2 414 #define IPD_WQE_L3_HEADER_MALFORMED 3 415 #define IPD_WQE_L3_MELFORMED 4 416 #define IPD_WQE_L3_TTL_HOP 5 417 #define IPD_WQE_L3_IP_OPT 6 418 419 /* L4 (UDP/TCP) error */ 420 #define IPD_WQE_L4_MALFORMED 1 421 #define IPD_WQE_L4_CSUM_ERR 2 422 #define IPD_WQE_L4_UDP_LEN_ERR 3 423 #define IPD_WQE_L4_BAD_PORT 4 424 #define IPD_WQE_L4_FIN_ONLY 8 425 #define IPD_WQE_L4_NO_FLAGS 9 426 #define IPD_WQE_L4_FIN_RST 10 427 #define IPD_WQE_L4_SYN_URG 11 428 #define IPD_WQE_L4_SYN_RST 12 429 #define IPD_WQE_L4_SYN_FIN 13 430 431 #define IPD_1ST_MBUFF_SKIP_BITS \ 432 "\177" /* new format */ \ 433 "\020" /* hex display */ \ 434 "\020" /* %016x format */ \ 435 "f\x06\x3a" "63_6\0" \ 436 "f\x00\x06" "SZ\0" 437 #define IPD_NOT_1ST_MBUFF_SKIP_BITS \ 438 "\177" /* new format */ \ 439 "\020" /* hex display */ \ 440 "\020" /* %016x format */ \ 441 "f\x06\x3a" "63_6\0" \ 442 "f\x00\x06" "SZ\0" 443 #define IPD_PACKET_MBUFF_SIZE_BITS \ 444 "\177" /* new format */ \ 445 "\020" /* hex display */ \ 446 "\020" /* %016x format */ \ 447 "f\x0c\x34" "63_12\0" \ 448 "f\x00\x0c" "MB_SIZE\0" 449 #define IPD_CTL_STATUS_BITS \ 450 "\177" /* new format */ \ 451 "\020" /* hex display */ \ 452 "\020" /* %016x format */ \ 453 "f\x0a\x36" "63_10\0" \ 454 "b\x09" "LEN_M8\0" \ 455 "b\x08" "RESET\0" \ 456 "b\x07" "ADDPKT\0" \ 457 "b\x06" "NADDBUF\0" \ 458 "b\x05" "PKT_LEND\0" \ 459 "b\x04" "WQE_LEND\0" \ 460 "b\x03" "PBP_EN\0" \ 461 "f\x01\x02" "OPC_MODE\0" \ 462 "b\x00" "IPD_EN\0" 463 #define IPD_WQE_FPA_QUEUE_BITS \ 464 "\177" /* new format */ \ 465 "\020" /* hex display */ \ 466 "\020" /* %016x format */ \ 467 "f\x03\x3d" "63_3\0" \ 468 "f\x00\x03" "WQE_QUE\0" 469 #define IPD_PORT0_BP_PAGE_CNT_BITS \ 470 "\177" /* new format */ \ 471 "\020" /* hex display */ \ 472 "\020" /* %016x format */ \ 473 474 #define IPD_PORT1_BP_PAGE_CNT_BITS \ 475 "\177" /* new format */ \ 476 "\020" /* hex display */ \ 477 "\020" /* %016x format */ \ 478 479 #define IPD_PORT2_BP_PAGE_CNT_BITS \ 480 "\177" /* new format */ \ 481 "\020" /* hex display */ \ 482 "\020" /* %016x format */ \ 483 484 #define IPD_PORT32_BP_PAGE_CNT_BITS \ 485 "\177" /* new format */ \ 486 "\020" /* hex display */ \ 487 "\020" /* %016x format */ \ 488 489 #define IPD_SUB_PORT_BP_PAGE_CNT_BITS \ 490 "\177" /* new format */ \ 491 "\020" /* hex display */ \ 492 "\020" /* %016x format */ \ 493 "f\x1f\x21" "63_18\0" \ 494 "f\x19\x06" "PORT\0" \ 495 "f\x00\x19" "PAGE_CNT\0" 496 #define IPD_1ST_NEXT_PTR_BACK_BITS \ 497 "\177" /* new format */ \ 498 "\020" /* hex display */ \ 499 "\020" /* %016x format */ \ 500 "f\x04\x3c" "63_4\0" \ 501 "f\x00\x04" "BACK\0" 502 #define IPD_2ND_NEXT_PTR_BACK_BITS \ 503 "\177" /* new format */ \ 504 "\020" /* hex display */ \ 505 "\020" /* %016x format */ \ 506 "f\x04\x3c" "63_4\0" \ 507 "f\x00\x04" "BACK\0" 508 #define IPD_INT_ENB_BITS \ 509 "\177" /* new format */ \ 510 "\020" /* hex display */ \ 511 "\020" /* %016x format */ \ 512 "f\x05\x3b" "63_4\0" \ 513 "b\x04" "BP_SUB\0" \ 514 "b\x03" "PRC_PAR3\0" \ 515 "b\x02" "PRC_PAR2\0" \ 516 "b\x01" "PRC_PAR1\0" \ 517 "b\x00" "PRC_PAR0\0" 518 #define IPD_INT_SUM_BITS \ 519 "\177" /* new format */ \ 520 "\020" /* hex display */ \ 521 "\020" /* %016x format */ \ 522 "f\x05\x3b" "63_4\0" \ 523 "b\x04" "BP_SUB\0" \ 524 "b\x03" "PRC_PAR3\0" \ 525 "b\x02" "PRC_PAR2\0" \ 526 "b\x01" "PRC_PAR1\0" \ 527 "b\x00" "PRC_PAR0\0" 528 #define IPD_SUB_PORT_FCS_BITS \ 529 "\177" /* new format */ \ 530 "\020" /* hex display */ \ 531 "\020" /* %016x format */ \ 532 "f\x03\x3d" "63_3\0" \ 533 "f\x00\x03" "PORT_BIT\0" 534 #define IPD_QOS0_RED_MARKS_BITS \ 535 "\177" /* new format */ \ 536 "\020" /* hex display */ \ 537 "\020" /* %016x format */ \ 538 539 #define IPD_QOS1_RED_MARKS_BITS \ 540 "\177" /* new format */ \ 541 "\020" /* hex display */ \ 542 "\020" /* %016x format */ \ 543 544 #define IPD_QOS2_RED_MARKS_BITS \ 545 "\177" /* new format */ \ 546 "\020" /* hex display */ \ 547 "\020" /* %016x format */ \ 548 549 #define IPD_QOS3_RED_MARKS_BITS \ 550 "\177" /* new format */ \ 551 "\020" /* hex display */ \ 552 "\020" /* %016x format */ \ 553 554 #define IPD_QOS4_RED_MARKS_BITS \ 555 "\177" /* new format */ \ 556 "\020" /* hex display */ \ 557 "\020" /* %016x format */ \ 558 559 #define IPD_QOS5_RED_MARKS_BITS \ 560 "\177" /* new format */ \ 561 "\020" /* hex display */ \ 562 "\020" /* %016x format */ \ 563 564 #define IPD_QOS6_RED_MARKS_BITS \ 565 "\177" /* new format */ \ 566 "\020" /* hex display */ \ 567 "\020" /* %016x format */ \ 568 569 #define IPD_QOS7_RED_MARKS_BITS \ 570 "\177" /* new format */ \ 571 "\020" /* hex display */ \ 572 "\020" /* %016x format */ \ 573 574 #define IPD_PORT_BP_COUNTERS_PAIR0_BITS \ 575 "\177" /* new format */ \ 576 "\020" /* hex display */ \ 577 "\020" /* %016x format */ \ 578 579 #define IPD_PORT_BP_COUNTERS_PAIR1_BITS \ 580 "\177" /* new format */ \ 581 "\020" /* hex display */ \ 582 "\020" /* %016x format */ \ 583 584 #define IPD_PORT_BP_COUNTERS_PAIR2_BITS \ 585 "\177" /* new format */ \ 586 "\020" /* hex display */ \ 587 "\020" /* %016x format */ \ 588 589 #define IPD_PORT_BP_COUNTERS_PAIR32_BITS \ 590 "\177" /* new format */ \ 591 "\020" /* hex display */ \ 592 "\020" /* %016x format */ \ 593 594 #define IPD_RED_PORT_ENABLE_BITS \ 595 "\177" /* new format */ \ 596 "\020" /* hex display */ \ 597 "\020" /* %016x format */ \ 598 "f\x32\x0e" "PRB_DLY\0" \ 599 "f\x24\x0e" "AVG_DLY\0" \ 600 "f\x00\x24" "PRT_ENB\0" 601 #define IPD_RED_QUE0_PARAM_BITS \ 602 "\177" /* new format */ \ 603 "\020" /* hex display */ \ 604 "\020" /* %016x format */ \ 605 606 #define IPD_RED_QUE1_PARAM_BITS \ 607 "\177" /* new format */ \ 608 "\020" /* hex display */ \ 609 "\020" /* %016x format */ \ 610 611 #define IPD_RED_QUE2_PARAM_BITS \ 612 "\177" /* new format */ \ 613 "\020" /* hex display */ \ 614 "\020" /* %016x format */ \ 615 616 #define IPD_RED_QUE3_PARAM_BITS \ 617 "\177" /* new format */ \ 618 "\020" /* hex display */ \ 619 "\020" /* %016x format */ \ 620 621 #define IPD_RED_QUE4_PARAM_BITS \ 622 "\177" /* new format */ \ 623 "\020" /* hex display */ \ 624 "\020" /* %016x format */ \ 625 626 #define IPD_RED_QUE5_PARAM_BITS \ 627 "\177" /* new format */ \ 628 "\020" /* hex display */ \ 629 "\020" /* %016x format */ \ 630 631 #define IPD_RED_QUE6_PARAM_BITS \ 632 "\177" /* new format */ \ 633 "\020" /* hex display */ \ 634 "\020" /* %016x format */ \ 635 636 #define IPD_RED_QUE7_PARAM_BITS \ 637 "\177" /* new format */ \ 638 "\020" /* hex display */ \ 639 "\020" /* %016x format */ \ 640 641 #define IPD_PTR_COUNT_BITS \ 642 "\177" /* new format */ \ 643 "\020" /* hex display */ \ 644 "\020" /* %016x format */ \ 645 "f\x13\x2d" "63_19\0" \ 646 "b\x12" "PKTV_CNT\0" \ 647 "b\x11" "WQEV_CNT\0" \ 648 "f\x0e\x03" "PFIF_CNT\0" \ 649 "f\x07\x07" "PKT_PCNT\0" \ 650 "f\x00\x07" "WQE_PCNT\0" 651 #define IPD_BP_PRT_RED_END_BITS \ 652 "\177" /* new format */ \ 653 "\020" /* hex display */ \ 654 "\020" /* %016x format */ \ 655 "f\x24\x1c" "63_36\0" \ 656 "f\x00\x24" "PRT_ENB\0" 657 #define IPD_QUE0_FREE_PAGE_CNT_BITS \ 658 "\177" /* new format */ \ 659 "\020" /* hex display */ \ 660 "\020" /* %016x format */ \ 661 "f\x20\x20" "63_32\0" \ 662 "f\x00\x20" "Q0_PCNT\0" 663 #define IPD_CLK_COUNT_BITS \ 664 "\177" /* new format */ \ 665 "\020" /* hex display */ \ 666 "\020" /* %016x format */ \ 667 "f\x00\x40" "CLK_CNT\0" 668 #define IPD_PWP_PTR_FIFO_CTL_BITS \ 669 "\177" /* new format */ \ 670 "\020" /* hex display */ \ 671 "\020" /* %016x format */ \ 672 "f\x3d\x03" "63_61\0" \ 673 "f\x36\x07" "MAX_CNTS\0" \ 674 "f\x2e\x08" "WRADDR\0" \ 675 "f\x26\x08" "PRADDR\0" \ 676 "f\x09\x1d" "PTR\0" \ 677 "b\x08" "CENA\0" \ 678 "f\x00\x08" "RADDR\0" 679 #define IPD_PRC_HOLD_PTR_FIFO_CTL_BITS \ 680 "\177" /* new format */ \ 681 "\020" /* hex display */ \ 682 "\020" /* %016x format */ \ 683 "f\x27\x19" "63_39\0" \ 684 "f\x24\x03" "MAX_PTR\0" \ 685 "f\x21\x03" "PRADDR\0" \ 686 "f\x04\x1d" "PTR\0" \ 687 "b\x03" "CENA\0" \ 688 "f\x00\x03" "RADDR\0" 689 #define IPD_PRC_PORT_PTR_FIFO_CTL_BITS \ 690 "\177" /* new format */ \ 691 "\020" /* hex display */ \ 692 "\020" /* %016x format */ \ 693 "f\x2c\x14" "63_44\0" \ 694 "f\x25\x07" "MAX_PTR\0" \ 695 "f\x08\x1d" "PTR\0" \ 696 "b\x07" "CENA\0" \ 697 "f\x00\x07" "RADDR\0" 698 #define IPD_PKT_PTR_VALID_BITS \ 699 "\177" /* new format */ \ 700 "\020" /* hex display */ \ 701 "\020" /* %016x format */ \ 702 "f\x1d\x23" "63_29\0" \ 703 "f\x00\x1d" "PTR\0" 704 #define IPD_WQE_PTR_VALID_BITS \ 705 "\177" /* new format */ \ 706 "\020" /* hex display */ \ 707 "\020" /* %016x format */ \ 708 "f\x1d\x23" "63_29\0" \ 709 "f\x00\x1d" "PTR\0" 710 #define IPD_BIST_STATUS_BITS \ 711 "\177" /* new format */ \ 712 "\020" /* hex display */ \ 713 "\020" /* %016x format */ \ 714 "f\x10\x30" "63_29\0" \ 715 "b\x0f" "PWQ_WQED\0" \ 716 "b\x0e" "PWQ_WP1\0" \ 717 "b\x0d" "PWQ_POW\0" \ 718 "b\x0c" "IPQ_PBE1\0" \ 719 "b\x0b" "IPQ_PBE0\0" \ 720 "b\x0a" "PBM3\0" \ 721 "b\x09" "PBM2\0" \ 722 "b\x08" "PBM1\0" \ 723 "b\x07" "PBM0\0" \ 724 "b\x06" "PBM_WORD\0" \ 725 "b\x05" "PWQ1\0" \ 726 "b\x04" "PWQ0\0" \ 727 "b\x03" "PRC_OFF\0" \ 728 "b\x02" "IPD_OLD\0" \ 729 "b\x01" "IPD_NEW\0" \ 730 "b\x00" "PWP\0" 731 732 #endif /* _OCTEON_IPDREG_H_ */ 733
Indexes created Thu Oct 02 07:10:07 GMT 2025