octeon_mpi.c revision 1.1
1 /* $NetBSD: octeon_mpi.c,v 1.1 2015/04/29 08:32:01 hikaru Exp $ */ 2 3 /* 4 * Copyright (c) 2007 Internet Initiative Japan, Inc. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 30 #include <sys/cdefs.h> 31 __KERNEL_RCSID(0, "$NetBSD: octeon_mpi.c,v 1.1 2015/04/29 08:32:01 hikaru Exp $"); 32 33 #include "opt_octeon.h" 34 35 #include <sys/param.h> 36 #include <sys/systm.h> 37 #include <sys/types.h> 38 #include <sys/device.h> 39 #include <sys/lock.h> 40 #include <sys/cdefs.h> 41 42 #include <mips/locore.h> 43 #include <sys/bus.h> 44 45 #include <mips/cavium/include/iobusvar.h> 46 #include <mips/cavium/dev/octeon_mpireg.h> 47 #include <mips/cavium/dev/octeon_mpivar.h> 48 #include <mips/cavium/dev/octeon_ciureg.h> 49 50 struct octeon_mpi_softc { 51 device_t sc_dev; 52 53 bus_space_tag_t sc_regt; 54 bus_space_handle_t sc_regh; 55 56 void *sc_ih; /* XXX Interrupt Handler */ 57 58 /* board-specific chip-select hook ops */ 59 void (*sc_ops_cs_on)(void); 60 void (*sc_ops_cs_off)(void); 61 struct octeon_mpi_controller ctrl; 62 63 }; 64 65 static int octeon_mpi_match(device_t, struct cfdata *, 66 void *); 67 static void octeon_mpi_attach(device_t, device_t, 68 void *); 69 #if 0 70 static int octeon_mpi_intr(void *); 71 #endif 72 void octeon_mpi_read(void *, u_int, 73 u_int, size_t, uint8_t *); 74 void octeon_mpi_write(void *, u_int, 75 u_int, size_t, uint8_t *); 76 static void octeon_mpi_xfer(struct octeon_mpi_softc *, size_t, 77 size_t); 78 static void octeon_mpi_wait(struct octeon_mpi_softc *); 79 static inline uint64_t octeon_mpi_reg_rd(struct octeon_mpi_softc *, int); 80 static inline void octeon_mpi_reg_wr(struct octeon_mpi_softc *, int, 81 uint64_t); 82 83 /* SPI service routines */ 84 int octeon_mpi_configure(void *, void *, void *); 85 86 #define GETREG(sc, x) \ 87 bus_space_read_8(sc->sc_regt, sc->sc_regh, x) 88 #define PUTREG(sc, x, v) \ 89 bus_space_write_8(sc->sc_regt, sc->sc_regh, x, v) 90 91 CFATTACH_DECL_NEW(octeon_mpi, sizeof(struct octeon_mpi_softc), 92 octeon_mpi_match, octeon_mpi_attach, NULL, NULL); 93 94 95 static int 96 spi_print(void *aux, const char *pnp) 97 { 98 aprint_normal(" spi"); 99 return (UNCONF); 100 } 101 102 static int 103 octeon_mpi_match(device_t parent, struct cfdata *cf, void *aux) 104 { 105 struct iobus_attach_args *aa = aux; 106 107 if (strcmp(cf->cf_name, aa->aa_name) != 0) 108 return 0; 109 return 1; 110 } 111 112 static void 113 octeon_mpi_attach(device_t parent, device_t self, void *aux) 114 { 115 struct octeon_mpi_softc *sc = device_private(self); 116 struct iobus_attach_args *aa = aux; 117 struct octeon_mpi_attach_args pa; 118 int status; 119 120 sc->sc_regt = aa->aa_bust; 121 122 /* 123 * Map registers. 124 */ 125 status = bus_space_map(sc->sc_regt, MPI_BASE, MPI_SIZE, 0, 126 &sc->sc_regh); 127 if (status != 0) 128 panic(": can't map register"); 129 130 aprint_normal(": Octeon MPI/SPI Controller\n"); 131 132 /* 133 * Initialize MPI/SPI Controller 134 */ 135 sc->ctrl.sc_bust = sc->sc_regt; 136 sc->ctrl.sc_bush = sc->sc_regh; 137 sc->ctrl.sct_cookie = sc; 138 sc->ctrl.sct_configure = octeon_mpi_configure; 139 sc->ctrl.sct_read = octeon_mpi_read; 140 sc->ctrl.sct_write = octeon_mpi_write; 141 pa.octeon_mpi_ctrl = &(sc->ctrl); 142 143 /* Enable SPI mode */ 144 #if 0 145 octeon_mpi_reg_wr(sc, MPI_CFG_OFFSET, 146 (0x7d << MPI_CFG_CLKDIV_SHIFT) | MPI_CFG_CSENA | MPI_CFG_ENABLE | MPI_CFG_INT_ENA); 147 /* Enable device interrupts */ 148 sc->sc_ih = octeon_intr_establish(ffs64(CIU_INTX_SUM0_MPI) - 1, 149 0, IPL_SERIAL, octeon_mpi_intr, sc); 150 if (sc->sc_ih == NULL) 151 panic("l2sw: can't establish interrupt\n"); 152 #else 153 octeon_mpi_reg_wr(sc, MPI_CFG_OFFSET, 154 (0x7d << MPI_CFG_CLKDIV_SHIFT) | MPI_CFG_CSENA | MPI_CFG_ENABLE); 155 #endif 156 octeon_mpi_reg_wr(sc, MPI_TX_OFFSET, 0); 157 158 config_found_ia(&sc->sc_dev, "octeon_mpi", &pa, spi_print); 159 } 160 161 #if 0 162 static int 163 octeon_mpi_intr(void *arg) 164 { 165 struct octeon_mpi_softc *sc = arg; 166 167 octeon_mpi_recv(sc); 168 169 /* Clear interrupts? */ 170 171 return 1; 172 } 173 #endif 174 175 void 176 octeon_mpi_read(void *parent, u_int cmd, u_int addr, 177 size_t len, uint8_t *data) 178 { 179 struct octeon_mpi_softc *sc = (void *)parent; 180 int i; 181 182 octeon_mpi_reg_wr(sc, MPI_DAT0_OFFSET, cmd); 183 octeon_mpi_reg_wr(sc, MPI_DAT1_OFFSET, addr); 184 185 octeon_mpi_xfer(sc, 2, 2 + len); 186 187 for (i = 0; i < (int)len; i++) 188 data[i] = octeon_mpi_reg_rd(sc, MPI_DAT2_OFFSET + i * 0x8); 189 } 190 191 void 192 octeon_mpi_write(void *parent, u_int cmd, u_int addr, 193 size_t len, uint8_t *data) 194 { 195 struct octeon_mpi_softc *sc = (void *)parent; 196 int i; 197 198 octeon_mpi_reg_wr(sc, MPI_DAT0_OFFSET, cmd); 199 octeon_mpi_reg_wr(sc, MPI_DAT1_OFFSET, addr); 200 201 for (i = 0; i < (int)len; i++) 202 octeon_mpi_reg_wr(sc, MPI_DAT2_OFFSET + i * 0x8, data[i]); 203 204 octeon_mpi_xfer(sc, 2 + len, 2 + len); 205 } 206 207 static void 208 octeon_mpi_xfer(struct octeon_mpi_softc *sc, size_t tx, size_t total) 209 { 210 if (sc->sc_ops_cs_on != NULL) 211 (*sc->sc_ops_cs_on)(); 212 213 octeon_mpi_reg_wr(sc, MPI_TX_OFFSET, 214 (tx << MPI_TX_TXNUM_SHIFT) | (total << MPI_TX_TOTNUM_SHIFT)); 215 octeon_mpi_wait(sc); 216 217 if (sc->sc_ops_cs_off != NULL) 218 (*sc->sc_ops_cs_off)(); 219 } 220 221 static void 222 octeon_mpi_wait(struct octeon_mpi_softc *sc) 223 { 224 uint64_t tmp; 225 226 /* XXX ltsleep & interrupt */ 227 tmp = octeon_mpi_reg_rd(sc, MPI_STS_OFFSET); 228 while (ISSET(tmp, MPI_STS_BUSY)) { 229 delay(10); 230 tmp = octeon_mpi_reg_rd(sc, MPI_STS_OFFSET); 231 } 232 } 233 234 static inline uint64_t 235 octeon_mpi_reg_rd(struct octeon_mpi_softc *sc, int offset) 236 { 237 return GETREG(sc, offset); 238 } 239 240 static inline void 241 octeon_mpi_reg_wr(struct octeon_mpi_softc *sc, int offset, uint64_t datum) 242 { 243 PUTREG(sc, offset, datum); 244 } 245 246 int 247 octeon_mpi_configure(void *arg, void *cs_on, void *cs_off) 248 { 249 struct octeon_mpi_softc *sc = arg; 250 251 sc->sc_ops_cs_on = cs_on; 252 sc->sc_ops_cs_off = cs_off; 253 254 return 0; 255 } 256
Indexes created Sun Sep 21 20:09:37 GMT 2025