octeon_mpi.c revision 1.6
1 /* $NetBSD: octeon_mpi.c,v 1.6 2021/04/24 23:36:42 thorpej Exp $ */ 2 3 /* 4 * Copyright (c) 2007 Internet Initiative Japan, Inc. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 30 #include <sys/cdefs.h> 31 __KERNEL_RCSID(0, "$NetBSD: octeon_mpi.c,v 1.6 2021/04/24 23:36:42 thorpej Exp $"); 32 33 #include "opt_octeon.h" 34 35 #include <sys/param.h> 36 #include <sys/systm.h> 37 #include <sys/types.h> 38 #include <sys/device.h> 39 #include <sys/lock.h> 40 #include <sys/cdefs.h> 41 42 #include <mips/locore.h> 43 #include <sys/bus.h> 44 45 #include <mips/cavium/include/iobusvar.h> 46 #include <mips/cavium/dev/octeon_mpireg.h> 47 #include <mips/cavium/dev/octeon_mpivar.h> 48 #include <mips/cavium/dev/octeon_ciureg.h> 49 50 struct octmpi_softc { 51 device_t sc_dev; 52 53 bus_space_tag_t sc_regt; 54 bus_space_handle_t sc_regh; 55 56 void *sc_ih; /* XXX Interrupt Handler */ 57 58 /* board-specific chip-select hook ops */ 59 void (*sc_ops_cs_on)(void); 60 void (*sc_ops_cs_off)(void); 61 struct octmpi_controller ctrl; 62 63 }; 64 65 static int octmpi_match(device_t, struct cfdata *, void *); 66 static void octmpi_attach(device_t, device_t, void *); 67 #if 0 68 static int octmpi_intr(void *); 69 #endif 70 void octmpi_read(void *, u_int, u_int, size_t, uint8_t *); 71 void octmpi_write(void *, u_int, u_int, size_t, uint8_t *); 72 static void octmpi_xfer(struct octmpi_softc *, size_t, size_t); 73 static void octmpi_wait(struct octmpi_softc *); 74 static inline uint64_t octmpi_reg_rd(struct octmpi_softc *, int); 75 static inline void octmpi_reg_wr(struct octmpi_softc *, int, uint64_t); 76 77 /* SPI service routines */ 78 int octmpi_configure(void *, void *, void *); 79 80 #define GETREG(sc, x) \ 81 bus_space_read_8(sc->sc_regt, sc->sc_regh, x) 82 #define PUTREG(sc, x, v) \ 83 bus_space_write_8(sc->sc_regt, sc->sc_regh, x, v) 84 85 CFATTACH_DECL_NEW(octeon_mpi, sizeof(struct octmpi_softc), 86 octmpi_match, octmpi_attach, NULL, NULL); 87 88 89 static int 90 spi_print(void *aux, const char *pnp) 91 { 92 aprint_normal(" spi"); 93 return (UNCONF); 94 } 95 96 static int 97 octmpi_match(device_t parent, struct cfdata *cf, void *aux) 98 { 99 struct iobus_attach_args *aa = aux; 100 101 if (strcmp(cf->cf_name, aa->aa_name) != 0) 102 return 0; 103 return 1; 104 } 105 106 static void 107 octmpi_attach(device_t parent, device_t self, void *aux) 108 { 109 struct octmpi_softc *sc = device_private(self); 110 struct iobus_attach_args *aa = aux; 111 struct octmpi_attach_args pa; 112 int status; 113 114 sc->sc_regt = aa->aa_bust; 115 116 /* 117 * Map registers. 118 */ 119 status = bus_space_map(sc->sc_regt, MPI_BASE, MPI_SIZE, 0, 120 &sc->sc_regh); 121 if (status != 0) 122 panic(": can't map register"); 123 124 aprint_normal(": Octeon MPI/SPI Controller\n"); 125 126 /* 127 * Initialize MPI/SPI Controller 128 */ 129 sc->ctrl.sc_bust = sc->sc_regt; 130 sc->ctrl.sc_bush = sc->sc_regh; 131 sc->ctrl.sct_cookie = sc; 132 sc->ctrl.sct_configure = octmpi_configure; 133 sc->ctrl.sct_read = octmpi_read; 134 sc->ctrl.sct_write = octmpi_write; 135 pa.octmpi_ctrl = &(sc->ctrl); 136 137 /* Enable SPI mode */ 138 #if 0 139 octmpi_reg_wr(sc, MPI_CFG_OFFSET, 140 (0x7d << MPI_CFG_CLKDIV_SHIFT) | MPI_CFG_CSENA | MPI_CFG_ENABLE | MPI_CFG_INT_ENA); 141 /* Enable device interrupts */ 142 sc->sc_ih = octeon_intr_establish(CIU_INT_MPI, IPL_SERIAL, octmpi_intr, sc); 143 if (sc->sc_ih == NULL) 144 panic("l2sw: can't establish interrupt\n"); 145 #else 146 octmpi_reg_wr(sc, MPI_CFG_OFFSET, 147 (0x7d << MPI_CFG_CLKDIV_SHIFT) | MPI_CFG_CSENA | MPI_CFG_ENABLE); 148 #endif 149 octmpi_reg_wr(sc, MPI_TX_OFFSET, 0); 150 151 config_found(&sc->sc_dev, &pa, spi_print, 152 CFARG_IATTR, "octmpi", 153 CFARG_EOL); 154 } 155 156 #if 0 157 static int 158 octmpi_intr(void *arg) 159 { 160 struct octmpi_softc *sc = arg; 161 162 octmpi_recv(sc); 163 164 /* Clear interrupts? */ 165 166 return 1; 167 } 168 #endif 169 170 void 171 octmpi_read(void *parent, u_int cmd, u_int addr, size_t len, uint8_t *data) 172 { 173 struct octmpi_softc *sc = (void *)parent; 174 int i; 175 176 octmpi_reg_wr(sc, MPI_DAT0_OFFSET, cmd); 177 octmpi_reg_wr(sc, MPI_DAT1_OFFSET, addr); 178 179 octmpi_xfer(sc, 2, 2 + len); 180 181 for (i = 0; i < (int)len; i++) 182 data[i] = octmpi_reg_rd(sc, MPI_DAT2_OFFSET + i * 0x8); 183 } 184 185 void 186 octmpi_write(void *parent, u_int cmd, u_int addr, size_t len, uint8_t *data) 187 { 188 struct octmpi_softc *sc = (void *)parent; 189 int i; 190 191 octmpi_reg_wr(sc, MPI_DAT0_OFFSET, cmd); 192 octmpi_reg_wr(sc, MPI_DAT1_OFFSET, addr); 193 194 for (i = 0; i < (int)len; i++) 195 octmpi_reg_wr(sc, MPI_DAT2_OFFSET + i * 0x8, data[i]); 196 197 octmpi_xfer(sc, 2 + len, 2 + len); 198 } 199 200 static void 201 octmpi_xfer(struct octmpi_softc *sc, size_t tx, size_t total) 202 { 203 if (sc->sc_ops_cs_on != NULL) 204 (*sc->sc_ops_cs_on)(); 205 206 octmpi_reg_wr(sc, MPI_TX_OFFSET, 207 (tx << MPI_TX_TXNUM_SHIFT) | (total << MPI_TX_TOTNUM_SHIFT)); 208 octmpi_wait(sc); 209 210 if (sc->sc_ops_cs_off != NULL) 211 (*sc->sc_ops_cs_off)(); 212 } 213 214 static void 215 octmpi_wait(struct octmpi_softc *sc) 216 { 217 uint64_t tmp; 218 219 /* XXX ltsleep & interrupt */ 220 tmp = octmpi_reg_rd(sc, MPI_STS_OFFSET); 221 while (ISSET(tmp, MPI_STS_BUSY)) { 222 delay(10); 223 tmp = octmpi_reg_rd(sc, MPI_STS_OFFSET); 224 } 225 } 226 227 static inline uint64_t 228 octmpi_reg_rd(struct octmpi_softc *sc, int offset) 229 { 230 231 return GETREG(sc, offset); 232 } 233 234 static inline void 235 octmpi_reg_wr(struct octmpi_softc *sc, int offset, uint64_t datum) 236 { 237 238 PUTREG(sc, offset, datum); 239 } 240 241 int 242 octmpi_configure(void *arg, void *cs_on, void *cs_off) 243 { 244 struct octmpi_softc *sc = arg; 245 246 sc->sc_ops_cs_on = cs_on; 247 sc->sc_ops_cs_off = cs_off; 248 249 return 0; 250 } 251
Indexes created Sun Sep 21 20:09:37 GMT 2025