octeon_pipreg.h revision 1.2 1 1.2 simonb /* $NetBSD: octeon_pipreg.h,v 1.2 2020/06/18 13:52:08 simonb Exp $ */
2 1.1 hikaru
3 1.1 hikaru /*
4 1.1 hikaru * Copyright (c) 2007 Internet Initiative Japan, Inc.
5 1.1 hikaru * All rights reserved.
6 1.1 hikaru *
7 1.1 hikaru * Redistribution and use in source and binary forms, with or without
8 1.1 hikaru * modification, are permitted provided that the following conditions
9 1.1 hikaru * are met:
10 1.1 hikaru * 1. Redistributions of source code must retain the above copyright
11 1.1 hikaru * notice, this list of conditions and the following disclaimer.
12 1.1 hikaru * 2. Redistributions in binary form must reproduce the above copyright
13 1.1 hikaru * notice, this list of conditions and the following disclaimer in the
14 1.1 hikaru * documentation and/or other materials provided with the distribution.
15 1.1 hikaru *
16 1.1 hikaru * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
17 1.1 hikaru * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 1.1 hikaru * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 1.1 hikaru * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
20 1.1 hikaru * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21 1.1 hikaru * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22 1.1 hikaru * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23 1.1 hikaru * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24 1.1 hikaru * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 1.1 hikaru * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26 1.1 hikaru * SUCH DAMAGE.
27 1.1 hikaru */
28 1.1 hikaru
29 1.1 hikaru /*
30 1.1 hikaru * PIP Registers
31 1.1 hikaru */
32 1.1 hikaru
33 1.1 hikaru #ifndef _OCTEON_PIPREG_H_
34 1.1 hikaru #define _OCTEON_PIPREG_H_
35 1.1 hikaru
36 1.1 hikaru #define PIP_BIST_STATUS 0x00011800a0000000ULL
37 1.1 hikaru #define PIP_INT_REG 0x00011800a0000008ULL
38 1.1 hikaru #define PIP_INT_EN 0x00011800a0000010ULL
39 1.1 hikaru #define PIP_STAT_CTL 0x00011800a0000018ULL
40 1.1 hikaru #define PIP_GBL_CTL 0x00011800a0000020ULL
41 1.1 hikaru #define PIP_GBL_CFG 0x00011800a0000028ULL
42 1.1 hikaru #define PIP_SOFT_RST 0x00011800a0000030ULL
43 1.1 hikaru #define PIP_IP_OFFSET 0x00011800a0000060ULL
44 1.1 hikaru #define PIP_TAG_SECRET 0x00011800a0000068ULL
45 1.1 hikaru #define PIP_TAG_MASK 0x00011800a0000070ULL
46 1.1 hikaru #define PIP_DEC_IPSEC0 0x00011800a0000080ULL
47 1.1 hikaru #define PIP_DEC_IPSEC1 0x00011800a0000088ULL
48 1.1 hikaru #define PIP_DEC_IPSEC2 0x00011800a0000090ULL
49 1.1 hikaru #define PIP_DEC_IPSEC3 0x00011800a0000098ULL
50 1.1 hikaru #define PIP_RAW_WORD 0x00011800a00000b0ULL
51 1.1 hikaru #define PIP_QOS_VLAN0 0x00011800a00000c0ULL
52 1.1 hikaru #define PIP_QOS_VLAN1 0x00011800a00000c8ULL
53 1.1 hikaru #define PIP_QOS_VLAN2 0x00011800a00000d0ULL
54 1.1 hikaru #define PIP_QOS_VLAN3 0x00011800a00000d8ULL
55 1.1 hikaru #define PIP_QOS_VLAN4 0x00011800a00000e0ULL
56 1.1 hikaru #define PIP_QOS_VLAN5 0x00011800a00000e8ULL
57 1.1 hikaru #define PIP_QOS_VLAN6 0x00011800a00000f0ULL
58 1.1 hikaru #define PIP_QOS_VLAN7 0x00011800a00000f8ULL
59 1.1 hikaru #define PIP_QOS_WATCH0 0x00011800a0000100ULL
60 1.1 hikaru #define PIP_QOS_WATCH1 0x00011800a0000108ULL
61 1.1 hikaru #define PIP_QOS_WATCH2 0x00011800a0000110ULL
62 1.1 hikaru #define PIP_QOS_WATCH3 0x00011800a0000118ULL
63 1.1 hikaru #define PIP_QOS_WATCH4 0x00011800a0000120ULL
64 1.1 hikaru #define PIP_QOS_WATCH5 0x00011800a0000128ULL
65 1.1 hikaru #define PIP_QOS_WATCH6 0x00011800a0000130ULL
66 1.1 hikaru #define PIP_QOS_WATCH7 0x00011800a0000138ULL
67 1.1 hikaru #define PIP_FRM_LEN_CHK0 0x00011800a0000180ULL
68 1.1 hikaru #define PIP_FRM_LEN_CHK1 0x00011800a0000188ULL
69 1.1 hikaru #define PIP_DSA_SRC_GRP 0x00011800a0000190ULL
70 1.1 hikaru #define PIP_DSA_VID_GRP 0x00011800a0000198ULL
71 1.1 hikaru #define PIP_HG_PRI_QOS 0x00011800a00001a0ULL
72 1.1 hikaru #define PIP_PRT_CFG0 0x00011800a0000200ULL
73 1.1 hikaru #define PIP_PRT_CFG1 0x00011800a0000208ULL
74 1.1 hikaru #define PIP_PRT_CFG2 0x00011800a0000210ULL
75 1.1 hikaru #define PIP_PRT_CFG32 0x00011800a0000300ULL
76 1.1 hikaru #define PIP_PRT_TAG0 0x00011800a0000400ULL
77 1.1 hikaru #define PIP_PRT_TAG1 0x00011800a0000408ULL
78 1.1 hikaru #define PIP_PRT_TAG2 0x00011800a0000410ULL
79 1.1 hikaru #define PIP_PRT_TAG32 0x00011800a0000500ULL
80 1.1 hikaru #define PIP_QOS_DIFF0 0x00011800a0000600ULL
81 1.1 hikaru /* PIP_QOS_DIFF[1-63] */
82 1.1 hikaru /* PIP_STAT[0-9]_PRT{0,1,2,32} */
83 1.1 hikaru #define PIP_STAT0_PRT0 0x00011800a0000800ULL
84 1.1 hikaru #define PIP_STAT0_PRT1 0x00011800a0000850ULL
85 1.1 hikaru #define PIP_STAT0_PRT2 0x00011800a00008a0ULL
86 1.1 hikaru #define PIP_STAT0_PRT32 0x00011800a0001200ULL
87 1.1 hikaru #define PIP_TAG_INC0 0x00011800a0001800ULL
88 1.1 hikaru /* PIP_TAG_INC[1-63] */
89 1.1 hikaru #define PIP_STAT_INB_PKTS0 0x00011800a0001a00ULL
90 1.1 hikaru #define PIP_STAT_INB_PKTS1 0x00011800a0001a20ULL
91 1.1 hikaru #define PIP_STAT_INB_PKTS2 0x00011800a0001a40ULL
92 1.1 hikaru #define PIP_STAT_INB_PKTS32 0x00011800a0001e00ULL
93 1.1 hikaru #define PIP_STAT_INB_OCTS0 0x00011800a0001a08ULL
94 1.1 hikaru #define PIP_STAT_INB_OCTS1 0x00011800a0001a28ULL
95 1.1 hikaru #define PIP_STAT_INB_OCTS2 0x00011800a0001a48ULL
96 1.1 hikaru #define PIP_STAT_INB_OCTS32 0x00011800a0001e08ULL
97 1.1 hikaru #define PIP_STAT_INB_ERRS0 0x00011800a0001a10ULL
98 1.1 hikaru #define PIP_STAT_INB_ERRS1 0x00011800a0001a30ULL
99 1.1 hikaru #define PIP_STAT_INB_ERRS2 0x00011800a0001a50ULL
100 1.1 hikaru #define PIP_STAT_INB_ERRS32 0x00011800a0001e10ULL
101 1.1 hikaru
102 1.1 hikaru #define PIP_BASE 0x00011800a0000000ULL
103 1.1 hikaru #define PIP_SIZE 0x1e50ULL
104 1.1 hikaru
105 1.1 hikaru #define PIP_BIST_STATUS_OFFSET 0x0ULL
106 1.1 hikaru #define PIP_INT_REG_OFFSET 0x8ULL
107 1.1 hikaru #define PIP_INT_EN_OFFSET 0x10ULL
108 1.1 hikaru #define PIP_STAT_CTL_OFFSET 0x18ULL
109 1.1 hikaru #define PIP_GBL_CTL_OFFSET 0x20ULL
110 1.1 hikaru #define PIP_GBL_CFG_OFFSET 0x28ULL
111 1.1 hikaru #define PIP_SOFT_RST_OFFSET 0x30ULL
112 1.1 hikaru #define PIP_IP_OFFSET_OFFSET 0x60ULL
113 1.1 hikaru #define PIP_TAG_SECRET_OFFSET 0x68ULL
114 1.1 hikaru #define PIP_TAG_MASK_OFFSET 0x70ULL
115 1.1 hikaru #define PIP_DEC_IPSEC0_OFFSET 0x80ULL
116 1.1 hikaru #define PIP_DEC_IPSEC1_OFFSET 0x88ULL
117 1.1 hikaru #define PIP_DEC_IPSEC2_OFFSET 0x90ULL
118 1.1 hikaru #define PIP_DEC_IPSEC3_OFFSET 0x98ULL
119 1.1 hikaru #define PIP_RAW_WORD_OFFSET 0xb0ULL
120 1.1 hikaru #define PIP_QOS_VLAN0_OFFSET 0xc0ULL
121 1.1 hikaru #define PIP_QOS_VLAN1_OFFSET 0xc8ULL
122 1.1 hikaru #define PIP_QOS_VLAN2_OFFSET 0xd0ULL
123 1.1 hikaru #define PIP_QOS_VLAN3_OFFSET 0xd8ULL
124 1.1 hikaru #define PIP_QOS_VLAN4_OFFSET 0xe0ULL
125 1.1 hikaru #define PIP_QOS_VLAN5_OFFSET 0xe8ULL
126 1.1 hikaru #define PIP_QOS_VLAN6_OFFSET 0xf0ULL
127 1.1 hikaru #define PIP_QOS_VLAN7_OFFSET 0xf8ULL
128 1.1 hikaru #define PIP_QOS_WATCH0_OFFSET 0x100ULL
129 1.1 hikaru #define PIP_QOS_WATCH1_OFFSET 0x108ULL
130 1.1 hikaru #define PIP_QOS_WATCH2_OFFSET 0x110ULL
131 1.1 hikaru #define PIP_QOS_WATCH3_OFFSET 0x118ULL
132 1.1 hikaru #define PIP_PRT_CFG0_OFFSET 0x200ULL
133 1.1 hikaru #define PIP_PRT_CFG1_OFFSET 0x208ULL
134 1.1 hikaru #define PIP_PRT_CFG2_OFFSET 0x210ULL
135 1.1 hikaru #define PIP_PRT_CFG32_OFFSET 0x300ULL
136 1.1 hikaru #define PIP_PRT_TAG0_OFFSET 0x400ULL
137 1.1 hikaru #define PIP_PRT_TAG1_OFFSET 0x408ULL
138 1.1 hikaru #define PIP_PRT_TAG2_OFFSET 0x410ULL
139 1.1 hikaru #define PIP_PRT_TAG32_OFFSET 0x500ULL
140 1.1 hikaru #define PIP_QOS_DIFF0_OFFSET 0x600ULL
141 1.1 hikaru /* PIP_QOS_DIFF[1-63] */
142 1.1 hikaru #define PIP_STAT0_PRT0_OFFSET 0x800ULL
143 1.1 hikaru #define PIP_STAT0_PRT1_OFFSET 0x850ULL
144 1.1 hikaru #define PIP_STAT0_PRT2_OFFSET 0x8a0ULL
145 1.1 hikaru #define PIP_STAT0_PRT32_OFFSET 0x1200ULL
146 1.1 hikaru #define PIP_STAT0_PRT33_OFFSET 0x1250ULL
147 1.1 hikaru #define PIP_STAT1_PRT0_OFFSET 0x800ULL
148 1.1 hikaru #define PIP_STAT1_PRT1_OFFSET 0x850ULL
149 1.1 hikaru #define PIP_STAT1_PRT2_OFFSET 0x8a0ULL
150 1.1 hikaru #define PIP_STAT1_PRT32_OFFSET 0x1200ULL
151 1.1 hikaru #define PIP_STAT1_PRT33_OFFSET 0x1250ULL
152 1.1 hikaru #define PIP_STAT2_PRT0_OFFSET 0x810ULL
153 1.1 hikaru #define PIP_STAT2_PRT1_OFFSET 0x860ULL
154 1.1 hikaru #define PIP_STAT2_PRT2_OFFSET 0x8b0ULL
155 1.1 hikaru #define PIP_STAT2_PRT32_OFFSET 0x1210ULL
156 1.1 hikaru #define PIP_STAT2_PRT33_OFFSET 0x1260ULL
157 1.1 hikaru #define PIP_STAT3_PRT0_OFFSET 0x818ULL
158 1.1 hikaru #define PIP_STAT3_PRT1_OFFSET 0x868ULL
159 1.1 hikaru #define PIP_STAT3_PRT2_OFFSET 0x8b8ULL
160 1.1 hikaru #define PIP_STAT3_PRT32_OFFSET 0x1218ULL
161 1.1 hikaru #define PIP_STAT3_PRT33_OFFSET 0x1268ULL
162 1.1 hikaru #define PIP_STAT4_PRT0_OFFSET 0x820ULL
163 1.1 hikaru #define PIP_STAT4_PRT1_OFFSET 0x870ULL
164 1.1 hikaru #define PIP_STAT4_PRT2_OFFSET 0x8c0ULL
165 1.1 hikaru #define PIP_STAT4_PRT32_OFFSET 0x1220ULL
166 1.1 hikaru #define PIP_STAT4_PRT33_OFFSET 0x1270ULL
167 1.1 hikaru #define PIP_STAT5_PRT0_OFFSET 0x828ULL
168 1.1 hikaru #define PIP_STAT5_PRT1_OFFSET 0x878ULL
169 1.1 hikaru #define PIP_STAT5_PRT2_OFFSET 0x8c8ULL
170 1.1 hikaru #define PIP_STAT5_PRT32_OFFSET 0x1228ULL
171 1.1 hikaru #define PIP_STAT5_PRT33_OFFSET 0x1278ULL
172 1.1 hikaru #define PIP_STAT6_PRT0_OFFSET 0x830ULL
173 1.1 hikaru #define PIP_STAT6_PRT1_OFFSET 0x880ULL
174 1.1 hikaru #define PIP_STAT6_PRT2_OFFSET 0x8d0ULL
175 1.1 hikaru #define PIP_STAT6_PRT32_OFFSET 0x1238ULL
176 1.1 hikaru #define PIP_STAT6_PRT33_OFFSET 0x1288ULL
177 1.1 hikaru #define PIP_STAT7_PRT0_OFFSET 0x838ULL
178 1.1 hikaru #define PIP_STAT7_PRT1_OFFSET 0x888ULL
179 1.1 hikaru #define PIP_STAT7_PRT2_OFFSET 0x8d8ULL
180 1.1 hikaru #define PIP_STAT7_PRT32_OFFSET 0x1238ULL
181 1.1 hikaru #define PIP_STAT7_PRT33_OFFSET 0x1288ULL
182 1.1 hikaru #define PIP_STAT8_PRT0_OFFSET 0x840ULL
183 1.1 hikaru #define PIP_STAT8_PRT1_OFFSET 0x890ULL
184 1.1 hikaru #define PIP_STAT8_PRT2_OFFSET 0x8e0ULL
185 1.1 hikaru #define PIP_STAT8_PRT32_OFFSET 0x1240ULL
186 1.1 hikaru #define PIP_STAT8_PRT33_OFFSET 0x1290ULL
187 1.1 hikaru #define PIP_STAT9_PRT0_OFFSET 0x848ULL
188 1.1 hikaru #define PIP_STAT9_PRT1_OFFSET 0x898ULL
189 1.1 hikaru #define PIP_STAT9_PRT2_OFFSET 0x8e8ULL
190 1.1 hikaru #define PIP_STAT9_PRT32_OFFSET 0x1248ULL
191 1.1 hikaru #define PIP_STAT9_PRT33_OFFSET 0x1298ULL
192 1.1 hikaru #define PIP_TAG_INC0_OFFSET 0x1800ULL
193 1.1 hikaru /* PIP_TAG_INC[1-63] */
194 1.1 hikaru #define PIP_STAT_INB_PKTS0_OFFSET 0x1a00ULL
195 1.1 hikaru #define PIP_STAT_INB_PKTS1_OFFSET 0x1a20ULL
196 1.1 hikaru #define PIP_STAT_INB_PKTS2_OFFSET 0x1a40ULL
197 1.1 hikaru #define PIP_STAT_INB_PKTS32_OFFSET 0x1e00ULL
198 1.1 hikaru #define PIP_STAT_INB_OCTS0_OFFSET 0x1a08ULL
199 1.1 hikaru #define PIP_STAT_INB_OCTS1_OFFSET 0x1a28ULL
200 1.1 hikaru #define PIP_STAT_INB_OCTS2_OFFSET 0x1a48ULL
201 1.1 hikaru #define PIP_STAT_INB_OCTS32_OFFSET 0x1e08ULL
202 1.1 hikaru #define PIP_STAT_INB_ERRS0_OFFSET 0x1a10ULL
203 1.1 hikaru #define PIP_STAT_INB_ERRS1_OFFSET 0x1a30ULL
204 1.1 hikaru #define PIP_STAT_INB_ERRS2_OFFSET 0x1a50ULL
205 1.1 hikaru #define PIP_STAT_INB_ERRS32_OFFSET 0x1e10ULL
206 1.1 hikaru #define PIP_STAT_INB_ERRS33_OFFSET 0x1e30ULL
207 1.1 hikaru
208 1.1 hikaru /*
209 1.1 hikaru * PIP_BIST_STATUS
210 1.1 hikaru */
211 1.1 hikaru #define PIP_BIST_STATUS_63_13 UINT64_C(0xfffffffffffc0000)
212 1.1 hikaru #define PIP_BIST_STATUS_BIST UINT64_C(0x000000000003ffff)
213 1.1 hikaru
214 1.1 hikaru /*
215 1.1 hikaru * PIP_INT_REG
216 1.1 hikaru */
217 1.1 hikaru #define PIP_INT_REG_63_9 UINT64_C(0xfffffffffffffe00)
218 1.1 hikaru #define PIP_INT_REG_BEPERR UINT64_C(0x0000000000000100)
219 1.1 hikaru #define PIP_INT_REG_FEPERR UINT64_C(0x0000000000000080)
220 1.1 hikaru #define PIP_INT_REG_6 UINT64_C(0x0000000000000040)
221 1.1 hikaru #define PIP_INT_REG_SKPRUNT UINT64_C(0x0000000000000020)
222 1.1 hikaru #define PIP_INT_REG_BADTAG UINT64_C(0x0000000000000010)
223 1.1 hikaru #define PIP_INT_REG_PRTNXA UINT64_C(0x0000000000000008)
224 1.1 hikaru #define PIP_INT_REG_2_1 0x00000006
225 1.1 hikaru #define PIP_INT_REG_PKTDRP UINT32_C(0x00000001)
226 1.1 hikaru
227 1.1 hikaru /*
228 1.1 hikaru * PIP_INT_EN
229 1.1 hikaru */
230 1.1 hikaru #define PIP_INT_EN_63_9 UINT64_C(0xfffffffffffffe00)
231 1.1 hikaru #define PIP_INT_EN_BEPERR UINT64_C(0x0000000000000100)
232 1.1 hikaru #define PIP_INT_EN_FEPERR UINT64_C(0x0000000000000080)
233 1.1 hikaru #define PIP_INT_EN_6 UINT64_C(0x0000000000000040)
234 1.1 hikaru #define PIP_INT_EN_SKPRUNT UINT64_C(0x0000000000000020)
235 1.1 hikaru #define PIP_INT_EN_BADTAG UINT64_C(0x0000000000000010)
236 1.1 hikaru #define PIP_INT_EN_PRTNXA UINT64_C(0x0000000000000008)
237 1.1 hikaru #define PIP_INT_EN_2_1 0x00000006
238 1.1 hikaru #define PIP_INT_EN_PKTDRP UINT32_C(0x00000001)
239 1.1 hikaru
240 1.1 hikaru /*
241 1.1 hikaru * PIP_STAT_CTL
242 1.1 hikaru */
243 1.1 hikaru #define PIP_STAT_CTL_63_1 UINT64_C(0xfffffffffffffffe)
244 1.1 hikaru #define PIP_STAT_CTL_RDCLR UINT64_C(0x0000000000000001)
245 1.1 hikaru
246 1.1 hikaru /*
247 1.1 hikaru * PIP_GBL_CTL
248 1.1 hikaru */
249 1.1 hikaru #define PIP_GBL_CTL_63_17 UINT64_C(0xfffffffffffe0000)
250 1.1 hikaru #define PIP_GBL_CTL_IGNRS UINT64_C(0x0000000000010000)
251 1.1 hikaru #define PIP_GBL_CTL_VS_WQE UINT64_C(0x0000000000008000)
252 1.1 hikaru #define PIP_GBL_CTL_VS_QOS UINT64_C(0x0000000000004000)
253 1.1 hikaru #define PIP_GBL_CTL_L2MAL UINT64_C(0x0000000000002000)
254 1.1 hikaru #define PIP_GBL_CTL_TCP_FLAG UINT64_C(0x0000000000001000)
255 1.1 hikaru #define PIP_GBL_CTL_L4_LEN UINT64_C(0x0000000000000800)
256 1.1 hikaru #define PIP_GBL_CTL_L4_CHK UINT64_C(0x0000000000000400)
257 1.1 hikaru #define PIP_GBL_CTL_L4_PRT UINT64_C(0x0000000000000200)
258 1.1 hikaru #define PIP_GBL_CTL_L4_MAL UINT64_C(0x0000000000000100)
259 1.1 hikaru #define PIP_GBL_CTL_7_6 UINT64_C(0x00000000000000c0)
260 1.1 hikaru #define PIP_GBL_CTL_IP6_EEXT UINT64_C(0x0000000000000030)
261 1.1 hikaru #define PIP_GBL_CTL_IP4_OPTS UINT64_C(0x0000000000000008)
262 1.1 hikaru #define PIP_GBL_CTL_IP_HOP UINT64_C(0x0000000000000004)
263 1.1 hikaru #define PIP_GBL_CTL_IP_MAL UINT64_C(0x0000000000000002)
264 1.1 hikaru #define PIP_GBL_CTL_IP_CHK UINT64_C(0x0000000000000001)
265 1.1 hikaru
266 1.1 hikaru /*
267 1.1 hikaru * PIP_GBL_CFG
268 1.1 hikaru */
269 1.1 hikaru /* XXX 63_17 is reserved? */
270 1.1 hikaru #define PIP_GBL_CFG_63_19 UINT64_C(0xfffffffffff80000)
271 1.1 hikaru #define PIP_GBL_CFG_TAG_SYN UINT64_C(0x0000000000040000)
272 1.1 hikaru #define PIP_GBL_CFG_IP6_UDP UINT64_C(0x0000000000020000)
273 1.1 hikaru #define PIP_GBL_CFG_MAX_L2 UINT64_C(0x0000000000010000)
274 1.1 hikaru #define PIP_GBL_CFG_15_11 UINT64_C(0x000000000000f800)
275 1.1 hikaru #define PIP_GBL_CFG_RAW_SHF UINT64_C(0x0000000000000700)
276 1.1 hikaru #define PIP_GBL_CFG_7_3 UINT64_C(0x00000000000000f8)
277 1.1 hikaru #define PIP_GBL_CFG_NIP_SHF UINT64_C(0x0000000000000007)
278 1.1 hikaru
279 1.1 hikaru /*
280 1.1 hikaru * PIP_SFT_RST
281 1.1 hikaru */
282 1.1 hikaru #define PIP_SFT_RST_63_17 UINT64_C(0xfffffffffffffffe)
283 1.1 hikaru #define PIP_SFT_RST_RST UINT64_C(0x0000000000000001)
284 1.1 hikaru
285 1.1 hikaru /*
286 1.1 hikaru * PIP_IP_OFFSET
287 1.1 hikaru */
288 1.1 hikaru #define PIP_IP_OFFSET_63_3 UINT64_C(0xfffffffffffffff8)
289 1.1 hikaru /* PIP_IP_OFFSET_OFFSET is defined above - conflict! */
290 1.1 hikaru #define PIP_IP_OFFSET_MASK_OFFSET UINT64_C(0x0000000000000007)
291 1.1 hikaru
292 1.1 hikaru /*
293 1.1 hikaru * PIP_TAG_SECRET
294 1.1 hikaru */
295 1.1 hikaru #define PIP_TAG_SECRET_63_3 UINT64_C(0xffffffff00000000)
296 1.1 hikaru #define PIP_TAG_SECRET_DST UINT64_C(0x00000000ffff0000)
297 1.1 hikaru #define PIP_TAG_SECRET_SRC UINT64_C(0x000000000000ffff)
298 1.1 hikaru
299 1.1 hikaru /*
300 1.1 hikaru * PIP_TAG_MASK
301 1.1 hikaru */
302 1.1 hikaru #define PIP_TAG_MASK_63_16 UINT64_C(0xffffffffffff0000)
303 1.1 hikaru #define PIP_TAG_MASK_MASK UINT64_C(0x000000000000ffff)
304 1.1 hikaru
305 1.1 hikaru /*
306 1.1 hikaru * PIP_DEC_IPSECN
307 1.1 hikaru */
308 1.1 hikaru #define PIP_DEC_IPSECN_63_18 UINT64_C(0xfffffffffffc0000)
309 1.1 hikaru #define PIP_DEC_IPSECN_TCP UINT64_C(0x0000000000020000)
310 1.1 hikaru #define PIP_DEC_IPSECN_UDP UINT64_C(0x0000000000010000)
311 1.1 hikaru #define PIP_DEC_IPSECN_DPRT UINT64_C(0x000000000000ffff)
312 1.1 hikaru
313 1.1 hikaru /*
314 1.1 hikaru * PIP_RAW_WORD
315 1.1 hikaru */
316 1.1 hikaru #define PIP_RAW_WORD_63_56 UINT64_C(0xff00000000000000)
317 1.1 hikaru #define PIP_RAW_WORD_WORD UINT64_C(0x00ffffffffffffff)
318 1.1 hikaru
319 1.1 hikaru /*
320 1.1 hikaru * PIP_QOS_VLAN
321 1.1 hikaru */
322 1.1 hikaru #define PIP_QOS_VLAN_63_3 UINT64_C(0xfffffffffffffff8)
323 1.1 hikaru #define PIP_QOS_VLAN_QOS UINT64_C(0x0000000000000007)
324 1.1 hikaru
325 1.1 hikaru /*
326 1.1 hikaru * PIP_QOS_WATCHN
327 1.1 hikaru */
328 1.1 hikaru #define PIP_QOS_WATCHN_63_48 UINT64_C(0xffff000000000000)
329 1.1 hikaru #define PIP_QOS_WATCHN_MASK UINT64_C(0x0000ffff00000000)
330 1.1 hikaru #define PIP_QOS_WATCHN_31_28 UINT64_C(0x00000000f0000000)
331 1.1 hikaru #define PIP_QOS_WATCHN_GRP UINT64_C(0x000000000f000000)
332 1.1 hikaru #define PIP_QOS_WATCHN_23 UINT64_C(0x0000000000800000)
333 1.1 hikaru #define PIP_QOS_WATCHN_WATCHER UINT64_C(0x0000000000700000)
334 1.1 hikaru #define PIP_QOS_WATCHN_19_18 UINT64_C(0x00000000000c0000)
335 1.1 hikaru #define PIP_QOS_WATCHN_TYPE UINT64_C(0x0000000000030000)
336 1.1 hikaru #define PIP_QOS_WATCHN_15_0 UINT64_C(0x000000000000ffff)
337 1.1 hikaru
338 1.1 hikaru /*
339 1.1 hikaru * PIP_PRT_CFGN
340 1.1 hikaru */
341 1.1 hikaru #define PIP_PRT_CFGN_63_53 UINT64_C(0xffe0000000000000)
342 1.1 hikaru #define PIP_PRT_CFGN_PAD_LEN UINT64_C(0x0010000000000000)
343 1.1 hikaru #define PIP_PRT_CFGN_VLAN_LEN UINT64_C(0x0008000000000000)
344 1.1 hikaru #define PIP_PRT_CFGN_LENERR_EN UINT64_C(0x0004000000000000)
345 1.1 hikaru #define PIP_PRT_CFGN_MAXERR_EN UINT64_C(0x0002000000000000)
346 1.1 hikaru #define PIP_PRT_CFGN_MINERR_EN UINT64_C(0x0001000000000000)
347 1.1 hikaru #define PIP_PRT_CFGN_GRP_WAT_47 UINT64_C(0x0000f00000000000)
348 1.1 hikaru #define PIP_PRT_CFGN_QOS_WAT_47 UINT64_C(0x00000f0000000000)
349 1.1 hikaru #define PIP_PRT_CFGN_39_37 UINT64_C(0x000000e000000000)
350 1.1 hikaru #define PIP_PRT_CFGN_RAWDRP UINT64_C(0x0000001000000000)
351 1.1 hikaru #define PIP_PRT_CFGN_TAG_INC UINT64_C(0x0000000c00000000)
352 1.1 hikaru #define PIP_PRT_CFGN_DYN_RS UINT64_C(0x0000000200000000)
353 1.1 hikaru #define PIP_PRT_CFGN_INST_HDR UINT64_C(0x0000000100000000)
354 1.1 hikaru #define PIP_PRT_CFGN_GRP_WAT UINT64_C(0x00000000f0000000)
355 1.1 hikaru #define PIP_PRT_CFGN_27 UINT64_C(0x0000000008000000)
356 1.1 hikaru #define PIP_PRT_CFGN_QOS UINT64_C(0x0000000007000000)
357 1.1 hikaru #define PIP_PRT_CFGN_QOS_WAT UINT64_C(0x0000000000f00000)
358 1.1 hikaru #define PIP_PRT_CFGN_19 UINT64_C(0x0000000000080000)
359 1.1 hikaru #define PIP_PRT_CFGN_SPARE UINT64_C(0x0000000000040000)
360 1.1 hikaru #define PIP_PRT_CFGN_QOS_DIFF UINT64_C(0x0000000000020000)
361 1.1 hikaru #define PIP_PRT_CFGN_QOS_VLAN UINT64_C(0x0000000000010000)
362 1.1 hikaru #define PIP_PRT_CFGN_15_13 UINT64_C(0x000000000000e000)
363 1.1 hikaru #define PIP_PRT_CFGN_CRC_EN UINT64_C(0x0000000000001000)
364 1.1 hikaru #define PIP_PRT_CFGN_11_10 UINT64_C(0x0000000000000c00)
365 1.1 hikaru #define PIP_PRT_CFGN_MODE UINT64_C(0x0000000000000300)
366 1.2 simonb #define PIP_PORT_CFG_MODE_NONE 0
367 1.2 simonb #define PIP_PORT_CFG_MODE_L2 1
368 1.2 simonb #define PIP_PORT_CFG_MODE_IP 2
369 1.2 simonb #define PIP_PORT_CFG_MODE_PCI 3
370 1.1 hikaru #define PIP_PRT_CFGN_7 UINT64_C(0x0000000000000080)
371 1.1 hikaru #define PIP_PRT_CFGN_SKIP UINT64_C(0x000000000000007f)
372 1.1 hikaru
373 1.1 hikaru /*
374 1.1 hikaru * PIP_PRT_TAGN
375 1.1 hikaru */
376 1.1 hikaru #define PIP_PRT_TAGN_63_40 UINT64_C(0xffffff0000000000)
377 1.1 hikaru #define PIP_PRT_TAGN_GRPTAGBASE UINT64_C(0x000000f000000000)
378 1.1 hikaru #define PIP_PRT_TAGN_GRPTAGMASK UINT64_C(0x0000000f00000000)
379 1.1 hikaru #define PIP_PRT_TAGN_GRPTAG UINT64_C(0x0000000080000000)
380 1.1 hikaru #define PIP_PRT_TAGN_SPARE UINT64_C(0x0000000040000000)
381 1.1 hikaru #define PIP_PRT_TAGN_TAG_MODE UINT64_C(0x0000000030000000)
382 1.1 hikaru #define PIP_PRT_TAGN_INC_VS UINT64_C(0x000000000c000000)
383 1.1 hikaru #define PIP_PRT_TAGN_INC_VLAN UINT64_C(0x0000000002000000)
384 1.1 hikaru #define PIP_PRT_TAGN_INC_PRT UINT64_C(0x0000000001000000)
385 1.1 hikaru #define PIP_PRT_TAGN_IP6_DPRT UINT64_C(0x0000000000800000)
386 1.1 hikaru #define PIP_PRT_TAGN_IP4_DPRT UINT64_C(0x0000000000400000)
387 1.1 hikaru #define PIP_PRT_TAGN_IP6_SPRT UINT64_C(0x0000000000200000)
388 1.1 hikaru #define PIP_PRT_TAGN_IP4_SPRT UINT64_C(0x0000000000100000)
389 1.1 hikaru #define PIP_PRT_TAGN_IP6_NXTH UINT64_C(0x0000000000080000)
390 1.1 hikaru #define PIP_PRT_TAGN_IP4_PCTL UINT64_C(0x0000000000040000)
391 1.1 hikaru #define PIP_PRT_TAGN_IP6_DST UINT64_C(0x0000000000020000)
392 1.1 hikaru #define PIP_PRT_TAGN_IP4_SRC UINT64_C(0x0000000000010000)
393 1.1 hikaru #define PIP_PRT_TAGN_IP6_SRC UINT64_C(0x0000000000008000)
394 1.1 hikaru #define PIP_PRT_TAGN_IP4_DST UINT64_C(0x0000000000004000)
395 1.1 hikaru #define PIP_PRT_TAGN_TCP6_TAG UINT64_C(0x0000000000003000)
396 1.2 simonb #define PIP_PRT_TAGN_TCP6_TAG_ORDERED 0
397 1.2 simonb #define PIP_PRT_TAGN_TCP6_TAG_ATOMIC 1
398 1.2 simonb #define PIP_PRT_TAGN_TCP6_TAG_NULL 2
399 1.2 simonb #define PIP_PRT_TAGN_TCP6_TAG_XXX_3 3
400 1.1 hikaru #define PIP_PRT_TAGN_TCP4_TAG UINT64_C(0x0000000000000c00)
401 1.2 simonb #define PIP_PRT_TAGN_TCP4_TAG_ORDERED 0
402 1.2 simonb #define PIP_PRT_TAGN_TCP4_TAG_ATOMIC 1
403 1.2 simonb #define PIP_PRT_TAGN_TCP4_TAG_NULL 2
404 1.2 simonb #define PIP_PRT_TAGN_TCP4_TAG_XXX_3 3
405 1.1 hikaru #define PIP_PRT_TAGN_IP6_TAG UINT64_C(0x0000000000000300)
406 1.2 simonb #define PIP_PRT_TAGN_IP6_TAG_ORDERED 0
407 1.2 simonb #define PIP_PRT_TAGN_IP6_TAG_ATOMIC 1
408 1.2 simonb #define PIP_PRT_TAGN_IP6_TAG_NULL 2
409 1.2 simonb #define PIP_PRT_TAGN_IP6_TAG_XXX_3 3
410 1.1 hikaru #define PIP_PRT_TAGN_IP4_TAG UINT64_C(0x00000000000000c0)
411 1.2 simonb #define PIP_PRT_TAGN_IP4_TAG_ORDERED 0
412 1.2 simonb #define PIP_PRT_TAGN_IP4_TAG_ATOMIC 1
413 1.2 simonb #define PIP_PRT_TAGN_IP4_TAG_NULL 2
414 1.2 simonb #define PIP_PRT_TAGN_IP4_TAG_XXX_3 3
415 1.1 hikaru #define PIP_PRT_TAGN_NON_TAG UINT64_C(0x0000000000000030)
416 1.2 simonb #define PIP_PRT_TAGN_NON_TAG_ORDERED 0
417 1.2 simonb #define PIP_PRT_TAGN_NON_TAG_ATOMIC 1
418 1.2 simonb #define PIP_PRT_TAGN_NON_TAG_NULL 2
419 1.2 simonb #define PIP_PRT_TAGN_NON_TAG_XXX_3 3
420 1.1 hikaru #define PIP_PRT_TAGN_GRP UINT64_C(0x000000000000000f)
421 1.1 hikaru
422 1.1 hikaru /*
423 1.1 hikaru * PIP_QOS_DIFFN
424 1.1 hikaru */
425 1.1 hikaru #define PIP_QOS_DIFF_63_3 UINT64_C(0xfffffffffffffff8)
426 1.1 hikaru #define PIP_QOS_DIFF_QOS UINT64_C(0x0000000000000007)
427 1.1 hikaru
428 1.1 hikaru /*
429 1.1 hikaru * PIP_TAG_INCN
430 1.1 hikaru */
431 1.1 hikaru #define PIP_TAG_INCN_63_8 UINT64_C(0xffffffffffffff00)
432 1.1 hikaru #define PIP_TAG_INCN_EN UINT64_C(0x00000000000000ff)
433 1.1 hikaru
434 1.1 hikaru /*
435 1.1 hikaru * PIP_STAT0_PRTN
436 1.1 hikaru */
437 1.1 hikaru #define PIP_STAT0_PRTN_DRP_PKTS UINT64_C(0xffffffff00000000)
438 1.1 hikaru #define PIP_STAT0_PRTN_DRP_OCTS UINT64_C(0x00000000ffffffff)
439 1.1 hikaru
440 1.1 hikaru /*
441 1.1 hikaru * PIP_STAT1_PRTN
442 1.1 hikaru */
443 1.1 hikaru #define PIP_STAT1_PRTN_63_48 UINT64_C(0xffff000000000000)
444 1.1 hikaru #define PIP_STAT1_PRTN_OCTS UINT64_C(0x0000ffffffffffff)
445 1.1 hikaru
446 1.1 hikaru /*
447 1.1 hikaru * PIP_STAT2_PRTN
448 1.1 hikaru */
449 1.1 hikaru #define PIP_STAT2_PRTN_PKTS UINT64_C(0xffffffff00000000)
450 1.1 hikaru #define PIP_STAT2_PRTN_RAW UINT64_C(0x00000000ffffffff)
451 1.1 hikaru
452 1.1 hikaru /*
453 1.1 hikaru * PIP_STAT3_PRTN
454 1.1 hikaru */
455 1.1 hikaru #define PIP_STAT3_PRTN_BCST UINT64_C(0xffffffff00000000)
456 1.1 hikaru #define PIP_STAT3_PRTN_MCST UINT64_C(0x00000000ffffffff)
457 1.1 hikaru
458 1.1 hikaru /*
459 1.1 hikaru * PIP_STAT4_PRTN
460 1.1 hikaru */
461 1.1 hikaru #define PIP_STAT4_PRTN_H65TO127 UINT64_C(0xffffffff00000000)
462 1.1 hikaru #define PIP_STAT4_PRTN_H64 UINT64_C(0x00000000ffffffff)
463 1.1 hikaru
464 1.1 hikaru /*
465 1.1 hikaru * PIP_STAT5_PRTN
466 1.1 hikaru */
467 1.1 hikaru #define PIP_STAT5_PRTN_H256TO511 UINT64_C(0xffffffff00000000)
468 1.1 hikaru #define PIP_STAT5_PRTN_H128TO255 UINT64_C(0x00000000ffffffff)
469 1.1 hikaru
470 1.1 hikaru /*
471 1.1 hikaru * PIP_STAT6_PRTN
472 1.1 hikaru */
473 1.1 hikaru #define PIP_STAT6_PRTN_H1024TO1518 UINT64_C(0xffffffff00000000)
474 1.1 hikaru #define PIP_STAT6_PRTN_H512TO1023 UINT64_C(0x00000000ffffffff)
475 1.1 hikaru
476 1.1 hikaru /*
477 1.1 hikaru * PIP_STAT7_PRTN
478 1.1 hikaru */
479 1.1 hikaru #define PIP_STAT7_PRTN_FCS UINT64_C(0xffffffff00000000)
480 1.1 hikaru #define PIP_STAT7_PRTN_H1519 UINT64_C(0x00000000ffffffff)
481 1.1 hikaru
482 1.1 hikaru /*
483 1.1 hikaru * PIP_STAT8_PRTN
484 1.1 hikaru */
485 1.1 hikaru #define PIP_STAT8_PRTN_FRAG UINT64_C(0xffffffff00000000)
486 1.1 hikaru #define PIP_STAT8_PRTN_UNDERSZ UINT64_C(0x00000000ffffffff)
487 1.1 hikaru
488 1.1 hikaru /*
489 1.1 hikaru * PIP_STAT9_PRTN
490 1.1 hikaru */
491 1.1 hikaru #define PIP_STAT9_PRTN_JABBER UINT64_C(0xffffffff00000000)
492 1.1 hikaru #define PIP_STAT9_PRTN_OVERSZ UINT64_C(0x00000000ffffffff)
493 1.1 hikaru
494 1.1 hikaru /*
495 1.1 hikaru * PIP_STAT_INB_PKTN
496 1.1 hikaru */
497 1.1 hikaru #define PIP_STAT_INB_PKTSN UINT64_C(0xffffffff00000000)
498 1.1 hikaru #define PIP_STAT_INB_PKTSN_PKTS UINT64_C(0x00000000ffffffff)
499 1.1 hikaru
500 1.1 hikaru /*
501 1.1 hikaru * PIP_STAT_INB_OCTSN
502 1.1 hikaru */
503 1.1 hikaru #define PIP_STAT_INB_OCTSN UINT64_C(0xffff000000000000)
504 1.1 hikaru #define PIP_STAT_INB_OCTSN_OCTS UINT64_C(0x0000ffffffffffff)
505 1.1 hikaru
506 1.1 hikaru /*
507 1.1 hikaru * PIP_STAT_INB_ERRS
508 1.1 hikaru */
509 1.1 hikaru #define PIP_STAT_INB_ERRSN UINT64_C(0xffffffffffff0000)
510 1.1 hikaru #define PIP_STAT_INB_ERRSN_OCTS UINT64_C(0x000000000000ffff)
511 1.1 hikaru
512 1.1 hikaru /*
513 1.1 hikaru * Work-Queue Entry Format
514 1.1 hikaru */
515 1.1 hikaru /* WORD0 */
516 1.1 hikaru #define PIP_WQE_WORD0_HW_CSUM UINT64_C(0xffff000000000000)
517 1.1 hikaru #define PIP_WQE_WORD0_47_40 UINT64_C(0x0000ff0000000000)
518 1.1 hikaru #define PIP_WQE_WORD0_POW_NEXT_PTR UINT64_C(0x000000ffffffffff)
519 1.1 hikaru
520 1.1 hikaru /* WORD 1 */
521 1.1 hikaru #define PIP_WQE_WORD1_LEN UINT64_C(0xffff000000000000)
522 1.1 hikaru #define PIP_WQE_WORD1_IPRT UINT64_C(0x0000fc0000000000)
523 1.1 hikaru #define PIP_WQE_WORD1_QOS UINT64_C(0x0000038000000000)
524 1.1 hikaru #define PIP_WQE_WORD1_GRP UINT64_C(0x0000007800000000)
525 1.1 hikaru #define PIP_WQE_WORD1_TT UINT64_C(0x0000000700000000)
526 1.1 hikaru #define PIP_WQE_WORD1_TAG UINT64_C(0x00000000ffffffff)
527 1.1 hikaru
528 1.1 hikaru /* WORD 2 */
529 1.1 hikaru #define PIP_WQE_WORD2_RAWFULL_BUFS UINT64_C(0xff00000000000000)
530 1.1 hikaru #define PIP_WQE_WORD2_RAWFULL_PIP_RAW_WORD UINT64_C(0x00ffffffffffffff)
531 1.1 hikaru
532 1.1 hikaru #define PIP_WQE_WORD2_IP_BUFS UINT64_C(0xff00000000000000)
533 1.1 hikaru #define PIP_WQE_WORD2_IP_OFFSET UINT64_C(0x00ff000000000000)
534 1.1 hikaru #define PIP_WQE_WORD2_IP_VV UINT64_C(0x0000800000000000)
535 1.1 hikaru #define PIP_WQE_WORD2_IP_VS UINT64_C(0x0000400000000000)
536 1.1 hikaru #define PIP_WQE_WORD2_IP_45 UINT64_C(0x0000200000000000)
537 1.1 hikaru #define PIP_WQE_WORD2_IP_VC UINT64_C(0x0000100000000000)
538 1.1 hikaru #define PIP_WQE_WORD2_IP_VLAN_ID UINT64_C(0x00000fff00000000)
539 1.1 hikaru #define PIP_WQE_WORD2_IP_31_20 UINT64_C(0x00000000fff00000)
540 1.1 hikaru #define PIP_WQE_WORD2_IP_CO UINT64_C(0x0000000000080000)
541 1.1 hikaru #define PIP_WQE_WORD2_IP_TU UINT64_C(0x0000000000040000)
542 1.1 hikaru #define PIP_WQE_WORD2_IP_SE UINT64_C(0x0000000000020000)
543 1.1 hikaru #define PIP_WQE_WORD2_IP_V6 UINT64_C(0x0000000000010000)
544 1.1 hikaru #define PIP_WQE_WORD2_IP_15 UINT64_C(0x0000000000008000)
545 1.1 hikaru #define PIP_WQE_WORD2_IP_LE UINT64_C(0x0000000000004000)
546 1.1 hikaru #define PIP_WQE_WORD2_IP_FR UINT64_C(0x0000000000002000)
547 1.1 hikaru #define PIP_WQE_WORD2_IP_IE UINT64_C(0x0000000000001000)
548 1.1 hikaru #define PIP_WQE_WORD2_IP_B UINT64_C(0x0000000000000800)
549 1.1 hikaru #define PIP_WQE_WORD2_IP_M UINT64_C(0x0000000000000400)
550 1.1 hikaru #define PIP_WQE_WORD2_IP_NI UINT64_C(0x0000000000000200)
551 1.1 hikaru #define PIP_WQE_WORD2_IP_RE UINT64_C(0x0000000000000100)
552 1.1 hikaru #define PIP_WQE_WORD2_IP_OPECODE UINT64_C(0x00000000000000ff)
553 1.1 hikaru
554 1.1 hikaru #define PIP_WQE_WORD2_NOIP_BUFS UINT64_C(0xff00000000000000)
555 1.1 hikaru #define PIP_WQE_WORD2_NOIP_55_48 UINT64_C(0x00ff000000000000)
556 1.1 hikaru #define PIP_WQE_WORD2_NOIP_VV UINT64_C(0x0000800000000000)
557 1.1 hikaru #define PIP_WQE_WORD2_NOIP_VS UINT64_C(0x0000400000000000)
558 1.1 hikaru #define PIP_WQE_WORD2_NOIP_45 UINT64_C(0x0000200000000000)
559 1.1 hikaru #define PIP_WQE_WORD2_NOIP_VC UINT64_C(0x0000100000000000)
560 1.1 hikaru #define PIP_WQE_WORD2_NOIP_VLAN_ID UINT64_C(0x00000fff00000000)
561 1.1 hikaru #define PIP_WQE_WORD2_NOIP_31_14 UINT64_C(0x00000000ffffc000)
562 1.1 hikaru #define PIP_WQE_WORD2_NOIP_IR UINT64_C(0x0000000000002000)
563 1.1 hikaru #define PIP_WQE_WORD2_NOIP_IA UINT64_C(0x0000000000001000)
564 1.1 hikaru #define PIP_WQE_WORD2_NOIP_B UINT64_C(0x0000000000000800)
565 1.1 hikaru #define PIP_WQE_WORD2_NOIP_M UINT64_C(0x0000000000000400)
566 1.1 hikaru #define PIP_WQE_WORD2_NOIP_NI UINT64_C(0x0000000000000200)
567 1.1 hikaru #define PIP_WQE_WORD2_NOIP_RE UINT64_C(0x0000000000000100)
568 1.1 hikaru #define PIP_WQE_WORD2_NOIP_OPECODE UINT64_C(0x00000000000000ff)
569 1.1 hikaru
570 1.1 hikaru /* WORD 3 */
571 1.1 hikaru #define PIP_WQE_WORD3_63 UINT64_C(0x8000000000000000)
572 1.1 hikaru #define PIP_WQE_WORD3_BACK UINT64_C(0x7800000000000000)
573 1.1 hikaru #define PIP_WQE_WORD3_58_56 UINT64_C(0x0700000000000000)
574 1.1 hikaru #define PIP_WQE_WORD3_SIZE UINT64_C(0x00ffff0000000000)
575 1.1 hikaru #define PIP_WQE_WORD3_ADDR UINT64_C(0x000000ffffffffff)
576 1.1 hikaru
577 1.1 hikaru /* opcode for WORD2[LE] */
578 1.1 hikaru #define PIP_WQE_WORD2_LE_OPCODE_MAL 1ULL
579 1.1 hikaru #define PIP_WQE_WORD2_LE_OPCODE_CSUM 2ULL
580 1.1 hikaru #define PIP_WQE_WORD2_LE_OPCODE_UDPLEN 3ULL
581 1.1 hikaru #define PIP_WQE_WORD2_LE_OPCODE_PORT 4ULL
582 1.1 hikaru #define PIP_WQE_WORD2_LE_OPCODE_XXX_5 5ULL
583 1.1 hikaru #define PIP_WQE_WORD2_LE_OPCODE_XXX_6 6ULL
584 1.1 hikaru #define PIP_WQE_WORD2_LE_OPCODE_XXX_7 7ULL
585 1.1 hikaru #define PIP_WQE_WORD2_LE_OPCODE_FINO 8ULL
586 1.1 hikaru #define PIP_WQE_WORD2_LE_OPCODE_NOFL 9ULL
587 1.1 hikaru #define PIP_WQE_WORD2_LE_OPCODE_FINRST 10ULL
588 1.1 hikaru #define PIP_WQE_WORD2_LE_OPCODE_SYNURG 11ULL
589 1.1 hikaru #define PIP_WQE_WORD2_LE_OPCODE_SYNRST 12ULL
590 1.1 hikaru #define PIP_WQE_WORD2_LE_OPCODE_SYNFIN 13ULL
591 1.1 hikaru
592 1.1 hikaru /* opcode for WORD2[IE] */
593 1.1 hikaru #define PIP_WQE_WORD2_IE_OPCODE_NOTIP 1ULL
594 1.1 hikaru #define PIP_WQE_WORD2_IE_OPCODE_CSUM 2ULL
595 1.1 hikaru #define PIP_WQE_WORD2_IE_OPCODE_MALHDR 3ULL
596 1.1 hikaru #define PIP_WQE_WORD2_IE_OPCODE_MAL 4ULL
597 1.1 hikaru #define PIP_WQE_WORD2_IE_OPCODE_TTL 5ULL
598 1.1 hikaru #define PIP_WQE_WORD2_IE_OPCODE_OPT 6ULL
599 1.1 hikaru
600 1.1 hikaru /* opcode for WORD2[RE] */
601 1.1 hikaru #define PIP_WQE_WORD2_RE_OPCODE_PARTIAL 1ULL
602 1.1 hikaru #define PIP_WQE_WORD2_RE_OPCODE_JABBER 2ULL
603 1.1 hikaru #define PIP_WQE_WORD2_RE_OPCODE_OVRRUN 3ULL
604 1.1 hikaru #define PIP_WQE_WORD2_RE_OPCODE_OVRSZ 4ULL
605 1.1 hikaru #define PIP_WQE_WORD2_RE_OPCODE_ALIGN 5ULL
606 1.1 hikaru #define PIP_WQE_WORD2_RE_OPCODE_FRAG 6ULL
607 1.1 hikaru #define PIP_WQE_WORD2_RE_OPCODE_GMXFCS 7ULL
608 1.1 hikaru #define PIP_WQE_WORD2_RE_OPCODE_UDRSZ 8ULL
609 1.1 hikaru #define PIP_WQE_WORD2_RE_OPCODE_EXTEND 9ULL
610 1.1 hikaru #define PIP_WQE_WORD2_RE_OPCODE_LENGTH 10ULL
611 1.1 hikaru #define PIP_WQE_WORD2_RE_OPCODE_MIIRX 11ULL
612 1.1 hikaru #define PIP_WQE_WORD2_RE_OPCODE_MIISKIP 12ULL
613 1.1 hikaru #define PIP_WQE_WORD2_RE_OPCODE_MIINBL 13ULL
614 1.1 hikaru #define PIP_WQE_WORD2_RE_OPCODE_XXX_14 14ULL
615 1.1 hikaru #define PIP_WQE_WORD2_RE_OPCODE_XXX_15 15ULL
616 1.1 hikaru #define PIP_WQE_WORD2_RE_OPCODE_XXX_16 16ULL
617 1.1 hikaru #define PIP_WQE_WORD2_RE_OPCODE_SKIP 17ULL
618 1.1 hikaru #define PIP_WQE_WORD2_RE_OPCODE_L2MAL 18ULL
619 1.1 hikaru
620 1.1 hikaru /* XXX backward compatibility */
621 1.1 hikaru #define PIP_OVER_ERR PIP_WQE_WORD2_RE_OPCODE_OVRRUN
622 1.1 hikaru #define PIP_GMX_FCS_ERR PIP_WQE_WORD2_RE_OPCODE_GMXFCS
623 1.1 hikaru #define PIP_ALIGN_ERR PIP_WQE_WORD2_RE_OPCODE_ALIGN
624 1.1 hikaru
625 1.1 hikaru #define PIP_BIST_STATUS_BITS \
626 1.1 hikaru "\177" /* new format */ \
627 1.1 hikaru "\020" /* hex display */ \
628 1.1 hikaru "\020" /* %016x format */ \
629 1.1 hikaru "f\x12\x2e" "63_13\0" \
630 1.1 hikaru "f\x00\x12" "BIST\0"
631 1.1 hikaru #define PIP_INT_REG_BITS \
632 1.1 hikaru "\177" /* new format */ \
633 1.1 hikaru "\020" /* hex display */ \
634 1.1 hikaru "\020" /* %016x format */ \
635 1.1 hikaru "f\x09\x37" "63_9\0" \
636 1.1 hikaru "b\x08" "BEPERR\0" \
637 1.1 hikaru "b\x07" "FEPERR\0" \
638 1.1 hikaru "b\x06" "6\0" \
639 1.1 hikaru "b\x05" "SKPRUNT\0" \
640 1.1 hikaru "b\x04" "BADTAG\0" \
641 1.1 hikaru "b\x03" "PRTNXA\0" \
642 1.1 hikaru "f\x01\x02" "2_1\0" \
643 1.1 hikaru "b\x00" "PKTDRP\0"
644 1.1 hikaru #define PIP_INT_EN_BITS \
645 1.1 hikaru "\177" /* new format */ \
646 1.1 hikaru "\020" /* hex display */ \
647 1.1 hikaru "\020" /* %016x format */ \
648 1.1 hikaru "f\x09\x37" "63_9\0" \
649 1.1 hikaru "b\x08" "BEPERR\0" \
650 1.1 hikaru "b\x07" "FEPERR\0" \
651 1.1 hikaru "b\x06" "6\0" \
652 1.1 hikaru "b\x05" "SKPRUNT\0" \
653 1.1 hikaru "b\x04" "BADTAG\0" \
654 1.1 hikaru "b\x03" "PRTNXA\0" \
655 1.1 hikaru "f\x01\x02" "2_1\0" \
656 1.1 hikaru "b\x00" "PKTDRP\0"
657 1.1 hikaru #define PIP_STAT_CTL_BITS \
658 1.1 hikaru "\177" /* new format */ \
659 1.1 hikaru "\020" /* hex display */ \
660 1.1 hikaru "\020" /* %016x format */ \
661 1.1 hikaru "f\x01\x3f" "63_1\0" \
662 1.1 hikaru "b\x00" "RDCLR\0"
663 1.1 hikaru #define PIP_GBL_CTL_BITS \
664 1.1 hikaru "\177" /* new format */ \
665 1.1 hikaru "\020" /* hex display */ \
666 1.1 hikaru "\020" /* %016x format */ \
667 1.1 hikaru "f\x11\x2f" "63_17\0" \
668 1.1 hikaru "b\x10" "IGNRS\0" \
669 1.1 hikaru "b\x0f" "VS_WQE\0" \
670 1.1 hikaru "b\x0e" "VS_QOS\0" \
671 1.1 hikaru "b\x0d" "L2MAL\0" \
672 1.1 hikaru "b\x0c" "TCP_FLAG\0" \
673 1.1 hikaru "b\x0b" "L4_LEN\0" \
674 1.1 hikaru "b\x0a" "L4_CHK\0" \
675 1.1 hikaru "b\x09" "L4_PRT\0" \
676 1.1 hikaru "b\x08" "L4_MAL\0" \
677 1.1 hikaru "f\x06\x02" "7_6\0" \
678 1.1 hikaru "f\x04\x02" "IP6_EEXT\0" \
679 1.1 hikaru "b\x03" "IP4_OPTS\0" \
680 1.1 hikaru "b\x02" "IP_HOP\0" \
681 1.1 hikaru "b\x01" "IP_MAL\0" \
682 1.1 hikaru "b\x00" "IP_CHK\0"
683 1.1 hikaru #define PIP_GBL_CFG_BITS \
684 1.1 hikaru "\177" /* new format */ \
685 1.1 hikaru "\020" /* hex display */ \
686 1.1 hikaru "\020" /* %016x format */ \
687 1.1 hikaru "f\x13\x2d" "63_19\0" \
688 1.1 hikaru "b\x12" "TAG_SYN\0" \
689 1.1 hikaru "b\x11" "IP6_UDP\0" \
690 1.1 hikaru "b\x10" "MAX_L2\0" \
691 1.1 hikaru "f\x0b\x05" "15_11\0" \
692 1.1 hikaru "f\x08\x03" "RAW_SHF\0" \
693 1.1 hikaru "f\x03\x05" "7_3\0" \
694 1.1 hikaru "f\x00\x03" "NIP_SHF\0"
695 1.1 hikaru #define PIP_SOFT_RST_BITS \
696 1.1 hikaru "\177" /* new format */ \
697 1.1 hikaru "\020" /* hex display */ \
698 1.1 hikaru "\020" /* %016x format */ \
699 1.1 hikaru
700 1.1 hikaru #define PIP_IP_OFFSET_BITS \
701 1.1 hikaru "\177" /* new format */ \
702 1.1 hikaru "\020" /* hex display */ \
703 1.1 hikaru "\020" /* %016x format */ \
704 1.1 hikaru "f\x03\x3d" "63_3\0" \
705 1.1 hikaru "f\x00\x03" "MASK_OFFSET\0"
706 1.1 hikaru #define PIP_TAG_SECRET_BITS \
707 1.1 hikaru "\177" /* new format */ \
708 1.1 hikaru "\020" /* hex display */ \
709 1.1 hikaru "\020" /* %016x format */ \
710 1.1 hikaru "f\x20\x20" "63_3\0" \
711 1.1 hikaru "f\x10\x10" "DST\0" \
712 1.1 hikaru "f\x00\x10" "SRC\0"
713 1.1 hikaru #define PIP_TAG_MASK_BITS \
714 1.1 hikaru "\177" /* new format */ \
715 1.1 hikaru "\020" /* hex display */ \
716 1.1 hikaru "\020" /* %016x format */ \
717 1.1 hikaru "f\x10\x30" "63_16\0" \
718 1.1 hikaru "f\x00\x10" "MASK\0"
719 1.1 hikaru #define PIP_DEC_IPSECN_BITS \
720 1.1 hikaru "\177" /* new format */ \
721 1.1 hikaru "\020" /* hex display */ \
722 1.1 hikaru "\020" /* %016x format */ \
723 1.1 hikaru "f\x12\x2e" "63_18\0" \
724 1.1 hikaru "b\x11" "TCP\0" \
725 1.1 hikaru "b\x10" "UDP\0" \
726 1.1 hikaru "f\x00\x10" "DPRT\0"
727 1.1 hikaru #define PIP_DEC_IPSEC0_BITS PIP_DEC_IPSECN_BITS
728 1.1 hikaru #define PIP_DEC_IPSEC1_BITS PIP_DEC_IPSECN_BITS
729 1.1 hikaru #define PIP_DEC_IPSEC2_BITS PIP_DEC_IPSECN_BITS
730 1.1 hikaru #define PIP_DEC_IPSEC3_BITS PIP_DEC_IPSECN_BITS
731 1.1 hikaru #define PIP_RAW_WORD_BITS \
732 1.1 hikaru "\177" /* new format */ \
733 1.1 hikaru "\020" /* hex display */ \
734 1.1 hikaru "\020" /* %016x format */ \
735 1.1 hikaru "f\x38\x08" "63_56\0" \
736 1.1 hikaru "f\x00\x38" "WORD\0"
737 1.1 hikaru #define PIP_QOS_VLANN_BITS \
738 1.1 hikaru "\177" /* new format */ \
739 1.1 hikaru "\020" /* hex display */ \
740 1.1 hikaru "\020" /* %016x format */ \
741 1.1 hikaru
742 1.1 hikaru #define PIP_QOS_VLAN0_BITS PIP_QOS_VLANN_BITS
743 1.1 hikaru #define PIP_QOS_VLAN1_BITS PIP_QOS_VLANN_BITS
744 1.1 hikaru #define PIP_QOS_VLAN2_BITS PIP_QOS_VLANN_BITS
745 1.1 hikaru #define PIP_QOS_VLAN3_BITS PIP_QOS_VLANN_BITS
746 1.1 hikaru #define PIP_QOS_VLAN4_BITS PIP_QOS_VLANN_BITS
747 1.1 hikaru #define PIP_QOS_VLAN5_BITS PIP_QOS_VLANN_BITS
748 1.1 hikaru #define PIP_QOS_VLAN6_BITS PIP_QOS_VLANN_BITS
749 1.1 hikaru #define PIP_QOS_VLAN7_BITS PIP_QOS_VLANN_BITS
750 1.1 hikaru #define PIP_QOS_WATCHN_BITS \
751 1.1 hikaru "\177" /* new format */ \
752 1.1 hikaru "\020" /* hex display */ \
753 1.1 hikaru "\020" /* %016x format */ \
754 1.1 hikaru "f\x30\x10" "63_48\0" \
755 1.1 hikaru "f\x20\x10" "MASK\0" \
756 1.1 hikaru "f\x1c\x04" "31_28\0" \
757 1.1 hikaru "f\x18\x04" "GRP\0" \
758 1.1 hikaru "b\x17" "23\0" \
759 1.1 hikaru "f\x14\x03" "WATCHER\0" \
760 1.1 hikaru "f\x12\x02" "19_18\0" \
761 1.1 hikaru "f\x10\x02" "TYPE\0" \
762 1.1 hikaru "f\x00\x10" "15_0\0"
763 1.1 hikaru #define PIP_QOS_WATCH0_BITS PIP_QOS_WATCHN_BITS
764 1.1 hikaru #define PIP_QOS_WATCH1_BITS PIP_QOS_WATCHN_BITS
765 1.1 hikaru #define PIP_QOS_WATCH2_BITS PIP_QOS_WATCHN_BITS
766 1.1 hikaru #define PIP_QOS_WATCH3_BITS PIP_QOS_WATCHN_BITS
767 1.1 hikaru #define PIP_PRT_CFGN_BITS \
768 1.1 hikaru "\177" /* new format */ \
769 1.1 hikaru "\020" /* hex display */ \
770 1.1 hikaru "\020" /* %016x format */ \
771 1.1 hikaru "f\x35\x0b" "63_53\0" \
772 1.1 hikaru "b\x34" "PAD_LEN\0" \
773 1.1 hikaru "b\x33" "VLAN_LEN\0" \
774 1.1 hikaru "b\x32" "LENERR_EN\0" \
775 1.1 hikaru "b\x31" "MAXERR_EN\0" \
776 1.1 hikaru "b\x30" "MINERR_EN\0" \
777 1.1 hikaru "f\x2c\x04" "GRP_WAT_47\0" \
778 1.1 hikaru "f\x28\x04" "QOS_WAT_47\0" \
779 1.1 hikaru "f\x25\x03" "39_37\0" \
780 1.1 hikaru "b\x24" "RAWDRP\0" \
781 1.1 hikaru "f\x22\x02" "TAG_INC\0" \
782 1.1 hikaru "b\x21" "DYN_RS\0" \
783 1.1 hikaru "b\x20" "INST_HDR\0" \
784 1.1 hikaru "f\x1c\x04" "GRP_WAT\0" \
785 1.1 hikaru "b\x1b" "27\0" \
786 1.1 hikaru "f\x18\x03" "QOS\0" \
787 1.1 hikaru "f\x14\x04" "QOS_WAT\0" \
788 1.1 hikaru "b\x13" "19\0" \
789 1.1 hikaru "b\x12" "SPARE\0" \
790 1.1 hikaru "b\x11" "QOS_DIFF\0" \
791 1.1 hikaru "b\x10" "QOS_VLAN\0" \
792 1.1 hikaru "f\x0d\x03" "15_13\0" \
793 1.1 hikaru "b\x0c" "CRC_EN\0" \
794 1.1 hikaru "f\x0a\x02" "11_10\0" \
795 1.1 hikaru "f\x08\x02" "MODE\0" \
796 1.1 hikaru "b\x07" "7\0" \
797 1.1 hikaru "f\x00\x07" "SKIP\0"
798 1.1 hikaru #define PIP_PRT_CFG0_BITS PIP_PRT_CFGN_BITS
799 1.1 hikaru #define PIP_PRT_CFG1_BITS PIP_PRT_CFGN_BITS
800 1.1 hikaru #define PIP_PRT_CFG2_BITS PIP_PRT_CFGN_BITS
801 1.1 hikaru #define PIP_PRT_CFG32_BITS PIP_PRT_CFGN_BITS
802 1.1 hikaru #define PIP_PRT_TAGN_BITS \
803 1.1 hikaru "\177" /* new format */ \
804 1.1 hikaru "\020" /* hex display */ \
805 1.1 hikaru "\020" /* %016x format */ \
806 1.1 hikaru "f\x28\x18" "63_40\0" \
807 1.1 hikaru "f\x24\x04" "GRPTAGBASE\0" \
808 1.1 hikaru "f\x20\x04" "GRPTAGMASK\0" \
809 1.1 hikaru "b\x1f" "GRPTAG\0" \
810 1.1 hikaru "b\x1e" "SPARE\0" \
811 1.1 hikaru "f\x1c\x02" "TAG_MODE\0" \
812 1.1 hikaru "f\x1a\x02" "INC_VS\0" \
813 1.1 hikaru "b\x19" "INC_VLAN\0" \
814 1.1 hikaru "b\x18" "INC_PRT\0" \
815 1.1 hikaru "b\x17" "IP6_DPRT\0" \
816 1.1 hikaru "b\x16" "IP4_DPRT\0" \
817 1.1 hikaru "b\x15" "IP6_SPRT\0" \
818 1.1 hikaru "b\x14" "IP4_SPRT\0" \
819 1.1 hikaru "b\x13" "IP6_NXTH\0" \
820 1.1 hikaru "b\x12" "IP4_PCTL\0" \
821 1.1 hikaru "b\x11" "IP6_DST\0" \
822 1.1 hikaru "b\x10" "IP4_SRC\0" \
823 1.1 hikaru "b\x0f" "IP6_SRC\0" \
824 1.1 hikaru "b\x0e" "IP4_DST\0" \
825 1.1 hikaru "f\x0c\x02" "TCP6_TAG\0" \
826 1.1 hikaru "f\x0a\x02" "TCP4_TAG\0" \
827 1.1 hikaru "f\x08\x02" "IP6_TAG\0" \
828 1.1 hikaru "f\x06\x02" "IP4_TAG\0" \
829 1.1 hikaru "f\x04\x02" "NON_TAG\0" \
830 1.1 hikaru "f\x00\x04" "GRP\0"
831 1.1 hikaru #define PIP_PRT_TAG0_BITS PIP_PRT_TAGN_BITS
832 1.1 hikaru #define PIP_PRT_TAG1_BITS PIP_PRT_TAGN_BITS
833 1.1 hikaru #define PIP_PRT_TAG2_BITS PIP_PRT_TAGN_BITS
834 1.1 hikaru #define PIP_PRT_TAG32_BITS PIP_PRT_TAGN_BITS
835 1.1 hikaru /* PIP_QOS_DIFF[0-63] */
836 1.1 hikaru #define PIP_STAT0_PRTN_BITS \
837 1.1 hikaru "\177" /* new format */ \
838 1.1 hikaru "\020" /* hex display */ \
839 1.1 hikaru "\020" /* %016x format */ \
840 1.1 hikaru "f\x20\x20" "DRP_PKTS\0" \
841 1.1 hikaru "f\x00\x20" "DRP_OCTS\0"
842 1.1 hikaru #define PIP_STAT0_PRT0_BITS PIP_STAT0_PRTN_BITS
843 1.1 hikaru #define PIP_STAT0_PRT1_BITS PIP_STAT0_PRTN_BITS
844 1.1 hikaru #define PIP_STAT0_PRT2_BITS PIP_STAT0_PRTN_BITS
845 1.1 hikaru #define PIP_STAT0_PRT32_BITS PIP_STAT0_PRTN_BITS
846 1.1 hikaru #define PIP_STAT1_PRTN_BITS \
847 1.1 hikaru "\177" /* new format */ \
848 1.1 hikaru "\020" /* hex display */ \
849 1.1 hikaru "\020" /* %016x format */ \
850 1.1 hikaru "f\x30\x10" "63_48\0" \
851 1.1 hikaru "f\x00\x30" "OCTS\0"
852 1.1 hikaru #define PIP_STAT1_PRT0_BITS PIP_STAT1_PRTN_BITS
853 1.1 hikaru #define PIP_STAT1_PRT1_BITS PIP_STAT1_PRTN_BITS
854 1.1 hikaru #define PIP_STAT1_PRT2_BITS PIP_STAT1_PRTN_BITS
855 1.1 hikaru #define PIP_STAT1_PRT32_BITS PIP_STAT1_PRTN_BITS
856 1.1 hikaru #define PIP_STAT2_PRTN_BITS \
857 1.1 hikaru "\177" /* new format */ \
858 1.1 hikaru "\020" /* hex display */ \
859 1.1 hikaru "\020" /* %016x format */ \
860 1.1 hikaru "f\x20\x20" "PKTS\0" \
861 1.1 hikaru "f\x00\x20" "RAW\0"
862 1.1 hikaru #define PIP_STAT2_PRT0_BITS PIP_STAT2_PRTN_BITS
863 1.1 hikaru #define PIP_STAT2_PRT1_BITS PIP_STAT2_PRTN_BITS
864 1.1 hikaru #define PIP_STAT2_PRT2_BITS PIP_STAT2_PRTN_BITS
865 1.1 hikaru #define PIP_STAT2_PRT32_BITS PIP_STAT2_PRTN_BITS
866 1.1 hikaru #define PIP_STAT3_PRTN_BITS \
867 1.1 hikaru "\177" /* new format */ \
868 1.1 hikaru "\020" /* hex display */ \
869 1.1 hikaru "\020" /* %016x format */ \
870 1.1 hikaru "f\x20\x20" "BCST\0" \
871 1.1 hikaru "f\x00\x20" "MCST\0"
872 1.1 hikaru #define PIP_STAT3_PRT0_BITS PIP_STAT3_PRTN_BITS
873 1.1 hikaru #define PIP_STAT3_PRT1_BITS PIP_STAT3_PRTN_BITS
874 1.1 hikaru #define PIP_STAT3_PRT2_BITS PIP_STAT3_PRTN_BITS
875 1.1 hikaru #define PIP_STAT3_PRT32_BITS PIP_STAT3_PRTN_BITS
876 1.1 hikaru #define PIP_STAT4_PRTN_BITS \
877 1.1 hikaru "\177" /* new format */ \
878 1.1 hikaru "\020" /* hex display */ \
879 1.1 hikaru "\020" /* %016x format */ \
880 1.1 hikaru "f\x20\x20" "H65TO127\0" \
881 1.1 hikaru "f\x00\x20" "H64\0"
882 1.1 hikaru #define PIP_STAT4_PRT0_BITS PIP_STAT4_PRTN_BITS
883 1.1 hikaru #define PIP_STAT4_PRT1_BITS PIP_STAT4_PRTN_BITS
884 1.1 hikaru #define PIP_STAT4_PRT2_BITS PIP_STAT4_PRTN_BITS
885 1.1 hikaru #define PIP_STAT4_PRT32_BITS PIP_STAT4_PRTN_BITS
886 1.1 hikaru #define PIP_STAT5_PRTN_BITS \
887 1.1 hikaru "\177" /* new format */ \
888 1.1 hikaru "\020" /* hex display */ \
889 1.1 hikaru "\020" /* %016x format */ \
890 1.1 hikaru "f\x20\x20" "H256TO511\0" \
891 1.1 hikaru "f\x00\x20" "H128TO255\0"
892 1.1 hikaru #define PIP_STAT5_PRT0_BITS PIP_STAT5_PRTN_BITS
893 1.1 hikaru #define PIP_STAT5_PRT1_BITS PIP_STAT5_PRTN_BITS
894 1.1 hikaru #define PIP_STAT5_PRT2_BITS PIP_STAT5_PRTN_BITS
895 1.1 hikaru #define PIP_STAT5_PRT32_BITS PIP_STAT5_PRTN_BITS
896 1.1 hikaru #define PIP_STAT6_PRTN_BITS \
897 1.1 hikaru "\177" /* new format */ \
898 1.1 hikaru "\020" /* hex display */ \
899 1.1 hikaru "\020" /* %016x format */ \
900 1.1 hikaru "f\x20\x20" "H1024TO1518\0" \
901 1.1 hikaru "f\x00\x20" "H512TO1023\0"
902 1.1 hikaru #define PIP_STAT6_PRT0_BITS PIP_STAT6_PRTN_BITS
903 1.1 hikaru #define PIP_STAT6_PRT1_BITS PIP_STAT6_PRTN_BITS
904 1.1 hikaru #define PIP_STAT6_PRT2_BITS PIP_STAT6_PRTN_BITS
905 1.1 hikaru #define PIP_STAT6_PRT32_BITS PIP_STAT6_PRTN_BITS
906 1.1 hikaru #define PIP_STAT7_PRTN_BITS \
907 1.1 hikaru "\177" /* new format */ \
908 1.1 hikaru "\020" /* hex display */ \
909 1.1 hikaru "\020" /* %016x format */ \
910 1.1 hikaru "f\x20\x20" "FCS\0" \
911 1.1 hikaru "f\x00\x20" "H1519\0"
912 1.1 hikaru #define PIP_STAT7_PRT0_BITS PIP_STAT7_PRTN_BITS
913 1.1 hikaru #define PIP_STAT7_PRT1_BITS PIP_STAT7_PRTN_BITS
914 1.1 hikaru #define PIP_STAT7_PRT2_BITS PIP_STAT7_PRTN_BITS
915 1.1 hikaru #define PIP_STAT7_PRT32_BITS PIP_STAT7_PRTN_BITS
916 1.1 hikaru #define PIP_STAT8_PRTN_BITS \
917 1.1 hikaru "\177" /* new format */ \
918 1.1 hikaru "\020" /* hex display */ \
919 1.1 hikaru "\020" /* %016x format */ \
920 1.1 hikaru "f\x20\x20" "FRAG\0" \
921 1.1 hikaru "f\x00\x20" "UNDERSZ\0"
922 1.1 hikaru #define PIP_STAT8_PRT0_BITS PIP_STAT8_PRTN_BITS
923 1.1 hikaru #define PIP_STAT8_PRT1_BITS PIP_STAT8_PRTN_BITS
924 1.1 hikaru #define PIP_STAT8_PRT2_BITS PIP_STAT8_PRTN_BITS
925 1.1 hikaru #define PIP_STAT8_PRT32_BITS PIP_STAT8_PRTN_BITS
926 1.1 hikaru #define PIP_STAT9_PRTN_BITS \
927 1.1 hikaru "\177" /* new format */ \
928 1.1 hikaru "\020" /* hex display */ \
929 1.1 hikaru "\020" /* %016x format */ \
930 1.1 hikaru "f\x20\x20" "JABBER\0" \
931 1.1 hikaru "f\x00\x20" "OVERSZ\0"
932 1.1 hikaru #define PIP_STAT9_PRT0_BITS PIP_STAT9_PRTN_BITS
933 1.1 hikaru #define PIP_STAT9_PRT1_BITS PIP_STAT9_PRTN_BITS
934 1.1 hikaru #define PIP_STAT9_PRT2_BITS PIP_STAT9_PRTN_BITS
935 1.1 hikaru #define PIP_STAT9_PRT32_BITS PIP_STAT9_PRTN_BITS
936 1.1 hikaru /* PIP_TAG_INC[0-63] */
937 1.1 hikaru #define PIP_STAT_INB_PKTSN_BITS \
938 1.1 hikaru "\177" /* new format */ \
939 1.1 hikaru "\020" /* hex display */ \
940 1.1 hikaru "\020" /* %016x format */ \
941 1.1 hikaru "f\x20\x20" "PIP_STAT_INB_PKTSN\0" \
942 1.1 hikaru "f\x00\x20" "PKTS\0"
943 1.1 hikaru #define PIP_STAT_INB_PKTS0_BITS PIP_STAT_INB_PKTSN_BITS
944 1.1 hikaru #define PIP_STAT_INB_PKTS1_BITS PIP_STAT_INB_PKTSN_BITS
945 1.1 hikaru #define PIP_STAT_INB_PKTS2_BITS PIP_STAT_INB_PKTSN_BITS
946 1.1 hikaru #define PIP_STAT_INB_PKTS32_BITS PIP_STAT_INB_PKTSN_BITS
947 1.1 hikaru #define PIP_STAT_INB_OCTSN_BITS \
948 1.1 hikaru "\177" /* new format */ \
949 1.1 hikaru "\020" /* hex display */ \
950 1.1 hikaru "\020" /* %016x format */ \
951 1.1 hikaru "f\x30\x10" "PIP_STAT_INB_OCTSN\0" \
952 1.1 hikaru "f\x00\x30" "OCTS\0"
953 1.1 hikaru #define PIP_STAT_INB_OCTS0_BITS PIP_STAT_INB_OCTSN_BITS
954 1.1 hikaru #define PIP_STAT_INB_OCTS1_BITS PIP_STAT_INB_OCTSN_BITS
955 1.1 hikaru #define PIP_STAT_INB_OCTS2_BITS PIP_STAT_INB_OCTSN_BITS
956 1.1 hikaru #define PIP_STAT_INB_OCTS32_BITS PIP_STAT_INB_OCTSN_BITS
957 1.1 hikaru #define PIP_STAT_INB_ERRSN_BITS \
958 1.1 hikaru "\177" /* new format */ \
959 1.1 hikaru "\020" /* hex display */ \
960 1.1 hikaru "\020" /* %016x format */ \
961 1.1 hikaru "f\x10\x30" "PIP_STAT_INB_ERRSN\0" \
962 1.1 hikaru "f\x00\x10" "OCTS\0"
963 1.1 hikaru #define PIP_STAT_INB_ERRS0_BITS PIP_STAT_INB_ERRSN_BITS
964 1.1 hikaru #define PIP_STAT_INB_ERRS1_BITS PIP_STAT_INB_ERRSN_BITS
965 1.1 hikaru #define PIP_STAT_INB_ERRS2_BITS PIP_STAT_INB_ERRSN_BITS
966 1.1 hikaru #define PIP_STAT_INB_ERRS32_BITS PIP_STAT_INB_ERRSN_BITS
967 1.1 hikaru
968 1.1 hikaru #endif /* _OCTEON_PIPREG_H_ */
969