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octeon_powreg.h revision 1.1
      1  1.1  hikaru /*	$NetBSD: octeon_powreg.h,v 1.1 2015/04/29 08:32:01 hikaru Exp $	*/
      2  1.1  hikaru 
      3  1.1  hikaru /*
      4  1.1  hikaru  * Copyright (c) 2007 Internet Initiative Japan, Inc.
      5  1.1  hikaru  * All rights reserved.
      6  1.1  hikaru  *
      7  1.1  hikaru  * Redistribution and use in source and binary forms, with or without
      8  1.1  hikaru  * modification, are permitted provided that the following conditions
      9  1.1  hikaru  * are met:
     10  1.1  hikaru  * 1. Redistributions of source code must retain the above copyright
     11  1.1  hikaru  *    notice, this list of conditions and the following disclaimer.
     12  1.1  hikaru  * 2. Redistributions in binary form must reproduce the above copyright
     13  1.1  hikaru  *    notice, this list of conditions and the following disclaimer in the
     14  1.1  hikaru  *    documentation and/or other materials provided with the distribution.
     15  1.1  hikaru  *
     16  1.1  hikaru  * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
     17  1.1  hikaru  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
     18  1.1  hikaru  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
     19  1.1  hikaru  * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
     20  1.1  hikaru  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
     21  1.1  hikaru  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
     22  1.1  hikaru  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
     23  1.1  hikaru  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
     24  1.1  hikaru  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
     25  1.1  hikaru  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
     26  1.1  hikaru  * SUCH DAMAGE.
     27  1.1  hikaru  */
     28  1.1  hikaru 
     29  1.1  hikaru /*
     30  1.1  hikaru  * POW Registers
     31  1.1  hikaru  */
     32  1.1  hikaru 
     33  1.1  hikaru #ifndef _OCTEON_POWREG_H_
     34  1.1  hikaru #define _OCTEON_POWREG_H_
     35  1.1  hikaru 
     36  1.1  hikaru /* ---- register addresses */
     37  1.1  hikaru 
     38  1.1  hikaru #define	POW_PP_GRP_MSK0				UINT64_C(0x0001670000000000)
     39  1.1  hikaru #define	POW_PP_GRP_MSK1				UINT64_C(0x0001670000000008)
     40  1.1  hikaru #define	POW_WQ_INT_THR0				UINT64_C(0x0001670000000080)
     41  1.1  hikaru #define	POW_WQ_INT_THR1				UINT64_C(0x0001670000000088)
     42  1.1  hikaru #define	POW_WQ_INT_THR2				UINT64_C(0x0001670000000090)
     43  1.1  hikaru #define	POW_WQ_INT_THR3				UINT64_C(0x0001670000000098)
     44  1.1  hikaru #define	POW_WQ_INT_THR4				UINT64_C(0x00016700000000a0)
     45  1.1  hikaru #define	POW_WQ_INT_THR5				UINT64_C(0x00016700000000a8)
     46  1.1  hikaru #define	POW_WQ_INT_THR6				UINT64_C(0x00016700000000b0)
     47  1.1  hikaru #define	POW_WQ_INT_THR7				UINT64_C(0x00016700000000b8)
     48  1.1  hikaru #define	POW_WQ_INT_THR8				UINT64_C(0x00016700000000c0)
     49  1.1  hikaru #define	POW_WQ_INT_THR9				UINT64_C(0x00016700000000c8)
     50  1.1  hikaru #define	POW_WQ_INT_THR10			UINT64_C(0x00016700000000d0)
     51  1.1  hikaru #define	POW_WQ_INT_THR11			UINT64_C(0x00016700000000d8)
     52  1.1  hikaru #define	POW_WQ_INT_THR12			UINT64_C(0x00016700000000e0)
     53  1.1  hikaru #define	POW_WQ_INT_THR13			UINT64_C(0x00016700000000e8)
     54  1.1  hikaru #define	POW_WQ_INT_THR14			UINT64_C(0x00016700000000f0)
     55  1.1  hikaru #define	POW_WQ_INT_THR15			UINT64_C(0x00016700000000f8)
     56  1.1  hikaru #define	POW_WQ_INT_CNT0				UINT64_C(0x0001670000000100)
     57  1.1  hikaru #define	POW_WQ_INT_CNT1				UINT64_C(0x0001670000000108)
     58  1.1  hikaru #define	POW_WQ_INT_CNT2				UINT64_C(0x0001670000000110)
     59  1.1  hikaru #define	POW_WQ_INT_CNT3				UINT64_C(0x0001670000000118)
     60  1.1  hikaru #define	POW_WQ_INT_CNT4				UINT64_C(0x0001670000000120)
     61  1.1  hikaru #define	POW_WQ_INT_CNT5				UINT64_C(0x0001670000000128)
     62  1.1  hikaru #define	POW_WQ_INT_CNT6				UINT64_C(0x0001670000000130)
     63  1.1  hikaru #define	POW_WQ_INT_CNT7				UINT64_C(0x0001670000000138)
     64  1.1  hikaru #define	POW_WQ_INT_CNT8				UINT64_C(0x0001670000000140)
     65  1.1  hikaru #define	POW_WQ_INT_CNT9				UINT64_C(0x0001670000000148)
     66  1.1  hikaru #define	POW_WQ_INT_CNT10			UINT64_C(0x0001670000000150)
     67  1.1  hikaru #define	POW_WQ_INT_CNT11			UINT64_C(0x0001670000000158)
     68  1.1  hikaru #define	POW_WQ_INT_CNT12			UINT64_C(0x0001670000000160)
     69  1.1  hikaru #define	POW_WQ_INT_CNT13			UINT64_C(0x0001670000000168)
     70  1.1  hikaru #define	POW_WQ_INT_CNT14			UINT64_C(0x0001670000000170)
     71  1.1  hikaru #define	POW_WQ_INT_CNT15			UINT64_C(0x0001670000000178)
     72  1.1  hikaru #define	POW_QOS_THR0				UINT64_C(0x0001670000000180)
     73  1.1  hikaru #define	POW_QOS_THR1				UINT64_C(0x0001670000000188)
     74  1.1  hikaru #define	POW_QOS_THR2				UINT64_C(0x0001670000000190)
     75  1.1  hikaru #define	POW_QOS_THR3				UINT64_C(0x0001670000000198)
     76  1.1  hikaru #define	POW_QOS_THR4				UINT64_C(0x00016700000001a0)
     77  1.1  hikaru #define	POW_QOS_THR5				UINT64_C(0x00016700000001a8)
     78  1.1  hikaru #define	POW_QOS_THR6				UINT64_C(0x00016700000001b0)
     79  1.1  hikaru #define	POW_QOS_THR7				UINT64_C(0x00016700000001b8)
     80  1.1  hikaru #define	POW_QOS_RND0				UINT64_C(0x00016700000001c0)
     81  1.1  hikaru #define	POW_QOS_RND1				UINT64_C(0x00016700000001c8)
     82  1.1  hikaru #define	POW_QOS_RND2				UINT64_C(0x00016700000001d0)
     83  1.1  hikaru #define	POW_QOS_RND3				UINT64_C(0x00016700000001d8)
     84  1.1  hikaru #define	POW_QOS_RND4				UINT64_C(0x00016700000001e0)
     85  1.1  hikaru #define	POW_QOS_RND5				UINT64_C(0x00016700000001e8)
     86  1.1  hikaru #define	POW_QOS_RND6				UINT64_C(0x00016700000001f0)
     87  1.1  hikaru #define	POW_QOS_RND7				UINT64_C(0x00016700000001f8)
     88  1.1  hikaru #define	POW_WQ_INT				UINT64_C(0x0001670000000200)
     89  1.1  hikaru #define	POW_WQ_INT_PC				UINT64_C(0x0001670000000208)
     90  1.1  hikaru #define	POW_NW_TIM				UINT64_C(0x0001670000000210)
     91  1.1  hikaru #define	POW_ECC_ERR				UINT64_C(0x0001670000000218)
     92  1.1  hikaru #define	POW_NOS_CNT				UINT64_C(0x0001670000000220)
     93  1.1  hikaru #define	POW_WS_PC0				UINT64_C(0x0001670000000280)
     94  1.1  hikaru #define	POW_WS_PC1				UINT64_C(0x0001670000000288)
     95  1.1  hikaru #define	POW_WS_PC2				UINT64_C(0x0001670000000290)
     96  1.1  hikaru #define	POW_WS_PC3				UINT64_C(0x0001670000000298)
     97  1.1  hikaru #define	POW_WS_PC4				UINT64_C(0x00016700000002a0)
     98  1.1  hikaru #define	POW_WS_PC5				UINT64_C(0x00016700000002a8)
     99  1.1  hikaru #define	POW_WS_PC6				UINT64_C(0x00016700000002b0)
    100  1.1  hikaru #define	POW_WS_PC7				UINT64_C(0x00016700000002b8)
    101  1.1  hikaru #define	POW_WS_PC8				UINT64_C(0x00016700000002c0)
    102  1.1  hikaru #define	POW_WS_PC9				UINT64_C(0x00016700000002c8)
    103  1.1  hikaru #define	POW_WS_PC10				UINT64_C(0x00016700000002d0)
    104  1.1  hikaru #define	POW_WS_PC11				UINT64_C(0x00016700000002d8)
    105  1.1  hikaru #define	POW_WS_PC12				UINT64_C(0x00016700000002e0)
    106  1.1  hikaru #define	POW_WS_PC13				UINT64_C(0x00016700000002e8)
    107  1.1  hikaru #define	POW_WS_PC14				UINT64_C(0x00016700000002f0)
    108  1.1  hikaru #define	POW_WS_PC15				UINT64_C(0x00016700000002f8)
    109  1.1  hikaru #define	POW_WA_PC0				UINT64_C(0x0001670000000300)
    110  1.1  hikaru #define	POW_WA_PC1				UINT64_C(0x0001670000000308)
    111  1.1  hikaru #define	POW_WA_PC2				UINT64_C(0x0001670000000310)
    112  1.1  hikaru #define	POW_WA_PC3				UINT64_C(0x0001670000000318)
    113  1.1  hikaru #define	POW_WA_PC4				UINT64_C(0x0001670000000320)
    114  1.1  hikaru #define	POW_WA_PC5				UINT64_C(0x0001670000000328)
    115  1.1  hikaru #define	POW_WA_PC6				UINT64_C(0x0001670000000330)
    116  1.1  hikaru #define	POW_WA_PC7				UINT64_C(0x0001670000000338)
    117  1.1  hikaru #define	POW_IQ_CNT0				UINT64_C(0x0001670000000340)
    118  1.1  hikaru #define	POW_IQ_CNT1				UINT64_C(0x0001670000000348)
    119  1.1  hikaru #define	POW_IQ_CNT2				UINT64_C(0x0001670000000350)
    120  1.1  hikaru #define	POW_IQ_CNT3				UINT64_C(0x0001670000000358)
    121  1.1  hikaru #define	POW_IQ_CNT4				UINT64_C(0x0001670000000360)
    122  1.1  hikaru #define	POW_IQ_CNT5				UINT64_C(0x0001670000000368)
    123  1.1  hikaru #define	POW_IQ_CNT6				UINT64_C(0x0001670000000370)
    124  1.1  hikaru #define	POW_IQ_CNT7				UINT64_C(0x0001670000000378)
    125  1.1  hikaru #define	POW_WA_COM_PC				UINT64_C(0x0001670000000380)
    126  1.1  hikaru #define	POW_IQ_COM_CNT				UINT64_C(0x0001670000000388)
    127  1.1  hikaru #define	POW_TS_PC				UINT64_C(0x0001670000000390)
    128  1.1  hikaru #define	POW_DS_PC				UINT64_C(0x0001670000000398)
    129  1.1  hikaru #define	POW_BIST_STAT				UINT64_C(0x00016700000003f8)
    130  1.1  hikaru 
    131  1.1  hikaru #define POW_BASE				UINT64_C(0x0001670000000000)
    132  1.1  hikaru #define POW_SIZE				UINT64_C(0x400)
    133  1.1  hikaru 
    134  1.1  hikaru #define	POW_PP_GRP_MSK0_OFFSET			UINT64_C(0x0)
    135  1.1  hikaru #define	POW_PP_GRP_MSK1_OFFSET			UINT64_C(0x8)
    136  1.1  hikaru #define	POW_WQ_INT_THR0_OFFSET			UINT64_C(0x80)
    137  1.1  hikaru #define	POW_WQ_INT_THR1_OFFSET			UINT64_C(0x88)
    138  1.1  hikaru #define	POW_WQ_INT_THR2_OFFSET			UINT64_C(0x90)
    139  1.1  hikaru #define	POW_WQ_INT_THR3_OFFSET			UINT64_C(0x98)
    140  1.1  hikaru #define	POW_WQ_INT_THR4_OFFSET			UINT64_C(0xa0)
    141  1.1  hikaru #define	POW_WQ_INT_THR5_OFFSET			UINT64_C(0xa8)
    142  1.1  hikaru #define	POW_WQ_INT_THR6_OFFSET			UINT64_C(0xb0)
    143  1.1  hikaru #define	POW_WQ_INT_THR7_OFFSET			UINT64_C(0xb8)
    144  1.1  hikaru #define	POW_WQ_INT_THR8_OFFSET			UINT64_C(0xc0)
    145  1.1  hikaru #define	POW_WQ_INT_THR9_OFFSET			UINT64_C(0xc8)
    146  1.1  hikaru #define	POW_WQ_INT_THR10_OFFSET			UINT64_C(0xd0)
    147  1.1  hikaru #define	POW_WQ_INT_THR11_OFFSET			UINT64_C(0xd8)
    148  1.1  hikaru #define	POW_WQ_INT_THR12_OFFSET			UINT64_C(0xe0)
    149  1.1  hikaru #define	POW_WQ_INT_THR13_OFFSET			UINT64_C(0xe8)
    150  1.1  hikaru #define	POW_WQ_INT_THR14_OFFSET			UINT64_C(0xf0)
    151  1.1  hikaru #define	POW_WQ_INT_THR15_OFFSET			UINT64_C(0xf8)
    152  1.1  hikaru #define	POW_WQ_INT_CNT0_OFFSET			UINT64_C(0x100)
    153  1.1  hikaru #define	POW_WQ_INT_CNT1_OFFSET			UINT64_C(0x108)
    154  1.1  hikaru #define	POW_WQ_INT_CNT2_OFFSET			UINT64_C(0x110)
    155  1.1  hikaru #define	POW_WQ_INT_CNT3_OFFSET			UINT64_C(0x118)
    156  1.1  hikaru #define	POW_WQ_INT_CNT4_OFFSET			UINT64_C(0x120)
    157  1.1  hikaru #define	POW_WQ_INT_CNT5_OFFSET			UINT64_C(0x128)
    158  1.1  hikaru #define	POW_WQ_INT_CNT6_OFFSET			UINT64_C(0x130)
    159  1.1  hikaru #define	POW_WQ_INT_CNT7_OFFSET			UINT64_C(0x138)
    160  1.1  hikaru #define	POW_WQ_INT_CNT8_OFFSET			UINT64_C(0x140)
    161  1.1  hikaru #define	POW_WQ_INT_CNT9_OFFSET			UINT64_C(0x148)
    162  1.1  hikaru #define	POW_WQ_INT_CNT10_OFFSET			UINT64_C(0x150)
    163  1.1  hikaru #define	POW_WQ_INT_CNT11_OFFSET			UINT64_C(0x158)
    164  1.1  hikaru #define	POW_WQ_INT_CNT12_OFFSET			UINT64_C(0x160)
    165  1.1  hikaru #define	POW_WQ_INT_CNT13_OFFSET			UINT64_C(0x168)
    166  1.1  hikaru #define	POW_WQ_INT_CNT14_OFFSET			UINT64_C(0x170)
    167  1.1  hikaru #define	POW_WQ_INT_CNT15_OFFSET			UINT64_C(0x178)
    168  1.1  hikaru #define	POW_QOS_THR0_OFFSET			UINT64_C(0x180)
    169  1.1  hikaru #define	POW_QOS_THR1_OFFSET			UINT64_C(0x188)
    170  1.1  hikaru #define	POW_QOS_THR2_OFFSET			UINT64_C(0x190)
    171  1.1  hikaru #define	POW_QOS_THR3_OFFSET			UINT64_C(0x198)
    172  1.1  hikaru #define	POW_QOS_THR4_OFFSET			UINT64_C(0x1a0)
    173  1.1  hikaru #define	POW_QOS_THR5_OFFSET			UINT64_C(0x1a8)
    174  1.1  hikaru #define	POW_QOS_THR6_OFFSET			UINT64_C(0x1b0)
    175  1.1  hikaru #define	POW_QOS_THR7_OFFSET			UINT64_C(0x1b8)
    176  1.1  hikaru #define	POW_QOS_RND0_OFFSET			UINT64_C(0x1c0)
    177  1.1  hikaru #define	POW_QOS_RND1_OFFSET			UINT64_C(0x1c8)
    178  1.1  hikaru #define	POW_QOS_RND2_OFFSET			UINT64_C(0x1d0)
    179  1.1  hikaru #define	POW_QOS_RND3_OFFSET			UINT64_C(0x1d8)
    180  1.1  hikaru #define	POW_QOS_RND4_OFFSET			UINT64_C(0x1e0)
    181  1.1  hikaru #define	POW_QOS_RND5_OFFSET			UINT64_C(0x1e8)
    182  1.1  hikaru #define	POW_QOS_RND6_OFFSET			UINT64_C(0x1f0)
    183  1.1  hikaru #define	POW_QOS_RND7_OFFSET			UINT64_C(0x1f8)
    184  1.1  hikaru #define	POW_WQ_INT_OFFSET			UINT64_C(0x200)
    185  1.1  hikaru #define	POW_WQ_INT_PC_OFFSET			UINT64_C(0x208)
    186  1.1  hikaru #define	POW_NW_TIM_OFFSET			UINT64_C(0x210)
    187  1.1  hikaru #define	POW_ECC_ERR_OFFSET			UINT64_C(0x218)
    188  1.1  hikaru #define	POW_NOS_CNT_OFFSET			UINT64_C(0x220)
    189  1.1  hikaru #define	POW_WS_PC0_OFFSET			UINT64_C(0x280)
    190  1.1  hikaru #define	POW_WS_PC1_OFFSET			UINT64_C(0x288)
    191  1.1  hikaru #define	POW_WS_PC2_OFFSET			UINT64_C(0x290)
    192  1.1  hikaru #define	POW_WS_PC3_OFFSET			UINT64_C(0x298)
    193  1.1  hikaru #define	POW_WS_PC4_OFFSET			UINT64_C(0x2a0)
    194  1.1  hikaru #define	POW_WS_PC5_OFFSET			UINT64_C(0x2a8)
    195  1.1  hikaru #define	POW_WS_PC6_OFFSET			UINT64_C(0x2b0)
    196  1.1  hikaru #define	POW_WS_PC7_OFFSET			UINT64_C(0x2b8)
    197  1.1  hikaru #define	POW_WS_PC8_OFFSET			UINT64_C(0x2c0)
    198  1.1  hikaru #define	POW_WS_PC9_OFFSET			UINT64_C(0x2c8)
    199  1.1  hikaru #define	POW_WS_PC10_OFFSET			UINT64_C(0x2d0)
    200  1.1  hikaru #define	POW_WS_PC11_OFFSET			UINT64_C(0x2d8)
    201  1.1  hikaru #define	POW_WS_PC12_OFFSET			UINT64_C(0x2e0)
    202  1.1  hikaru #define	POW_WS_PC13_OFFSET			UINT64_C(0x2e8)
    203  1.1  hikaru #define	POW_WS_PC14_OFFSET			UINT64_C(0x2f0)
    204  1.1  hikaru #define	POW_WS_PC15_OFFSET			UINT64_C(0x2f8)
    205  1.1  hikaru #define	POW_WA_PC0_OFFSET			UINT64_C(0x300)
    206  1.1  hikaru #define	POW_WA_PC1_OFFSET			UINT64_C(0x308)
    207  1.1  hikaru #define	POW_WA_PC2_OFFSET			UINT64_C(0x310)
    208  1.1  hikaru #define	POW_WA_PC3_OFFSET			UINT64_C(0x318)
    209  1.1  hikaru #define	POW_WA_PC4_OFFSET			UINT64_C(0x320)
    210  1.1  hikaru #define	POW_WA_PC5_OFFSET			UINT64_C(0x328)
    211  1.1  hikaru #define	POW_WA_PC6_OFFSET			UINT64_C(0x330)
    212  1.1  hikaru #define	POW_WA_PC7_OFFSET			UINT64_C(0x338)
    213  1.1  hikaru #define	POW_IQ_CNT0_OFFSET			UINT64_C(0x340)
    214  1.1  hikaru #define	POW_IQ_CNT1_OFFSET			UINT64_C(0x348)
    215  1.1  hikaru #define	POW_IQ_CNT2_OFFSET			UINT64_C(0x350)
    216  1.1  hikaru #define	POW_IQ_CNT3_OFFSET			UINT64_C(0x358)
    217  1.1  hikaru #define	POW_IQ_CNT4_OFFSET			UINT64_C(0x360)
    218  1.1  hikaru #define	POW_IQ_CNT5_OFFSET			UINT64_C(0x368)
    219  1.1  hikaru #define	POW_IQ_CNT6_OFFSET			UINT64_C(0x370)
    220  1.1  hikaru #define	POW_IQ_CNT7_OFFSET			UINT64_C(0x378)
    221  1.1  hikaru #define	POW_WA_COM_PC_OFFSET			UINT64_C(0x380)
    222  1.1  hikaru #define	POW_IQ_COM_CNT_OFFSET			UINT64_C(0x388)
    223  1.1  hikaru #define	POW_TS_PC_OFFSET			UINT64_C(0x390)
    224  1.1  hikaru #define	POW_DS_PC_OFFSET			UINT64_C(0x398)
    225  1.1  hikaru #define	POW_BIST_STAT_OFFSET			UINT64_C(0x3f8)
    226  1.1  hikaru 
    227  1.1  hikaru /* ---- register bits */
    228  1.1  hikaru 
    229  1.1  hikaru #define	POW_PP_GRP_MSKX_XXX_63_16		UINT64_C(0xffffffffffff0000)
    230  1.1  hikaru #define	POW_PP_GRP_MSKX_GRP_MSK			UINT64_C(0x000000000000ffff)
    231  1.1  hikaru #define	 POW_PP_GRP_MSKX_GRP_MSK_SHIFT		0
    232  1.1  hikaru 
    233  1.1  hikaru #define	POW_WQ_INT_THRX_XXX_63_29		UINT64_C(0xffffffffe0000000)
    234  1.1  hikaru #define	POW_WQ_INT_THRX_TC_EN			UINT64_C(0x0000000010000000)
    235  1.1  hikaru #define	POW_WQ_INT_THRX_TC_THR			UINT64_C(0x000000000f000000)
    236  1.1  hikaru #define	 POW_WQ_INT_THRX_TC_THR_SHIFT		24
    237  1.1  hikaru #define	POW_WQ_INT_THRX_XXX_23_18		UINT64_C(0x0000000000fc0000)
    238  1.1  hikaru #define	POW_WQ_INT_THRX_DS_THR			UINT64_C(0x000000000003f000)
    239  1.1  hikaru #define	 POW_WQ_INT_THRX_DS_THR_SHIFT		12
    240  1.1  hikaru #define	POW_WQ_INT_THRX_XXX_11_6		UINT64_C(0x0000000000000fc0)
    241  1.1  hikaru #define	POW_WQ_INT_THRX_IQ_THR			UINT64_C(0x000000000000003f)
    242  1.1  hikaru #define	 POW_WQ_INT_THRX_IQ_THR_SHIFT		0
    243  1.1  hikaru 
    244  1.1  hikaru #define	POW_WQ_INT_CNTX_XXX_63_28		UINT64_C(0xfffffffff0000000)
    245  1.1  hikaru #define	POW_WQ_INT_CNTX_TC_CNT			UINT64_C(0x000000000f000000)
    246  1.1  hikaru #define	 POW_WQ_INT_CNTX_TC_CNT_SHIFT		24
    247  1.1  hikaru #define	POW_WQ_INT_CNTX_XXX_23_18		UINT64_C(0x0000000000fc0000)
    248  1.1  hikaru #define	POW_WQ_INT_CNTX_DS_CNT			UINT64_C(0x000000000003f000)
    249  1.1  hikaru #define	 POW_WQ_INT_CNTX_DS_CNT_SHIFT		12
    250  1.1  hikaru #define	POW_WQ_INT_CNTX_XXX_11_6		UINT64_C(0x0000000000000fc0)
    251  1.1  hikaru #define	POW_WQ_INT_CNTX_IQ_CNT			UINT64_C(0x000000000000003f)
    252  1.1  hikaru #define	 POW_WQ_INT_CNTX_IQ_CNT_SHIFT		0
    253  1.1  hikaru 
    254  1.1  hikaru #define	POW_QOS_THRX_XXX_63_55			UINT64_C(0xff80000000000000)
    255  1.1  hikaru #define	POW_QOS_THRX_DES_CNT			UINT64_C(0x007f000000000000)
    256  1.1  hikaru #define	 POW_QOS_THRX_DES_CNT_SHIFT		48
    257  1.1  hikaru #define	POW_QOS_THRX_XXX_47_43			UINT64_C(0x0000f80000000000)
    258  1.1  hikaru #define	POW_QOS_THRX_BUF_CNT			UINT64_C(0x000007f000000000)
    259  1.1  hikaru #define	 POW_QOS_THRX_BUF_CNT_SHIFT		36
    260  1.1  hikaru #define	POW_QOS_THRX_XXX_35_31			UINT64_C(0x0000000f80000000)
    261  1.1  hikaru #define	POW_QOS_THRX_FREE_CNT			UINT64_C(0x000000007f000000)
    262  1.1  hikaru #define	 POW_QOS_THRX_FREE_CNT_SHIFT		24
    263  1.1  hikaru #define	POW_QOS_THRX_XXX_23_18			UINT64_C(0x0000000000fc0000)
    264  1.1  hikaru #define	POW_QOS_THRX_MAX_THR			UINT64_C(0x000000000003f000)
    265  1.1  hikaru #define	 POW_QOS_THRX_MAX_THR_SHIFT		12
    266  1.1  hikaru #define	POW_QOS_THRX_XXX_11_6			UINT64_C(0x0000000000000fc0)
    267  1.1  hikaru #define	POW_QOS_THRX_MIN_THR			UINT64_C(0x000000000000003f)
    268  1.1  hikaru #define	 POW_QOS_THRX_MIN_THR_SHIFT		0
    269  1.1  hikaru 
    270  1.1  hikaru #define	POW_QOS_RNDX_XXX_63_32			UINT64_C(0xffffffff00000000)
    271  1.1  hikaru #define	POW_QOS_RNDX_RND_P3			UINT64_C(0x00000000ff000000)
    272  1.1  hikaru #define	 POW_QOS_RNDX_RND_P3_SHIFT		24
    273  1.1  hikaru #define	POW_QOS_RNDX_RND_P2			UINT64_C(0x0000000000ff0000)
    274  1.1  hikaru #define	 POW_QOS_RNDX_RND_P2_SHIFT		16
    275  1.1  hikaru #define	POW_QOS_RNDX_RND_P1			UINT64_C(0x000000000000ff00)
    276  1.1  hikaru #define	 POW_QOS_RNDX_RND_P1_SHIFT		8
    277  1.1  hikaru #define	POW_QOS_RNDX_RND			UINT64_C(0x00000000000000ff)
    278  1.1  hikaru #define	 POW_QOS_RNDX_RND_SHIFT			0
    279  1.1  hikaru 
    280  1.1  hikaru #define	POW_WQ_INT_XXX_63_32			UINT64_C(0xffffffff00000000)
    281  1.1  hikaru #define	POW_WQ_INT_IQ_DIS			UINT64_C(0x00000000ffff0000)
    282  1.1  hikaru #define	 POW_WQ_INT_IQ_DIS_SHIFT		16
    283  1.1  hikaru #define	POW_WQ_INT_WQ_INT			UINT64_C(0x000000000000ffff)
    284  1.1  hikaru #define	 POW_WQ_INT_WQ_INT_SHIFT		0
    285  1.1  hikaru 
    286  1.1  hikaru #define	POW_WQ_INT_PC_XXX_63_60			UINT64_C(0xf000000000000000)
    287  1.1  hikaru #define	POW_WQ_INT_PC_PC			UINT64_C(0x0fffffff00000000)
    288  1.1  hikaru #define	 POW_WQ_INT_PC_PC_SHIFT			32
    289  1.1  hikaru #define	POW_WQ_INT_PC_XXX_31_28			UINT64_C(0x00000000f0000000)
    290  1.1  hikaru #define	POW_WQ_INT_PC_PC_THR			UINT64_C(0x000000000fffff00)
    291  1.1  hikaru #define	 POW_WQ_INT_PC_PC_THR_SHIFT		8
    292  1.1  hikaru #define	POW_WQ_INT_PC_XXX_7_0			UINT64_C(0x00000000000000ff)
    293  1.1  hikaru 
    294  1.1  hikaru #define	POW_NW_TIM_XXX_63_10			UINT64_C(0xfffffffffffffc00)
    295  1.1  hikaru #define	POW_NW_TIM_NW_TIM			UINT64_C(0x00000000000003ff)
    296  1.1  hikaru #define	 POW_NW_TIM_NW_TIM_SHIFT		0
    297  1.1  hikaru 
    298  1.1  hikaru #define	POW_ECC_ERR_XXX_63_45			UINT64_C(0xffffe00000000000)
    299  1.1  hikaru #define	POW_ECC_ERR_IOP_IE			UINT64_C(0x00001fff00000000)
    300  1.1  hikaru #define	 POW_ECC_ERR_IOP_IE_SHIFT		32
    301  1.1  hikaru #define	POW_ECC_ERR_XXX_31_29			UINT64_C(0x00000000e0000000)
    302  1.1  hikaru #define	POW_ECC_ERR_IOP				UINT64_C(0x000000001fff0000)
    303  1.1  hikaru #define	 POW_ECC_ERR_IOP_SHIFT			16
    304  1.1  hikaru #define	  POW_ECC_ERR_IOP_CSRPEND		(UINT64_C(28) << POW_ECC_ERR_IOP_SHIFT)
    305  1.1  hikaru #define	  POW_ECC_ERR_IOP_DBGPEND		(UINT64_C(27) << POW_ECC_ERR_IOP_SHIFT)
    306  1.1  hikaru #define	  POW_ECC_ERR_IOP_ADDWORK		(UINT64_C(26) << POW_ECC_ERR_IOP_SHIFT)
    307  1.1  hikaru #define	  POW_ECC_ERR_IOP_ILLOP			(UINT64_C(25) << POW_ECC_ERR_IOP_SHIFT)
    308  1.1  hikaru #define	  POW_ECC_ERR_IOP_PEND24		(UINT64_C(24) << POW_ECC_ERR_IOP_SHIFT)
    309  1.1  hikaru #define	  POW_ECC_ERR_IOP_PEND23		(UINT64_C(23) << POW_ECC_ERR_IOP_SHIFT)
    310  1.1  hikaru #define	  POW_ECC_ERR_IOP_PEND22		(UINT64_C(22) << POW_ECC_ERR_IOP_SHIFT)
    311  1.1  hikaru #define	  POW_ECC_ERR_IOP_PEND21		(UINT64_C(21) << POW_ECC_ERR_IOP_SHIFT)
    312  1.1  hikaru #define	  POW_ECC_ERR_IOP_TAGNULL		(UINT64_C(20) << POW_ECC_ERR_IOP_SHIFT)
    313  1.1  hikaru #define	  POW_ECC_ERR_IOP_TAGNULLNULL		(UINT64_C(19) << POW_ECC_ERR_IOP_SHIFT)
    314  1.1  hikaru #define	  POW_ECC_ERR_IOP_ORDATOM		(UINT64_C(18) << POW_ECC_ERR_IOP_SHIFT)
    315  1.1  hikaru #define	  POW_ECC_ERR_IOP_NULL			(UINT64_C(17) << POW_ECC_ERR_IOP_SHIFT)
    316  1.1  hikaru #define	  POW_ECC_ERR_IOP_NULLNULL		(UINT64_C(16) << POW_ECC_ERR_IOP_SHIFT)
    317  1.1  hikaru #define	POW_ECC_ERR_XXX_15_14			UINT64_C(0x000000000000c000)
    318  1.1  hikaru #define	POW_ECC_ERR_RPE_IE			UINT64_C(0x0000000000002000)
    319  1.1  hikaru #define	POW_ECC_ERR_RPE				UINT64_C(0x0000000000001000)
    320  1.1  hikaru #define	POW_ECC_ERR_XXX_11_9			UINT64_C(0x0000000000000e00)
    321  1.1  hikaru #define	POW_ECC_ERR_SYN				UINT64_C(0x00000000000001f0)
    322  1.1  hikaru #define	 POW_ECC_ERR_SYN_SHIFT			4
    323  1.1  hikaru #define	POW_ECC_ERR_DBE_IE			UINT64_C(0x0000000000000008)
    324  1.1  hikaru #define	POW_ECC_ERR_SBE_IE			UINT64_C(0x0000000000000004)
    325  1.1  hikaru #define	POW_ECC_ERR_DBE				UINT64_C(0x0000000000000002)
    326  1.1  hikaru #define	POW_ECC_ERR_SBE				UINT64_C(0x0000000000000001)
    327  1.1  hikaru 
    328  1.1  hikaru #define	POW_NOS_CNT_XXX_63_7			UINT64_C(0xffffffffffffff80)
    329  1.1  hikaru #define	POW_NOS_CNT_NOS_CNT			UINT64_C(0x000000000000007f)
    330  1.1  hikaru #define	 POW_NOS_CNT_NOS_CNT_SHIFT		0
    331  1.1  hikaru 
    332  1.1  hikaru #define	POW_WS_PC0_XXX_63_32			UINT64_C(0xffffffff00000000)
    333  1.1  hikaru #define	POW_WS_PC0_WS_PC			UINT64_C(0x00000000ffffffff)
    334  1.1  hikaru #define	 POW_WS_PC0_WS_PC_SHIFT			0
    335  1.1  hikaru 
    336  1.1  hikaru #define	POW_WA_PC0_XXX_63_32			UINT64_C(0xffffffff00000000)
    337  1.1  hikaru #define	POW_WA_PC0_WA_PC			UINT64_C(0x00000000ffffffff)
    338  1.1  hikaru #define	 POW_WA_PC0_WA_PC_SHIFT			0
    339  1.1  hikaru 
    340  1.1  hikaru #define	POW_IQ_CNT0_XXX_63_32			UINT64_C(0xffffffff00000000)
    341  1.1  hikaru #define	POW_IQ_CNT0_IQ_CNT			UINT64_C(0x00000000ffffffff)
    342  1.1  hikaru #define	 POW_IQ_CNT0_IQ_CNT_SHIFT		0
    343  1.1  hikaru 
    344  1.1  hikaru #define	POW_WA_COM_PC_XXX_63_32			UINT64_C(0xffffffff00000000)
    345  1.1  hikaru #define	POW_WA_COM_PC_WA_PC			UINT64_C(0x00000000ffffffff)
    346  1.1  hikaru #define	 POW_WA_COM_PC_WA_PC_SHIFT		0
    347  1.1  hikaru 
    348  1.1  hikaru #define	POW_WQ_COM_CNT_XXX_63_32		UINT64_C(0xffffffff00000000)
    349  1.1  hikaru #define	POW_WQ_COM_CNT_IQ_CNT			UINT64_C(0x00000000ffffffff)
    350  1.1  hikaru #define	 POW_WQ_COM_CNT_IQ_CNT_SHIFT		0
    351  1.1  hikaru 
    352  1.1  hikaru #define	POW_TS_PC_XXX_63_32			UINT64_C(0xffffffff00000000)
    353  1.1  hikaru #define	POW_TS_PC_TS_PC				UINT64_C(0x00000000ffffffff)
    354  1.1  hikaru #define	 POW_TS_PC_TS_PC_SHIFT			0
    355  1.1  hikaru 
    356  1.1  hikaru #define	POW_DS_PC_XXX_63_32			UINT64_C(0xffffffff00000000)
    357  1.1  hikaru #define	POW_DS_PC_DS_PC				UINT64_C(0x00000000ffffffff)
    358  1.1  hikaru #define	 POW_DS_PC_DS_PC_SHIFT			0
    359  1.1  hikaru 
    360  1.1  hikaru #define	POW_BIST_STAT_XXX_63_7			UINT64_C(0xfffffffffffe0000)
    361  1.1  hikaru #define	POW_BIST_STAT_PP			UINT64_C(0x0000000000010000)
    362  1.1  hikaru #define	POW_BIST_STAT_XXX_15_9			UINT64_C(0x000000000000fe00)
    363  1.1  hikaru #define	POW_BIST_STAT_CAM			UINT64_C(0x0000000000000100)
    364  1.1  hikaru #define	POW_BIST_STAT_NBT1			UINT64_C(0x0000000000000080)
    365  1.1  hikaru #define	POW_BIST_STAT_NBT0			UINT64_C(0x0000000000000040)
    366  1.1  hikaru #define	POW_BIST_STAT_IDX			UINT64_C(0x0000000000000020)
    367  1.1  hikaru #define	POW_BIST_STAT_FIDX			UINT64_C(0x0000000000000010)
    368  1.1  hikaru #define	POW_BIST_STAT_NBR1			UINT64_C(0x0000000000000008)
    369  1.1  hikaru #define	POW_BIST_STAT_NBR0			UINT64_C(0x0000000000000004)
    370  1.1  hikaru #define	POW_BIST_STAT_PEND			UINT64_C(0x0000000000000002)
    371  1.1  hikaru #define	POW_BIST_STAT_ADR			UINT64_C(0x0000000000000001)
    372  1.1  hikaru 
    373  1.1  hikaru /* ---- pow operations */
    374  1.1  hikaru 
    375  1.1  hikaru /* pow operations base */
    376  1.1  hikaru #define POW_OPERATION_BASE_IO_BIT		UINT64_C(0x0001000000000000)
    377  1.1  hikaru #define POW_OPERATION_BASE_MAJOR_DID		UINT64_C(0x0000f80000000000)
    378  1.1  hikaru #define POW_OPERATION_BASE_SUB_DID		UINT64_C(0x0000070000000000)
    379  1.1  hikaru #define	POW_OPERATION_BASE_IO_BIT_SHIFT	48
    380  1.1  hikaru #define	POW_OPERATION_BASE_MAJOR_DID_SHIFT	43
    381  1.1  hikaru #define	POW_OPERATION_BASE_SUB_DID_SHIFT	40
    382  1.1  hikaru 
    383  1.1  hikaru /* get work load  (subid = 0) */
    384  1.1  hikaru #define POW_GET_WORK_LOAD_WAIT			UINT64_C(0x0000000000000008)
    385  1.1  hikaru #define POW_GET_WORK_LOAD_2_0			UINT64_C(0x0000000000000007)
    386  1.1  hikaru #define	POW_GET_WORK_LOAD_WAIT_SHIFT	3
    387  1.1  hikaru #define	POW_GET_WORK_LOAD_2_0_SHIFT	0
    388  1.1  hikaru 
    389  1.1  hikaru #define POW_GET_WORK_LOAD_RESULT_NO_WORK	UINT64_C(0x8000000000000000)
    390  1.1  hikaru #define POW_GET_WORK_LOAD_RESULT_62_40		UINT64_C(0x7fffff0000000000)
    391  1.1  hikaru #define POW_GET_WORK_LOAD_RESULT_ADDR		UINT64_C(0x000000ffffffffff)
    392  1.1  hikaru 
    393  1.1  hikaru /* pow status load (subid = 1) */
    394  1.1  hikaru #define POW_STATUS_LOAD_COREID			UINT64_C(0x00000000000003c0)
    395  1.1  hikaru #define POW_STATUS_LOAD_GET_REV			UINT64_C(0x0000000000000020)
    396  1.1  hikaru #define POW_STATUS_LOAD_GET_CUR			UINT64_C(0x0000000000000010)
    397  1.1  hikaru #define POW_STATUS_LOAD_GET_WQP			UINT64_C(0x0000000000000008)
    398  1.1  hikaru #define POW_STATUS_LOAD_GET_2_0			UINT64_C(0x0000000000000007)
    399  1.1  hikaru #define	POW_STATUS_LOAD_GET_WQP_SHIFT	3
    400  1.1  hikaru #define	POW_STATUS_LOAD_GET_CUR_SHIFT	4
    401  1.1  hikaru #define	POW_STATUS_LOAD_COREID_SHIFT	6
    402  1.1  hikaru #define	POW_STATUS_LOAD_GET_2_0_SHIFT	0
    403  1.1  hikaru #define	POW_STATUS_LOAD_GET_REV_SHIFT	5
    404  1.1  hikaru 
    405  1.1  hikaru /* get_cur = 0 and get_wqp = 0 ("pend_tag") */
    406  1.1  hikaru #define POW_STATUS_LOAD_RESULT_PEND_TAG_XXX_63_62		UINT64_C(0xc000000000000000)
    407  1.1  hikaru #define POW_STATUS_LOAD_RESULT_PEND_TAG_PEND_SWITCH		UINT64_C(0x2000000000000000)
    408  1.1  hikaru #define POW_STATUS_LOAD_RESULT_PEND_TAG_PEND_SWITCH_FULL	UINT64_C(0x1000000000000000)
    409  1.1  hikaru #define POW_STATUS_LOAD_RESULT_PEND_TAG_PEND_SWITCH_NULL	UINT64_C(0x0800000000000000)
    410  1.1  hikaru #define POW_STATUS_LOAD_RESULT_PEND_TAG_PEND_DESCHED		UINT64_C(0x0400000000000000)
    411  1.1  hikaru #define POW_STATUS_LOAD_RESULT_PEND_TAG_PEND_DESCHED_SWITCH	UINT64_C(0x0200000000000000)
    412  1.1  hikaru #define POW_STATUS_LOAD_RESULT_PEND_TAG_PEND_NOSCHED		UINT64_C(0x0100000000000000)
    413  1.1  hikaru #define POW_STATUS_LOAD_RESULT_PEND_TAG_PEND_NEW_WORK		UINT64_C(0x0080000000000000)
    414  1.1  hikaru #define POW_STATUS_LOAD_RESULT_PEND_TAG_PEND_NEW_WORK_WAIT	UINT64_C(0x0040000000000000)
    415  1.1  hikaru #define POW_STATUS_LOAD_RESULT_PEND_TAG_PEND_NULL_RD		UINT64_C(0x0020000000000000)
    416  1.1  hikaru #define POW_STATUS_LOAD_RESULT_PEND_TAG_PEND_NOSCHED_CLR	UINT64_C(0x0010000000000000)
    417  1.1  hikaru #define POW_STATUS_LOAD_RESULT_PEND_TAG_PEND_XXX_51		UINT64_C(0x0008000000000000)
    418  1.1  hikaru #define POW_STATUS_LOAD_RESULT_PEND_TAG_PEND_INDEX		UINT64_C(0x0007ff0000000000)
    419  1.1  hikaru #define POW_STATUS_LOAD_RESULT_PEND_TAG_PEND_GRP		UINT64_C(0x000000f000000000)
    420  1.1  hikaru #define POW_STATUS_LOAD_RESULT_PEND_TAG_PEND_XXX_35_34		UINT64_C(0x0000000c00000000)
    421  1.1  hikaru #define POW_STATUS_LOAD_RESULT_PEND_TAG_PEND_TYPE		UINT64_C(0x0000000300000000)
    422  1.1  hikaru #define POW_STATUS_LOAD_RESULT_PEND_TAG_PEND_TAG		UINT64_C(0x00000000ffffffff)
    423  1.1  hikaru #define	POW_STATUS_LOAD_RESULT_PEND_TAG_BITS \
    424  1.1  hikaru 	"\177"		/* new format */ \
    425  1.1  hikaru 	"\020"		/* hex display */ \
    426  1.1  hikaru 	"\020"		/* %016x format */ \
    427  1.1  hikaru 	"b\x3d"		"PEND_SWITCH\0" \
    428  1.1  hikaru 	"b\x3c"		"PEND_SWITCH_FULL\0" \
    429  1.1  hikaru 	"b\x3b"		"PEND_SWITCH_NULL\0" \
    430  1.1  hikaru 	"b\x3a"		"PEND_DESCHED\0" \
    431  1.1  hikaru 	"b\x39"		"PEND_DESCHED_SWITCH\0" \
    432  1.1  hikaru 	"b\x38"		"PEND_NOSCHED\0" \
    433  1.1  hikaru 	"b\x37"		"PEND_NEW_WORK\0" \
    434  1.1  hikaru 	"b\x36"		"PEND_NEW_WORK_WAIT\0" \
    435  1.1  hikaru 	"b\x35"		"PEND_NULL_RD\0" \
    436  1.1  hikaru 	"b\x34"		"PEND_NOSCHED_CLR\0" \
    437  1.1  hikaru 	"f\x28\x0b"	"PEND_INDEX\0" \
    438  1.1  hikaru 	"f\x24\x04"	"PEND_GRP\0" \
    439  1.1  hikaru 	"f\x20\x02"	"PEND_TYPE\0" \
    440  1.1  hikaru 	"f\x00\x20"	"PEND_TAG\0"
    441  1.1  hikaru 
    442  1.1  hikaru /* get_cur = 0 and get_wqp = 1 ("pend_wqp") */
    443  1.1  hikaru #define POW_STATUS_LOAD_RESULT_PEND_WQP_XXX_63_62		UINT64_C(0xc000000000000000)
    444  1.1  hikaru #define POW_STATUS_LOAD_RESULT_PEND_WQP_PEND_SWITCH		UINT64_C(0x2000000000000000)
    445  1.1  hikaru #define POW_STATUS_LOAD_RESULT_PEND_WQP_PEND_SWITCH_FULL	UINT64_C(0x1000000000000000)
    446  1.1  hikaru #define POW_STATUS_LOAD_RESULT_PEND_WQP_PEND_SWITCH_NULL	UINT64_C(0x0800000000000000)
    447  1.1  hikaru #define POW_STATUS_LOAD_RESULT_PEND_WQP_PEND_DESCHED		UINT64_C(0x0400000000000000)
    448  1.1  hikaru #define POW_STATUS_LOAD_RESULT_PEND_WQP_PEND_DESCHED_SWITCH	UINT64_C(0x0200000000000000)
    449  1.1  hikaru #define POW_STATUS_LOAD_RESULT_PEND_WQP_PEND_NOSCHED		UINT64_C(0x0100000000000000)
    450  1.1  hikaru #define POW_STATUS_LOAD_RESULT_PEND_WQP_PEND_NEW_WORK		UINT64_C(0x0080000000000000)
    451  1.1  hikaru #define POW_STATUS_LOAD_RESULT_PEND_WQP_PEND_NEW_WORK_WAIT	UINT64_C(0x0040000000000000)
    452  1.1  hikaru #define POW_STATUS_LOAD_RESULT_PEND_WQP_PEND_NULL_RD		UINT64_C(0x0020000000000000)
    453  1.1  hikaru #define POW_STATUS_LOAD_RESULT_PEND_WQP_PEND_NOSCHED_CLR	UINT64_C(0x0010000000000000)
    454  1.1  hikaru #define POW_STATUS_LOAD_RESULT_PEND_WQP_PEND_XXX_51		UINT64_C(0x0008000000000000)
    455  1.1  hikaru #define POW_STATUS_LOAD_RESULT_PEND_WQP_PEND_INDEX		UINT64_C(0x0007ff0000000000)
    456  1.1  hikaru #define POW_STATUS_LOAD_RESULT_PEND_WQP_PEND_WQP		UINT64_C(0x0000000fffffffff)
    457  1.1  hikaru #define	POW_STATUS_LOAD_RESULT_PEND_WQP_BITS \
    458  1.1  hikaru 	"\177"		/* new format */ \
    459  1.1  hikaru 	"\020"		/* hex display */ \
    460  1.1  hikaru 	"\020"		/* %016x format */ \
    461  1.1  hikaru 	"b\x3d"		"PEND_SWITCH\0" \
    462  1.1  hikaru 	"b\x3c"		"PEND_SWITCH_FULL\0" \
    463  1.1  hikaru 	"b\x3b"		"PEND_SWITCH_NULL\0" \
    464  1.1  hikaru 	"b\x3a"		"PEND_DESCHED\0" \
    465  1.1  hikaru 	"b\x39"		"PEND_DESCHED_SWITCH\0" \
    466  1.1  hikaru 	"b\x38"		"PEND_NOSCHED\0" \
    467  1.1  hikaru 	"b\x37"		"PEND_NEW_WORK\0" \
    468  1.1  hikaru 	"b\x36"		"PEND_NEW_WORK_WAIT\0" \
    469  1.1  hikaru 	"b\x35"		"PEND_NULL_RD\0" \
    470  1.1  hikaru 	"b\x34"		"PEND_NOSCHED_CLR\0" \
    471  1.1  hikaru 	"f\x28\x0b"	"PEND_INDEX\0" \
    472  1.1  hikaru 	"f\x00\x24"	"PEND_WQP\0"
    473  1.1  hikaru 
    474  1.1  hikaru /* get_cur = 1 and get_wqp = 0 and get_rev = 0 ("cur_tag_next") */
    475  1.1  hikaru #define POW_STATUS_LOAD_RESULT_CUR_TAG_NEXT_XXX_63_62		UINT64_C(0xc000000000000000)
    476  1.1  hikaru #define POW_STATUS_LOAD_RESULT_CUR_TAG_NEXT_LINK_INDEX		UINT64_C(0x3ff8000000000000)
    477  1.1  hikaru #define POW_STATUS_LOAD_RESULT_CUR_TAG_NEXT_INDEX		UINT64_C(0x0007ff0000000000)
    478  1.1  hikaru #define POW_STATUS_LOAD_RESULT_CUR_TAG_NEXT_GRP			UINT64_C(0x000000f000000000)
    479  1.1  hikaru #define POW_STATUS_LOAD_RESULT_CUR_TAG_NEXT_HEAD		UINT64_C(0x0000000800000000)
    480  1.1  hikaru #define POW_STATUS_LOAD_RESULT_CUR_TAG_NEXT_TAIL		UINT64_C(0x0000000400000000)
    481  1.1  hikaru #define POW_STATUS_LOAD_RESULT_CUR_TAG_NEXT_TAG_TYPE		UINT64_C(0x0000000300000000)
    482  1.1  hikaru #define POW_STATUS_LOAD_RESULT_CUR_TAG_NEXT_TAG			UINT64_C(0x00000000ffffffff)
    483  1.1  hikaru #define	POW_STATUS_LOAD_RESULT_CUR_TAG_NEXT_BITS \
    484  1.1  hikaru 	"\177"		/* new format */ \
    485  1.1  hikaru 	"\020"		/* hex display */ \
    486  1.1  hikaru 	"\020"		/* %016x format */ \
    487  1.1  hikaru 	"f\x33\x0b"	"LINK_INDEX\0" \
    488  1.1  hikaru 	"f\x28\x0b"	"INDEX\0" \
    489  1.1  hikaru 	"f\x24\x04"	"GRP\0" \
    490  1.1  hikaru 	"b\x23"		"HEAD\0" \
    491  1.1  hikaru 	"b\x22"		"TAIL\0" \
    492  1.1  hikaru 	"f\x20\x02"	"TAG_TYPE\0" \
    493  1.1  hikaru 	"f\x00\x20"	"TAG\0"
    494  1.1  hikaru 
    495  1.1  hikaru /* get_cur = 1 and get_wqp = 0 and get_rev = 1 ("cur_tag_prev") */
    496  1.1  hikaru #define POW_STATUS_LOAD_RESULT_CUR_TAG_PREV_XXX_63_62		UINT64_C(0xc000000000000000)
    497  1.1  hikaru #define POW_STATUS_LOAD_RESULT_CUR_TAG_PREV_REVLINK_INDEX	UINT64_C(0x3ff8000000000000)
    498  1.1  hikaru #define POW_STATUS_LOAD_RESULT_CUR_TAG_PREV_INDEX		UINT64_C(0x0007ff0000000000)
    499  1.1  hikaru #define POW_STATUS_LOAD_RESULT_CUR_TAG_PREV_GRP			UINT64_C(0x000000f000000000)
    500  1.1  hikaru #define POW_STATUS_LOAD_RESULT_CUR_TAG_PREV_HEAD		UINT64_C(0x0000000800000000)
    501  1.1  hikaru #define POW_STATUS_LOAD_RESULT_CUR_TAG_PREV_TAIL		UINT64_C(0x0000000400000000)
    502  1.1  hikaru #define POW_STATUS_LOAD_RESULT_CUR_TAG_PREV_TAG_TYPE		UINT64_C(0x0000000300000000)
    503  1.1  hikaru #define POW_STATUS_LOAD_RESULT_CUR_TAG_PREV_TAG			UINT64_C(0x00000000ffffffff)
    504  1.1  hikaru #define	POW_STATUS_LOAD_RESULT_CUR_TAG_PREV_BITS \
    505  1.1  hikaru 	"\177"		/* new format */ \
    506  1.1  hikaru 	"\020"		/* hex display */ \
    507  1.1  hikaru 	"\020"		/* %016x format */ \
    508  1.1  hikaru 	"f\x33\x0b"	"REVLINK_INDEX\0" \
    509  1.1  hikaru 	"f\x28\x0b"	"INDEX\0" \
    510  1.1  hikaru 	"f\x24\x04"	"GRP\0" \
    511  1.1  hikaru 	"b\x23"		"HEAD\0" \
    512  1.1  hikaru 	"b\x22"		"TAIL\0" \
    513  1.1  hikaru 	"f\x20\x02"	"TAG_TYPE\0" \
    514  1.1  hikaru 	"f\x00\x20"	"TAG\0"
    515  1.1  hikaru 
    516  1.1  hikaru /* get_cur = 1 and get_wqp = 1 and get_rev = 0 ("cur_wqp_next") */
    517  1.1  hikaru #define POW_STATUS_LOAD_RESULT_CUR_WQP_NEXT_XXX_63_62		UINT64_C(0xc000000000000000)
    518  1.1  hikaru #define POW_STATUS_LOAD_RESULT_CUR_WQP_NEXT_LINK_INDEX		UINT64_C(0x3ff8000000000000)
    519  1.1  hikaru #define POW_STATUS_LOAD_RESULT_CUR_WQP_NEXT_INDEX		UINT64_C(0x0007ff0000000000)
    520  1.1  hikaru #define POW_STATUS_LOAD_RESULT_CUR_WQP_NEXT_GRP			UINT64_C(0x000000f000000000)
    521  1.1  hikaru #define POW_STATUS_LOAD_RESULT_CUR_WQP_NEXT_WQP			UINT64_C(0x0000000fffffffff)
    522  1.1  hikaru #define	POW_STATUS_LOAD_RESULT_CUR_WQP_NEXT_BITS \
    523  1.1  hikaru 	"\177"		/* new format */ \
    524  1.1  hikaru 	"\020"		/* hex display */ \
    525  1.1  hikaru 	"\020"		/* %016x format */ \
    526  1.1  hikaru 	"f\x33\x0b"	"LINK_INDEX\0" \
    527  1.1  hikaru 	"f\x28\x0b"	"INDEX\0" \
    528  1.1  hikaru 	"f\x24\x04"	"GRP\0" \
    529  1.1  hikaru 	"f\x00\x24"	"WQP\0"
    530  1.1  hikaru 
    531  1.1  hikaru /* get_cur = 1 and get_wqp = 1 and get_rev = 1 ("cur_wqp_prev") */
    532  1.1  hikaru #define POW_STATUS_LOAD_RESULT_CUR_WQP_PREV_XXX_63_62		UINT64_C(0xc000000000000000)
    533  1.1  hikaru #define POW_STATUS_LOAD_RESULT_CUR_WQP_PREV_REVLINK_INDEX	UINT64_C(0x3ff8000000000000)
    534  1.1  hikaru #define POW_STATUS_LOAD_RESULT_CUR_WQP_PREV_INDEX		UINT64_C(0x0007ff0000000000)
    535  1.1  hikaru #define POW_STATUS_LOAD_RESULT_CUR_WQP_PREV_GRP			UINT64_C(0x000000f000000000)
    536  1.1  hikaru #define POW_STATUS_LOAD_RESULT_CUR_WQP_PREV_WQP			UINT64_C(0x0000000fffffffff)
    537  1.1  hikaru #define	POW_STATUS_LOAD_RESULT_CUR_WQP_PREV_BITS \
    538  1.1  hikaru 	"\177"		/* new format */ \
    539  1.1  hikaru 	"\020"		/* hex display */ \
    540  1.1  hikaru 	"\020"		/* %016x format */ \
    541  1.1  hikaru 	"f\x33\x0b"	"REVLINK_INDEX\0" \
    542  1.1  hikaru 	"f\x28\x0b"	"INDEX\0" \
    543  1.1  hikaru 	"f\x24\x04"	"GRP\0" \
    544  1.1  hikaru 	"f\x00\x24"	"WQP\0"
    545  1.1  hikaru 
    546  1.1  hikaru /* pow memory load (subid = 2) */
    547  1.1  hikaru #define POW_MEMORY_LOAD_INDEX		UINT64_C(0x000000000000ffe0)
    548  1.1  hikaru #define POW_MEMORY_LOAD_GET_DES		UINT64_C(0x0000000000000010)
    549  1.1  hikaru #define POW_MEMORY_LOAD_GET_WQP		UINT64_C(0x0000000000000008)
    550  1.1  hikaru #define POW_MEMORY_LOAD_2_0		UINT64_C(0x0000000000000007)
    551  1.1  hikaru #define	POW_MEMORY_LOAD_2_0_SHIFT	0
    552  1.1  hikaru #define	POW_MEMORY_LOAD_GET_WQP_SHIFT	3
    553  1.1  hikaru #define	POW_MEMORY_LOAD_INDEX_SHIFT	5
    554  1.1  hikaru #define	POW_MEMORY_LOAD_GET_DES_SHIFT	4
    555  1.1  hikaru 
    556  1.1  hikaru /* get_des = 0 and get_wqp = 0 ("tag") */
    557  1.1  hikaru #define POW_MEMORY_LOAD_RESULT_TAG_XXX_63_51			UINT64_C(0xfff8000000000000)
    558  1.1  hikaru #define POW_MEMORY_LOAD_RESULT_TAG_NEXT_INDEX			UINT64_C(0x0007ff0000000000)
    559  1.1  hikaru #define POW_MEMORY_LOAD_RESULT_TAG_GRP				UINT64_C(0x000000f000000000)
    560  1.1  hikaru #define POW_MEMORY_LOAD_RESULT_TAG_XXX_35			UINT64_C(0x0000000800000000)
    561  1.1  hikaru #define POW_MEMORY_LOAD_RESULT_TAG_TAIL				UINT64_C(0x0000000400000000)
    562  1.1  hikaru #define POW_MEMORY_LOAD_RESULT_TAG_TAG_TYPE			UINT64_C(0x0000000300000000)
    563  1.1  hikaru #define POW_MEMORY_LOAD_RESULT_TAG_TAG				UINT64_C(0x00000000ffffffff)
    564  1.1  hikaru #define	POW_MEMORY_LOAD_RESULT_TAG_BITS \
    565  1.1  hikaru 	"\177"		/* new format */ \
    566  1.1  hikaru 	"\020"		/* hex display */ \
    567  1.1  hikaru 	"\020"		/* %016x format */ \
    568  1.1  hikaru 	"f\x28\x0b"	"NEXT_INDEX\0" \
    569  1.1  hikaru 	"f\x24\x04"	"GRP\0" \
    570  1.1  hikaru 	"b\x22"		"TAIL\0" \
    571  1.1  hikaru 	"f\x20\x02"	"TAG_TYPE\0" \
    572  1.1  hikaru 	"f\x00\x20"	"TAG\0"
    573  1.1  hikaru 
    574  1.1  hikaru /* get_des = 0 and get_wqp = 1 ("wqp") */
    575  1.1  hikaru #define POW_MEMORY_LOAD_RESULT_WQP_XXX_63_51			UINT64_C(0xfff8000000000000)
    576  1.1  hikaru #define POW_MEMORY_LOAD_RESULT_WQP_NEXT_INDEX			UINT64_C(0x0007ff0000000000)
    577  1.1  hikaru #define POW_MEMORY_LOAD_RESULT_WQP_GRP				UINT64_C(0x000000f000000000)
    578  1.1  hikaru #define POW_MEMORY_LOAD_RESULT_WQP_WQP				UINT64_C(0x0000000fffffffff)
    579  1.1  hikaru #define	POW_MEMORY_LOAD_RESULT_WQP_BITS \
    580  1.1  hikaru 	"\177"		/* new format */ \
    581  1.1  hikaru 	"\020"		/* hex display */ \
    582  1.1  hikaru 	"\020"		/* %016x format */ \
    583  1.1  hikaru 	"f\x28\x0b"	"NEXT_INDEX\0" \
    584  1.1  hikaru 	"f\x24\x04"	"GRP\0" \
    585  1.1  hikaru 	"f\x00\x24"	"WQP\0"
    586  1.1  hikaru 
    587  1.1  hikaru /* get_des = 1 ("desched") */
    588  1.1  hikaru #define POW_MEMORY_LOAD_RESULT_DESCHED_XXX_63_51		UINT64_C(0xfff8000000000000)
    589  1.1  hikaru #define POW_MEMORY_LOAD_RESULT_DESCHED_FWD_INDEX		UINT64_C(0x0007ff0000000000)
    590  1.1  hikaru #define POW_MEMORY_LOAD_RESULT_DESCHED_GRP			UINT64_C(0x000000f000000000)
    591  1.1  hikaru #define POW_MEMORY_LOAD_RESULT_DESCHED_NOSCHED			UINT64_C(0x0000000800000000)
    592  1.1  hikaru #define POW_MEMORY_LOAD_RESULT_DESCHED_PEND_SWITCH		UINT64_C(0x0000000400000000)
    593  1.1  hikaru #define POW_MEMORY_LOAD_RESULT_DESCHED_PEND_TYPE		UINT64_C(0x0000000300000000)
    594  1.1  hikaru #define POW_MEMORY_LOAD_RESULT_DESCHED_PEND_TAG			UINT64_C(0x00000000ffffffff)
    595  1.1  hikaru #define	POW_MEMORY_LOAD_RESULT_DESCHED_BITS \
    596  1.1  hikaru 	"\177"		/* new format */ \
    597  1.1  hikaru 	"\020"		/* hex display */ \
    598  1.1  hikaru 	"\020"		/* %016x format */ \
    599  1.1  hikaru 	"f\x28\x0b"	"FWD_INDEX\0" \
    600  1.1  hikaru 	"f\x24\x04"	"GRP\0" \
    601  1.1  hikaru 	"b\x23"		"NOSCHED\0" \
    602  1.1  hikaru 	"b\x22"		"PEND_SWITCH\0" \
    603  1.1  hikaru 	"f\x20\x02"	"PEND_TYPE\0" \
    604  1.1  hikaru 	"f\x00\x20"	"PEND_TAG\0"
    605  1.1  hikaru 
    606  1.1  hikaru /* pow index/pointer load (subid = 3) */
    607  1.1  hikaru #define POW_IDXPTR_LOAD_QOSGRP			UINT64_C(0x00000000000001e0)
    608  1.1  hikaru #define POW_IDXPTR_LOAD_GET_DES_GET_TAIL	UINT64_C(0x0000000000000010)
    609  1.1  hikaru #define POW_IDXPTR_LOAD_GET_RMT			UINT64_C(0x0000000000000008)
    610  1.1  hikaru #define POW_IDXPTR_LOAD_2_0			UINT64_C(0x0000000000000007)
    611  1.1  hikaru #define	POW_IDXPTR_LOAD_QOSGRP_SHIFT	5
    612  1.1  hikaru #define	POW_IDXPTR_LOAD_GET_DES_GET_TAIL_SHIFT	4
    613  1.1  hikaru #define	POW_IDXPTR_LOAD_2_0_SHIFT	0
    614  1.1  hikaru #define	POW_IDXPTR_LOAD_GET_RMT_SHIFT	3
    615  1.1  hikaru 
    616  1.1  hikaru /* get_rmt = 0 and get_des_get_tail = 0 ("qos") */
    617  1.1  hikaru #define POW_IDXPTR_LOAD_RESULT_QOS_FREE_LOC_XXX_63_52		UINT64_C(0xfff0000000000000)
    618  1.1  hikaru #define POW_IDXPTR_LOAD_RESULT_QOS_FREE_LOC_FREE_VAL		UINT64_C(0x0008000000000000)
    619  1.1  hikaru #define POW_IDXPTR_LOAD_RESULT_QOS_FREE_LOC_FREE_ONE		UINT64_C(0x0004000000000000)
    620  1.1  hikaru #define POW_IDXPTR_LOAD_RESULT_QOS_FREE_LOC_XXX_49		UINT64_C(0x0002000000000000)
    621  1.1  hikaru #define POW_IDXPTR_LOAD_RESULT_QOS_FREE_LOC_FREE_HEAD		UINT64_C(0x0001ffc000000000)
    622  1.1  hikaru #define POW_IDXPTR_LOAD_RESULT_QOS_FREE_LOC_XXX_37		UINT64_C(0x0000002000000000)
    623  1.1  hikaru #define POW_IDXPTR_LOAD_RESULT_QOS_FREE_LOC_FREE_TAIL		UINT64_C(0x0000001ffc000000)
    624  1.1  hikaru #define POW_IDXPTR_LOAD_RESULT_QOS_FREE_LOC_LOC_VAL		UINT64_C(0x0000000002000000)
    625  1.1  hikaru #define POW_IDXPTR_LOAD_RESULT_QOS_FREE_LOC_LOC_ONE		UINT64_C(0x0000000001000000)
    626  1.1  hikaru #define POW_IDXPTR_LOAD_RESULT_QOS_FREE_LOC_XXX_23		UINT64_C(0x0000000000800000)
    627  1.1  hikaru #define POW_IDXPTR_LOAD_RESULT_QOS_FREE_LOC_LOC_HEAD		UINT64_C(0x00000000007ff000)
    628  1.1  hikaru #define POW_IDXPTR_LOAD_RESULT_QOS_FREE_LOC_XXX_11		UINT64_C(0x0000000000000800)
    629  1.1  hikaru #define POW_IDXPTR_LOAD_RESULT_QOS_FREE_LOC_LOC_TAIL		UINT64_C(0x00000000000007ff)
    630  1.1  hikaru #define	POW_IDXPTR_LOAD_RESULT_QOS_FREE_LOC_BITS \
    631  1.1  hikaru 	"\177"		/* new format */ \
    632  1.1  hikaru 	"\020"		/* hex display */ \
    633  1.1  hikaru 	"\020"		/* %016x format */ \
    634  1.1  hikaru 	"b\x33"		"FREE_VAL\0" \
    635  1.1  hikaru 	"b\x32"		"FREE_ONE\0" \
    636  1.1  hikaru 	"f\x26\x0b"	"FREE_HEAD\0" \
    637  1.1  hikaru 	"f\x1a\x0b"	"FREE_TAIL\0" \
    638  1.1  hikaru 	"b\x19"		"LOC_VAL\0" \
    639  1.1  hikaru 	"b\x18"		"LOC_ONE\0" \
    640  1.1  hikaru 	"f\x0c\x0b"	"LOC_HEAD\0" \
    641  1.1  hikaru 	"f\x00\x0b"	"LOC_TAIL\0"
    642  1.1  hikaru 
    643  1.1  hikaru /* get_rmt = 0 and get_des_get_tail = 1 ("desched") */
    644  1.1  hikaru #define POW_IDXPTR_LOAD_RESULT_GRP_NOSCHED_DES_XXX_63_52	UINT64_C(0xfff0000000000000)
    645  1.1  hikaru #define POW_IDXPTR_LOAD_RESULT_GRP_NOSCHED_DES_NOSCHED_VAL	UINT64_C(0x0008000000000000)
    646  1.1  hikaru #define POW_IDXPTR_LOAD_RESULT_GRP_NOSCHED_DES_NOSCHED_ONE	UINT64_C(0x0004000000000000)
    647  1.1  hikaru #define POW_IDXPTR_LOAD_RESULT_GRP_NOSCHED_DES_XXX_49		UINT64_C(0x0002000000000000)
    648  1.1  hikaru #define POW_IDXPTR_LOAD_RESULT_GRP_NOSCHED_DES_NOSCHED_HEAD	UINT64_C(0x0001ffc000000000)
    649  1.1  hikaru #define POW_IDXPTR_LOAD_RESULT_GRP_NOSCHED_DES_XXX_37		UINT64_C(0x0000002000000000)
    650  1.1  hikaru #define POW_IDXPTR_LOAD_RESULT_GRP_NOSCHED_DES_NOSCHED_TAIL	UINT64_C(0x0000001ffc000000)
    651  1.1  hikaru #define POW_IDXPTR_LOAD_RESULT_GRP_NOSCHED_DES_DES_VAL		UINT64_C(0x0000000002000000)
    652  1.1  hikaru #define POW_IDXPTR_LOAD_RESULT_GRP_NOSCHED_DES_DES_ONE		UINT64_C(0x0000000001000000)
    653  1.1  hikaru #define POW_IDXPTR_LOAD_RESULT_GRP_NOSCHED_DES_XXX_23		UINT64_C(0x0000000000800000)
    654  1.1  hikaru #define POW_IDXPTR_LOAD_RESULT_GRP_NOSCHED_DES_DES_HEAD		UINT64_C(0x00000000007ff000)
    655  1.1  hikaru #define POW_IDXPTR_LOAD_RESULT_GRP_NOSCHED_DES_XXX_11		UINT64_C(0x0000000000000800)
    656  1.1  hikaru #define POW_IDXPTR_LOAD_RESULT_GRP_NOSCHED_DES_DES_TAIL		UINT64_C(0x00000000000007ff)
    657  1.1  hikaru #define	POW_IDXPTR_LOAD_RESULT_GRP_NOSCHED_DES_BITS \
    658  1.1  hikaru 	"\177"		/* new format */ \
    659  1.1  hikaru 	"\020"		/* hex display */ \
    660  1.1  hikaru 	"\020"		/* %016x format */ \
    661  1.1  hikaru 	"b\x33"		"NOSCHED_VAL\0" \
    662  1.1  hikaru 	"b\x32"		"NOSCHED_ONE\0" \
    663  1.1  hikaru 	"f\x26\x0b"	"NOSCHED_HEAD\0" \
    664  1.1  hikaru 	"f\x1a\x0b"	"NOSCHED_TAIL\0" \
    665  1.1  hikaru 	"b\x19"		"DES_VAL\0" \
    666  1.1  hikaru 	"b\x18"		"DES_ONE\0" \
    667  1.1  hikaru 	"f\x0c\x0b"	"DES_HEAD\0" \
    668  1.1  hikaru 	"f\x00\x0b"	"DES_TAIL\0"
    669  1.1  hikaru 
    670  1.1  hikaru /* get_rmt = 1 and get_des_get_tail = 0 ("remote_head") */
    671  1.1  hikaru #define POW_IDXPTR_LOAD_RESULT_QUEUE_REMOTE_HEAD_XXX_63_39	UINT64_C(0xffffff8000000000)
    672  1.1  hikaru #define POW_IDXPTR_LOAD_RESULT_QUEUE_REMOTE_HEAD_RMT_IS_HEAD	UINT64_C(0x0000004000000000)
    673  1.1  hikaru #define POW_IDXPTR_LOAD_RESULT_QUEUE_REMOTE_HEAD_RMT_VAL	UINT64_C(0x0000002000000000)
    674  1.1  hikaru #define POW_IDXPTR_LOAD_RESULT_QUEUE_REMOTE_HEAD_RMT_ONE	UINT64_C(0x0000001000000000)
    675  1.1  hikaru #define POW_IDXPTR_LOAD_RESULT_QUEUE_REMOTE_HEAD_RMT_HEAD	UINT64_C(0x0000000fffffffff)
    676  1.1  hikaru #define	POW_IDXPTR_LOAD_RESULT_QUEUE_REMOTE_HEAD_BITS \
    677  1.1  hikaru 	"\177"		/* new format */ \
    678  1.1  hikaru 	"\020"		/* hex display */ \
    679  1.1  hikaru 	"\020"		/* %016x format */ \
    680  1.1  hikaru 	"b\x26"		"RMT_IS_HEAD\0" \
    681  1.1  hikaru 	"b\x25"		"RMT_VAL\0" \
    682  1.1  hikaru 	"b\x24"		"RMT_ONE\0" \
    683  1.1  hikaru 	"f\x00\x24"	"RMT_HEAD\0"
    684  1.1  hikaru 
    685  1.1  hikaru /* get_rmt = 1 and get_des_get_tail = 1 ("remote_tail") */
    686  1.1  hikaru #define POW_IDXPTR_LOAD_RESULT_QUEUE_REMOTE_TAIL_XXX_63_39	UINT64_C(0xffffff8000000000)
    687  1.1  hikaru #define POW_IDXPTR_LOAD_RESULT_QUEUE_REMOTE_TAIL_RMT_IS_HEAD	UINT64_C(0x0000004000000000)
    688  1.1  hikaru #define POW_IDXPTR_LOAD_RESULT_QUEUE_REMOTE_TAIL_RMT_VAL	UINT64_C(0x0000002000000000)
    689  1.1  hikaru #define POW_IDXPTR_LOAD_RESULT_QUEUE_REMOTE_TAIL_RMT_ONE	UINT64_C(0x0000001000000000)
    690  1.1  hikaru #define POW_IDXPTR_LOAD_RESULT_QUEUE_REMOTE_TAIL_RMT_TAIL	UINT64_C(0x0000000fffffffff)
    691  1.1  hikaru #define	POW_IDXPTR_LOAD_RESULT_QUEUE_REMOTE_TAIL_BITS \
    692  1.1  hikaru 	"\177"		/* new format */ \
    693  1.1  hikaru 	"\020"		/* hex display */ \
    694  1.1  hikaru 	"\020"		/* %016x format */ \
    695  1.1  hikaru 	"b\x26"		"RMT_IS_HEAD\0" \
    696  1.1  hikaru 	"b\x25"		"RMT_VAL\0" \
    697  1.1  hikaru 	"b\x24"		"RMT_ONE\0" \
    698  1.1  hikaru 	"f\x00\x24"	"RMT_TAIL\0"
    699  1.1  hikaru 
    700  1.1  hikaru /* pow index/pointer load (subid = 2) */
    701  1.1  hikaru #define POW_NULL_RD_LOAD_39_3			UINT64_C(0x000000fffffffff8)
    702  1.1  hikaru #define POW_NULL_RD_LOAD_2_0			UINT64_C(0x0000000000000007)
    703  1.1  hikaru #define	POW_NULL_RD_LOAD_39_3_SHIFT	3
    704  1.1  hikaru #define	POW_NULL_RD_LOAD_2_0_SHIFT	0
    705  1.1  hikaru 
    706  1.1  hikaru #define POW_NULL_RD_LOAD_RESULT_63_2		UINT64_C(0xfffffffffffffffc)
    707  1.1  hikaru #define POW_NULL_RD_LOAD_RESULT_STATUS		UINT64_C(0x0000000000000003)
    708  1.1  hikaru 
    709  1.1  hikaru /* pow store operations */
    710  1.1  hikaru 
    711  1.1  hikaru #define POW_PHY_ADDR_STORE_ADDR			UINT64_C(0x0000000fffffffff)
    712  1.1  hikaru #define	POW_PHY_ADDR_STORE_ADDR_SHIFT	0
    713  1.1  hikaru 
    714  1.1  hikaru #define POW_STORE_DATA_NO_SCHED			UINT64_C(0x8000000000000000)
    715  1.1  hikaru #define POW_STORE_DATA_62_61			UINT64_C(0x6000000000000000)
    716  1.1  hikaru #define POW_STORE_DATA_INDEX			UINT64_C(0x1fff000000000000)
    717  1.1  hikaru #define POW_STORE_DATA_OP			UINT64_C(0x0000f00000000000)
    718  1.1  hikaru #define POW_STORE_DATA_43_42			UINT64_C(0x00000c0000000000)
    719  1.1  hikaru #define POW_STORE_DATA_QOS			UINT64_C(0x0000038000000000)
    720  1.1  hikaru #define POW_STORE_DATA_GRP			UINT64_C(0x0000007800000000)
    721  1.1  hikaru #define POW_STORE_DATA_TYPE			UINT64_C(0x0000000700000000)
    722  1.1  hikaru #define POW_STORE_DATA_TAG			UINT64_C(0x00000000ffffffff)
    723  1.1  hikaru #define	POW_STORE_DATA_INDEX_SHIFT	48
    724  1.1  hikaru #define	POW_STORE_DATA_OP_SHIFT	44
    725  1.1  hikaru #define	POW_STORE_DATA_NO_SCHED_SHIFT	63
    726  1.1  hikaru #define	POW_STORE_DATA_62_61_SHIFT	61
    727  1.1  hikaru #define	POW_STORE_DATA_43_42_SHIFT	42
    728  1.1  hikaru #define	POW_STORE_DATA_QOS_SHIFT	39
    729  1.1  hikaru #define	POW_STORE_DATA_GRP_SHIFT	35
    730  1.1  hikaru #define	POW_STORE_DATA_TYPE_SHIFT	32
    731  1.1  hikaru #define	POW_STORE_DATA_TAG_SHIFT	0
    732  1.1  hikaru 
    733  1.1  hikaru /* pow iobdma operations */
    734  1.1  hikaru 
    735  1.1  hikaru /* pow iobdma operations base*/
    736  1.1  hikaru #define POW_IOBDMA_BASE_SCRADDR			UINT64_C(0xff00000000000000)
    737  1.1  hikaru #define POW_IOBDMA_BASE_LEN			UINT64_C(0x00ff000000000000)
    738  1.1  hikaru #define POW_IOBDMA_BASE_MAJOR_DID		UINT64_C(0x0000f80000000000)
    739  1.1  hikaru #define POW_IOBDMA_BASE_SUB_DID			UINT64_C(0x0000070000000000)
    740  1.1  hikaru #define POW_IOBDMA_BASE_39_0			UINT64_C(0x000000ffffffffff)
    741  1.1  hikaru #define	POW_IOBDMA_BASE_MAJOR_DID_SHIFT	43
    742  1.1  hikaru #define	POW_IOBDMA_BASE_LEN_SHIFT	48
    743  1.1  hikaru #define	POW_IOBDMA_BASE_39_0_SHIFT	0
    744  1.1  hikaru #define	POW_IOBDMA_BASE_SCRADDR_SHIFT	56
    745  1.1  hikaru #define	POW_IOBDMA_BASE_SUB_DID_SHIFT	40
    746  1.1  hikaru 
    747  1.1  hikaru /* pow iobdma get work (subid = 0) */
    748  1.1  hikaru #define POW_IOBDMA_GET_WORK_39_4		UINT64_C(0x000000ffffffffff)
    749  1.1  hikaru #define POW_IOBDMA_GET_WORK_WAIT		UINT64_C(0x0000000000000008)
    750  1.1  hikaru #define POW_IOBDMA_GET_WORK_2_0			UINT64_C(0x0000000000000007)
    751  1.1  hikaru #define	POW_IOBDMA_GET_WORK_WAIT_SHIFT	3
    752  1.1  hikaru #define	POW_IOBDMA_GET_WORK_39_4_SHIFT	0
    753  1.1  hikaru #define	POW_IOBDMA_GET_WORK_2_0_SHIFT	0
    754  1.1  hikaru 
    755  1.1  hikaru #define POW_IOBDMA_GET_WORK_RESULT_NO_WORK	UINT64_C(0x8000000000000000)
    756  1.1  hikaru #define POW_IOBDMA_GET_WORK_RESULT_62_40	UINT64_C(0x7fffff0000000000)
    757  1.1  hikaru #define POW_IOBDMA_GET_WORK_RESULT_ADDR		UINT64_C(0x000000ffffffffff)
    758  1.1  hikaru 
    759  1.1  hikaru /* pow iobdma null rd (subid = 4) */
    760  1.1  hikaru #define POW_IOBDMA_NULL_RD_39_0			UINT64_C(0x000000ffffffffff)
    761  1.1  hikaru #define	POW_IOBDMA_NULL_RD_39_0_SHIFT	0
    762  1.1  hikaru 
    763  1.1  hikaru #define POW_IOBDMA_NULL_RD_RESULT_63_2		UINT64_C(0xfffffffffffffffc)
    764  1.1  hikaru #define POW_IOBDMA_NULL_RD_RESULT_STATUS	UINT64_C(0x0000000000000003)
    765  1.1  hikaru 
    766  1.1  hikaru /* ------------------------------------------------------------------------- */
    767  1.1  hikaru 
    768  1.1  hikaru /* Work Queue Entry */
    769  1.1  hikaru 
    770  1.1  hikaru #define	POW_WQE_WORD0_XXX_63_40			UINT64_C(0xffffff0000000000)
    771  1.1  hikaru #define	POW_WQE_WORD0_NEXT			UINT64_C(0x000000ffffffffff)
    772  1.1  hikaru #define	POW_WQE_WORD0_BITS \
    773  1.1  hikaru 	"\177"		/* new format */ \
    774  1.1  hikaru 	"\020"		/* hex display */ \
    775  1.1  hikaru 	"\020"		/* %016x format */ \
    776  1.1  hikaru 	"f\x00\x28"	"NEXT\0"
    777  1.1  hikaru #define	POW_WQE_WORD0_NEXT_SHIFT	0
    778  1.1  hikaru 
    779  1.1  hikaru #define	POW_WQE_WORD1_XXX_63_42			UINT64_C(0xfffffc0000000000)
    780  1.1  hikaru #define	POW_WQE_WORD1_QOS			UINT64_C(0x0000038000000000)
    781  1.1  hikaru #define	POW_WQE_WORD1_GRP			UINT64_C(0x0000007800000000)
    782  1.1  hikaru #define	POW_WQE_WORD1_TT			UINT64_C(0x0000000700000000)
    783  1.1  hikaru #define	POW_WQE_WORD1_TAG			UINT64_C(0x00000000ffffffff)
    784  1.1  hikaru #define	POW_WQE_WORD1_BITS \
    785  1.1  hikaru 	"\177"		/* new format */ \
    786  1.1  hikaru 	"\020"		/* hex display */ \
    787  1.1  hikaru 	"\020"		/* %016x format */ \
    788  1.1  hikaru 	"f\x27\x03"	"QOS\0" \
    789  1.1  hikaru 	"f\x23\x04"	"GRP\0" \
    790  1.1  hikaru 	"f\x20\x03"	"TT\0" \
    791  1.1  hikaru 	"f\x00\x20"	"TAG\0"
    792  1.1  hikaru #define	POW_WQE_WORD1_TT_SHIFT	32
    793  1.1  hikaru #define	POW_WQE_WORD1_QOS_SHIFT	39
    794  1.1  hikaru #define	POW_WQE_WORD1_GRP_SHIFT	35
    795  1.1  hikaru #define	POW_WQE_WORD1_TAG_SHIFT	0
    796  1.1  hikaru 
    797  1.1  hikaru /* ------------------------------------------------------------------------- */
    798  1.1  hikaru 
    799  1.1  hikaru /* for snprintb(9) */
    800  1.1  hikaru 
    801  1.1  hikaru #define	POW_PP_GRP_MSKX_BITS \
    802  1.1  hikaru 	"\177"		/* new format */ \
    803  1.1  hikaru 	"\020"		/* hex display */ \
    804  1.1  hikaru 	"\020"		/* %016x format */ \
    805  1.1  hikaru 	"f\x00\x10"	"GRP_MSK\0"
    806  1.1  hikaru #define	POW_PP_GRP_MSK0_BITS	POW_PP_GRP_MSKX_BITS
    807  1.1  hikaru #define	POW_PP_GRP_MSK1_BITS	POW_PP_GRP_MSKX_BITS
    808  1.1  hikaru #define	POW_WQ_INT_THRX_BITS \
    809  1.1  hikaru 	"\177"		/* new format */ \
    810  1.1  hikaru 	"\020"		/* hex display */ \
    811  1.1  hikaru 	"\020"		/* %016x format */ \
    812  1.1  hikaru 	"b\x1c"		"TC_EN\0" \
    813  1.1  hikaru 	"f\x18\x04"	"TC_THR\0" \
    814  1.1  hikaru 	"f\x0c\x06"	"DS_THR\0" \
    815  1.1  hikaru 	"f\x00\x06"	"IQ_THR\0"
    816  1.1  hikaru #define	POW_WQ_INT_THR0_BITS	POW_WQ_INT_THRX_BITS
    817  1.1  hikaru #define	POW_WQ_INT_THR1_BITS	POW_WQ_INT_THRX_BITS
    818  1.1  hikaru #define	POW_WQ_INT_THR2_BITS	POW_WQ_INT_THRX_BITS
    819  1.1  hikaru #define	POW_WQ_INT_THR3_BITS	POW_WQ_INT_THRX_BITS
    820  1.1  hikaru #define	POW_WQ_INT_THR4_BITS	POW_WQ_INT_THRX_BITS
    821  1.1  hikaru #define	POW_WQ_INT_THR5_BITS	POW_WQ_INT_THRX_BITS
    822  1.1  hikaru #define	POW_WQ_INT_THR6_BITS	POW_WQ_INT_THRX_BITS
    823  1.1  hikaru #define	POW_WQ_INT_THR7_BITS	POW_WQ_INT_THRX_BITS
    824  1.1  hikaru #define	POW_WQ_INT_THR8_BITS	POW_WQ_INT_THRX_BITS
    825  1.1  hikaru #define	POW_WQ_INT_THR9_BITS	POW_WQ_INT_THRX_BITS
    826  1.1  hikaru #define	POW_WQ_INT_THR10_BITS	POW_WQ_INT_THRX_BITS
    827  1.1  hikaru #define	POW_WQ_INT_THR11_BITS	POW_WQ_INT_THRX_BITS
    828  1.1  hikaru #define	POW_WQ_INT_THR12_BITS	POW_WQ_INT_THRX_BITS
    829  1.1  hikaru #define	POW_WQ_INT_THR13_BITS	POW_WQ_INT_THRX_BITS
    830  1.1  hikaru #define	POW_WQ_INT_THR14_BITS	POW_WQ_INT_THRX_BITS
    831  1.1  hikaru #define	POW_WQ_INT_THR15_BITS	POW_WQ_INT_THRX_BITS
    832  1.1  hikaru #define	POW_WQ_INT_CNTX_BITS \
    833  1.1  hikaru 	"\177"		/* new format */ \
    834  1.1  hikaru 	"\020"		/* hex display */ \
    835  1.1  hikaru 	"\020"		/* %016x format */ \
    836  1.1  hikaru 	"f\x18\x04"	"TC_CNT\0" \
    837  1.1  hikaru 	"f\x0c\x06"	"DS_CNT\0" \
    838  1.1  hikaru 	"f\x00\x06"	"IQ_CNT\0"
    839  1.1  hikaru #define	POW_WQ_INT_CNT0_BITS	POW_WQ_INT_CNTX_BITS
    840  1.1  hikaru #define	POW_WQ_INT_CNT1_BITS	POW_WQ_INT_CNTX_BITS
    841  1.1  hikaru #define	POW_WQ_INT_CNT2_BITS	POW_WQ_INT_CNTX_BITS
    842  1.1  hikaru #define	POW_WQ_INT_CNT3_BITS	POW_WQ_INT_CNTX_BITS
    843  1.1  hikaru #define	POW_WQ_INT_CNT4_BITS	POW_WQ_INT_CNTX_BITS
    844  1.1  hikaru #define	POW_WQ_INT_CNT5_BITS	POW_WQ_INT_CNTX_BITS
    845  1.1  hikaru #define	POW_WQ_INT_CNT6_BITS	POW_WQ_INT_CNTX_BITS
    846  1.1  hikaru #define	POW_WQ_INT_CNT7_BITS	POW_WQ_INT_CNTX_BITS
    847  1.1  hikaru #define	POW_WQ_INT_CNT8_BITS	POW_WQ_INT_CNTX_BITS
    848  1.1  hikaru #define	POW_WQ_INT_CNT9_BITS	POW_WQ_INT_CNTX_BITS
    849  1.1  hikaru #define	POW_WQ_INT_CNT10_BITS	POW_WQ_INT_CNTX_BITS
    850  1.1  hikaru #define	POW_WQ_INT_CNT11_BITS	POW_WQ_INT_CNTX_BITS
    851  1.1  hikaru #define	POW_WQ_INT_CNT12_BITS	POW_WQ_INT_CNTX_BITS
    852  1.1  hikaru #define	POW_WQ_INT_CNT13_BITS	POW_WQ_INT_CNTX_BITS
    853  1.1  hikaru #define	POW_WQ_INT_CNT14_BITS	POW_WQ_INT_CNTX_BITS
    854  1.1  hikaru #define	POW_WQ_INT_CNT15_BITS	POW_WQ_INT_CNTX_BITS
    855  1.1  hikaru #define	POW_QOS_THRX_BITS \
    856  1.1  hikaru 	"\177"		/* new format */ \
    857  1.1  hikaru 	"\020"		/* hex display */ \
    858  1.1  hikaru 	"\020"		/* %016x format */ \
    859  1.1  hikaru 	"f\x30\x07"	"DES_CNT\0" \
    860  1.1  hikaru 	"f\x24\x07"	"BUF_CNT\0" \
    861  1.1  hikaru 	"f\x18\x07"	"FREE_CNT\0" \
    862  1.1  hikaru 	"f\x0c\x06"	"MAX_THR\0" \
    863  1.1  hikaru 	"f\x00\x06"	"MIN_THR\0"
    864  1.1  hikaru #define	POW_QOS_THR0_BITS	POW_QOS_THRX_BITS
    865  1.1  hikaru #define	POW_QOS_THR1_BITS	POW_QOS_THRX_BITS
    866  1.1  hikaru #define	POW_QOS_THR2_BITS	POW_QOS_THRX_BITS
    867  1.1  hikaru #define	POW_QOS_THR3_BITS	POW_QOS_THRX_BITS
    868  1.1  hikaru #define	POW_QOS_THR4_BITS	POW_QOS_THRX_BITS
    869  1.1  hikaru #define	POW_QOS_THR5_BITS	POW_QOS_THRX_BITS
    870  1.1  hikaru #define	POW_QOS_THR6_BITS	POW_QOS_THRX_BITS
    871  1.1  hikaru #define	POW_QOS_THR7_BITS	POW_QOS_THRX_BITS
    872  1.1  hikaru #define	POW_QOS_RNDX_BITS \
    873  1.1  hikaru 	"\177"		/* new format */ \
    874  1.1  hikaru 	"\020"		/* hex display */ \
    875  1.1  hikaru 	"\020"		/* %016x format */ \
    876  1.1  hikaru 	"f\x18\x08"	"RND_P3\0" \
    877  1.1  hikaru 	"f\x10\x08"	"RND_P2\0" \
    878  1.1  hikaru 	"f\x08\x08"	"RND_P1\0" \
    879  1.1  hikaru 	"f\x00\x08"	"RND\0"
    880  1.1  hikaru #define	POW_QOS_RND0_BITS	POW_QOS_RNDX_BITS
    881  1.1  hikaru #define	POW_QOS_RND1_BITS	POW_QOS_RNDX_BITS
    882  1.1  hikaru #define	POW_QOS_RND2_BITS	POW_QOS_RNDX_BITS
    883  1.1  hikaru #define	POW_QOS_RND3_BITS	POW_QOS_RNDX_BITS
    884  1.1  hikaru #define	POW_QOS_RND4_BITS	POW_QOS_RNDX_BITS
    885  1.1  hikaru #define	POW_QOS_RND5_BITS	POW_QOS_RNDX_BITS
    886  1.1  hikaru #define	POW_QOS_RND6_BITS	POW_QOS_RNDX_BITS
    887  1.1  hikaru #define	POW_QOS_RND7_BITS	POW_QOS_RNDX_BITS
    888  1.1  hikaru #define	POW_WQ_INT_BITS \
    889  1.1  hikaru 	"\177"		/* new format */ \
    890  1.1  hikaru 	"\020"		/* hex display */ \
    891  1.1  hikaru 	"\020"		/* %016x format */ \
    892  1.1  hikaru 	"f\x10\x10"	"IQ_DIS\0" \
    893  1.1  hikaru 	"f\x00\x10"	"WQ_INT\0"
    894  1.1  hikaru #define	POW_WQ_INT_PC_BITS \
    895  1.1  hikaru 	"\177"		/* new format */ \
    896  1.1  hikaru 	"\020"		/* hex display */ \
    897  1.1  hikaru 	"\020"		/* %016x format */ \
    898  1.1  hikaru 	"f\x20\x1c"	"PC\0" \
    899  1.1  hikaru 	"f\x08\x14"	"PC_THR\0"
    900  1.1  hikaru #define	POW_NW_TIM_BITS \
    901  1.1  hikaru 	"\177"		/* new format */ \
    902  1.1  hikaru 	"\020"		/* hex display */ \
    903  1.1  hikaru 	"\020"		/* %016x format */ \
    904  1.1  hikaru 	"f\x00\x0a"	"NW_TIM\0"
    905  1.1  hikaru #define	POW_ECC_ERR_BITS \
    906  1.1  hikaru 	"\177"		/* new format */ \
    907  1.1  hikaru 	"\020"		/* hex display */ \
    908  1.1  hikaru 	"\020"		/* %016x format */ \
    909  1.1  hikaru 	"f\x20\x0d"	"IOP_IE\0" \
    910  1.1  hikaru 	"f\x10\x0d"	"IOP\0" \
    911  1.1  hikaru 	"b\x0d"		"RPE_IE\0" \
    912  1.1  hikaru 	"b\x0c"		"RPE\0" \
    913  1.1  hikaru 	"f\x04\x05"	"SYN\0" \
    914  1.1  hikaru 	"b\x03"		"DBE_IE\0" \
    915  1.1  hikaru 	"b\x02"		"SBE_IE\0" \
    916  1.1  hikaru 	"b\x01"		"DBE\0" \
    917  1.1  hikaru 	"b\x00"		"SBE\0"
    918  1.1  hikaru #define	POW_NOS_CNT_BITS \
    919  1.1  hikaru 	"\177"		/* new format */ \
    920  1.1  hikaru 	"\020"		/* hex display */ \
    921  1.1  hikaru 	"\020"		/* %016x format */ \
    922  1.1  hikaru 	"f\x00\x07"	"NOS_CNT\0"
    923  1.1  hikaru #define	POW_WS_PCX_BITS \
    924  1.1  hikaru 	"\177"		/* new format */ \
    925  1.1  hikaru 	"\020"		/* hex display */ \
    926  1.1  hikaru 	"\020"		/* %016x format */ \
    927  1.1  hikaru 
    928  1.1  hikaru #define	POW_WS_PC0_BITS		POW_WS_PCX_BITS
    929  1.1  hikaru #define	POW_WS_PC1_BITS		POW_WS_PCX_BITS
    930  1.1  hikaru #define	POW_WS_PC2_BITS		POW_WS_PCX_BITS
    931  1.1  hikaru #define	POW_WS_PC3_BITS		POW_WS_PCX_BITS
    932  1.1  hikaru #define	POW_WS_PC4_BITS		POW_WS_PCX_BITS
    933  1.1  hikaru #define	POW_WS_PC5_BITS		POW_WS_PCX_BITS
    934  1.1  hikaru #define	POW_WS_PC6_BITS		POW_WS_PCX_BITS
    935  1.1  hikaru #define	POW_WS_PC7_BITS		POW_WS_PCX_BITS
    936  1.1  hikaru #define	POW_WS_PC8_BITS		POW_WS_PCX_BITS
    937  1.1  hikaru #define	POW_WS_PC9_BITS		POW_WS_PCX_BITS
    938  1.1  hikaru #define	POW_WS_PC10_BITS	POW_WS_PCX_BITS
    939  1.1  hikaru #define	POW_WS_PC11_BITS	POW_WS_PCX_BITS
    940  1.1  hikaru #define	POW_WS_PC12_BITS	POW_WS_PCX_BITS
    941  1.1  hikaru #define	POW_WS_PC13_BITS	POW_WS_PCX_BITS
    942  1.1  hikaru #define	POW_WS_PC14_BITS	POW_WS_PCX_BITS
    943  1.1  hikaru #define	POW_WS_PC15_BITS	POW_WS_PCX_BITS
    944  1.1  hikaru #define	POW_WA_PCX_BITS \
    945  1.1  hikaru 	"\177"		/* new format */ \
    946  1.1  hikaru 	"\020"		/* hex display */ \
    947  1.1  hikaru 	"\020"		/* %016x format */ \
    948  1.1  hikaru 
    949  1.1  hikaru #define	POW_WA_PC0_BITS		POW_WA_PCX_BITS
    950  1.1  hikaru #define	POW_WA_PC1_BITS		POW_WA_PCX_BITS
    951  1.1  hikaru #define	POW_WA_PC2_BITS		POW_WA_PCX_BITS
    952  1.1  hikaru #define	POW_WA_PC3_BITS		POW_WA_PCX_BITS
    953  1.1  hikaru #define	POW_WA_PC4_BITS		POW_WA_PCX_BITS
    954  1.1  hikaru #define	POW_WA_PC5_BITS		POW_WA_PCX_BITS
    955  1.1  hikaru #define	POW_WA_PC6_BITS		POW_WA_PCX_BITS
    956  1.1  hikaru #define	POW_WA_PC7_BITS		POW_WA_PCX_BITS
    957  1.1  hikaru #define	POW_IQ_CNTX_BITS \
    958  1.1  hikaru 	"\177"		/* new format */ \
    959  1.1  hikaru 	"\020"		/* hex display */ \
    960  1.1  hikaru 	"\020"		/* %016x format */ \
    961  1.1  hikaru 
    962  1.1  hikaru #define	POW_IQ_CNT0_BITS	POW_IQ_CNTX_BITS
    963  1.1  hikaru #define	POW_IQ_CNT1_BITS	POW_IQ_CNTX_BITS
    964  1.1  hikaru #define	POW_IQ_CNT2_BITS	POW_IQ_CNTX_BITS
    965  1.1  hikaru #define	POW_IQ_CNT3_BITS	POW_IQ_CNTX_BITS
    966  1.1  hikaru #define	POW_IQ_CNT4_BITS	POW_IQ_CNTX_BITS
    967  1.1  hikaru #define	POW_IQ_CNT5_BITS	POW_IQ_CNTX_BITS
    968  1.1  hikaru #define	POW_IQ_CNT6_BITS	POW_IQ_CNTX_BITS
    969  1.1  hikaru #define	POW_IQ_CNT7_BITS	POW_IQ_CNTX_BITS
    970  1.1  hikaru #define	POW_WA_COM_PC_BITS \
    971  1.1  hikaru 	"\177"		/* new format */ \
    972  1.1  hikaru 	"\020"		/* hex display */ \
    973  1.1  hikaru 	"\020"		/* %016x format */ \
    974  1.1  hikaru 	"f\x00\x20"	"WA_PC\0"
    975  1.1  hikaru #define	POW_IQ_COM_CNT_BITS \
    976  1.1  hikaru 	"\177"		/* new format */ \
    977  1.1  hikaru 	"\020"		/* hex display */ \
    978  1.1  hikaru 	"\020"		/* %016x format */ \
    979  1.1  hikaru 
    980  1.1  hikaru #define	POW_TS_PC_BITS \
    981  1.1  hikaru 	"\177"		/* new format */ \
    982  1.1  hikaru 	"\020"		/* hex display */ \
    983  1.1  hikaru 	"\020"		/* %016x format */ \
    984  1.1  hikaru 	"f\x00\x20"	"TS_PC\0"
    985  1.1  hikaru #define	POW_DS_PC_BITS \
    986  1.1  hikaru 	"\177"		/* new format */ \
    987  1.1  hikaru 	"\020"		/* hex display */ \
    988  1.1  hikaru 	"\020"		/* %016x format */ \
    989  1.1  hikaru 	"f\x00\x20"	"DS_PC\0"
    990  1.1  hikaru #define	POW_BIST_STAT_BITS \
    991  1.1  hikaru 	"\177"		/* new format */ \
    992  1.1  hikaru 	"\020"		/* hex display */ \
    993  1.1  hikaru 	"\020"		/* %016x format */ \
    994  1.1  hikaru 	"b\x10"		"PP\0" \
    995  1.1  hikaru 	"b\x08"		"CAM\0" \
    996  1.1  hikaru 	"b\x07"		"NBT1\0" \
    997  1.1  hikaru 	"b\x06"		"NBT0\0" \
    998  1.1  hikaru 	"b\x05"		"IDX\0" \
    999  1.1  hikaru 	"b\x04"		"FIDX\0" \
   1000  1.1  hikaru 	"b\x03"		"NBR1\0" \
   1001  1.1  hikaru 	"b\x02"		"NBR0\0" \
   1002  1.1  hikaru 	"b\x01"		"PEND\0" \
   1003  1.1  hikaru 	"b\x00"		"ADR\0"
   1004  1.1  hikaru 
   1005  1.1  hikaru #endif /* _OCTEON_POWREG_H_ */
   1006