octeon_powvar.h revision 1.1.2.3
1 1.1.2.3 skrll /* $NetBSD: octeon_powvar.h,v 1.1.2.3 2016/10/05 20:55:31 skrll Exp $ */ 2 1.1.2.2 skrll 3 1.1.2.2 skrll /* 4 1.1.2.2 skrll * Copyright (c) 2007 Internet Initiative Japan, Inc. 5 1.1.2.2 skrll * All rights reserved. 6 1.1.2.2 skrll * 7 1.1.2.2 skrll * Redistribution and use in source and binary forms, with or without 8 1.1.2.2 skrll * modification, are permitted provided that the following conditions 9 1.1.2.2 skrll * are met: 10 1.1.2.2 skrll * 1. Redistributions of source code must retain the above copyright 11 1.1.2.2 skrll * notice, this list of conditions and the following disclaimer. 12 1.1.2.2 skrll * 2. Redistributions in binary form must reproduce the above copyright 13 1.1.2.2 skrll * notice, this list of conditions and the following disclaimer in the 14 1.1.2.2 skrll * documentation and/or other materials provided with the distribution. 15 1.1.2.2 skrll * 16 1.1.2.2 skrll * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 17 1.1.2.2 skrll * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 1.1.2.2 skrll * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 1.1.2.2 skrll * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 20 1.1.2.2 skrll * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 1.1.2.2 skrll * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 1.1.2.2 skrll * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 1.1.2.2 skrll * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 1.1.2.2 skrll * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 1.1.2.2 skrll * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 1.1.2.2 skrll * SUCH DAMAGE. 27 1.1.2.2 skrll */ 28 1.1.2.2 skrll 29 1.1.2.2 skrll #ifndef _OCTEON_POWVAR_H_ 30 1.1.2.2 skrll #define _OCTEON_POWVAR_H_ 31 1.1.2.2 skrll 32 1.1.2.2 skrll #include <sys/cpu.h> 33 1.1.2.2 skrll 34 1.1.2.2 skrll #define POW_TAG_TYPE_ORDERED 0 35 1.1.2.2 skrll #define POW_TAG_TYPE_ATOMIC 1 36 1.1.2.2 skrll #define POW_TAG_TYPE_NULL 2 37 1.1.2.2 skrll #define POW_TAG_TYPE_NULL_NULL 3 38 1.1.2.2 skrll 39 1.1.2.2 skrll #define POW_TAG_OP_SWTAG 0 40 1.1.2.2 skrll #define POW_TAG_OP_SWTAG_FULL 1 41 1.1.2.2 skrll #define POW_TAG_OP_SWTAG_DESCHED 2 42 1.1.2.2 skrll #define POW_TAG_OP_DESCHED 3 43 1.1.2.2 skrll #define POW_TAG_OP_ADDWQ 4 44 1.1.2.2 skrll #define POW_TAG_OP_UPD_WQP_GRP 5 45 1.1.2.2 skrll #define POW_TAG_OP_CLR_NSCHED 7 46 1.1.2.2 skrll #define POW_TAG_OP_NOP 15 47 1.1.2.2 skrll 48 1.1.2.2 skrll #define POW_WAIT 1 49 1.1.2.2 skrll #define POW_NO_WAIT 0 50 1.1.2.2 skrll 51 1.1.2.2 skrll /* XXX */ 52 1.1.2.2 skrll struct octeon_pow_softc { 53 1.1.2.2 skrll device_t sc_dev; 54 1.1.2.2 skrll bus_space_tag_t sc_regt; 55 1.1.2.2 skrll bus_space_handle_t sc_regh; 56 1.1.2.2 skrll int sc_port; 57 1.1.2.2 skrll int sc_int_pc_base; 58 1.1.2.2 skrll #ifdef OCTEON_ETH_DEBUG 59 1.1.2.2 skrll struct evcnt sc_ev_powecciopcsrpend; 60 1.1.2.2 skrll struct evcnt sc_ev_powecciopdbgpend; 61 1.1.2.2 skrll struct evcnt sc_ev_powecciopaddwork; 62 1.1.2.2 skrll struct evcnt sc_ev_powecciopillop; 63 1.1.2.2 skrll struct evcnt sc_ev_poweccioppend24; 64 1.1.2.2 skrll struct evcnt sc_ev_poweccioppend23; 65 1.1.2.2 skrll struct evcnt sc_ev_poweccioppend22; 66 1.1.2.2 skrll struct evcnt sc_ev_poweccioppend21; 67 1.1.2.2 skrll struct evcnt sc_ev_poweccioptagnull; 68 1.1.2.2 skrll struct evcnt sc_ev_poweccioptagnullnull; 69 1.1.2.2 skrll struct evcnt sc_ev_powecciopordatom; 70 1.1.2.2 skrll struct evcnt sc_ev_powecciopnull; 71 1.1.2.2 skrll struct evcnt sc_ev_powecciopnullnull; 72 1.1.2.2 skrll struct evcnt sc_ev_poweccrpe; 73 1.1.2.2 skrll struct evcnt sc_ev_poweccsyn; 74 1.1.2.2 skrll struct evcnt sc_ev_poweccdbe; 75 1.1.2.2 skrll struct evcnt sc_ev_poweccsbe; 76 1.1.2.2 skrll #endif 77 1.1.2.2 skrll }; 78 1.1.2.2 skrll 79 1.1.2.2 skrll /* XXX */ 80 1.1.2.2 skrll struct octeon_pow_attach_args { 81 1.1.2.2 skrll int aa_port; 82 1.1.2.2 skrll bus_space_tag_t aa_regt; 83 1.1.2.2 skrll }; 84 1.1.2.2 skrll 85 1.1.2.2 skrll void octeon_pow_config(struct octeon_pow_softc *, int); 86 1.1.2.2 skrll void *octeon_pow_intr_establish(int, int, 87 1.1.2.2 skrll void (*)(void *, uint64_t *), 88 1.1.2.2 skrll void (*)(int *, int *, uint64_t, void *), 89 1.1.2.2 skrll void *); 90 1.1.2.2 skrll void octeon_pow_error_int_enable(void *, int); 91 1.1.2.2 skrll uint64_t octeon_pow_error_int_summary(void *); 92 1.1.2.2 skrll int octeon_pow_ring_reduce(void *); 93 1.1.2.2 skrll int octeon_pow_ring_grow(void *); 94 1.1.2.2 skrll int octeon_pow_ring_size(void); 95 1.1.2.2 skrll int octeon_pow_ring_intr(void); 96 1.1.2.2 skrll 97 1.1.2.2 skrll #define _POW_RD8(sc, off) \ 98 1.1.2.2 skrll bus_space_read_8((sc)->sc_regt, (sc)->sc_regh, (off)) 99 1.1.2.2 skrll #define _POW_WR8(sc, off, v) \ 100 1.1.2.2 skrll bus_space_write_8((sc)->sc_regt, (sc)->sc_regh, (off), (v)) 101 1.1.2.2 skrll #define _POW_GROUP_RD8(sc, pi, off) \ 102 1.1.2.2 skrll bus_space_read_8((sc)->sc_regt, (sc)->sc_regh, \ 103 1.1.2.2 skrll (off) + sizeof(uint64_t) * (pi)->pi_group) 104 1.1.2.2 skrll #define _POW_GROUP_WR8(sc, pi, off, v) \ 105 1.1.2.2 skrll bus_space_write_8((sc)->sc_regt, (sc)->sc_regh, \ 106 1.1.2.2 skrll (off) + sizeof(uint64_t) * (pi)->pi_group, (v)) 107 1.1.2.2 skrll 108 1.1.2.2 skrll extern struct octeon_pow_softc octeon_pow_softc; 109 1.1.2.2 skrll 110 1.1.2.2 skrll /* -------------------------------------------------------------------------- */ 111 1.1.2.2 skrll 112 1.1.2.2 skrll /* Load Operations */ 113 1.1.2.2 skrll 114 1.1.2.2 skrll /* GET_WORK Loads */ 115 1.1.2.2 skrll 116 1.1.2.3 skrll static inline uint64_t 117 1.1.2.2 skrll octeon_pow_ops_get_work_load( 118 1.1.2.2 skrll int wait) /* 0-1 */ 119 1.1.2.2 skrll { 120 1.1.2.2 skrll uint64_t ptr = 121 1.1.2.2 skrll POW_OPERATION_BASE_IO_BIT | 122 1.1.2.2 skrll __BITS64_SET(POW_OPERATION_BASE_MAJOR_DID, 0x0c) | 123 1.1.2.2 skrll __BITS64_SET(POW_OPERATION_BASE_SUB_DID, 0x00) | 124 1.1.2.2 skrll __BITS64_SET(POW_GET_WORK_LOAD_WAIT, wait); 125 1.1.2.2 skrll 126 1.1.2.2 skrll return octeon_xkphys_read_8(ptr); 127 1.1.2.2 skrll } 128 1.1.2.2 skrll 129 1.1.2.2 skrll /* POW Status Loads */ 130 1.1.2.2 skrll 131 1.1.2.2 skrll /* 132 1.1.2.2 skrll * a) get_cur == 0, get_wqp == 0 (pend_tag) 133 1.1.2.2 skrll * b) get_cur == 0, get_wqp == 1 (pend_wqp) 134 1.1.2.2 skrll * c) get_cur == 1, get_wqp == 0, get_rev == 0 (cur_tag_next) 135 1.1.2.2 skrll * d) get_cur == 1, get_wqp == 0, get_rev == 1 (cur_tag_prev) 136 1.1.2.2 skrll * e) get_cur == 1, get_wqp == 1, get_rev == 0 (cur_wqp_next) 137 1.1.2.2 skrll * f) get_cur == 1, get_wqp == 1, get_rev == 1 (cur_wqp_prev) 138 1.1.2.2 skrll */ 139 1.1.2.2 skrll 140 1.1.2.2 skrll static inline uint64_t 141 1.1.2.2 skrll octeon_pow_ops_pow_status( 142 1.1.2.2 skrll int coreid, /* 0-15 */ 143 1.1.2.2 skrll int get_rev, /* 0-1 */ 144 1.1.2.2 skrll int get_cur, /* 0-1 */ 145 1.1.2.2 skrll int get_wqp) /* 0-1 */ 146 1.1.2.2 skrll { 147 1.1.2.2 skrll uint64_t ptr = 148 1.1.2.2 skrll POW_OPERATION_BASE_IO_BIT | 149 1.1.2.2 skrll __BITS64_SET(POW_OPERATION_BASE_MAJOR_DID, 0x0c) | 150 1.1.2.2 skrll __BITS64_SET(POW_OPERATION_BASE_SUB_DID, 0x01) | 151 1.1.2.2 skrll __BITS64_SET(POW_STATUS_LOAD_COREID, coreid) | 152 1.1.2.2 skrll __BITS64_SET(POW_STATUS_LOAD_GET_REV, get_rev) | 153 1.1.2.2 skrll __BITS64_SET(POW_STATUS_LOAD_GET_CUR, get_cur) | 154 1.1.2.2 skrll __BITS64_SET(POW_STATUS_LOAD_GET_WQP, get_wqp); 155 1.1.2.2 skrll 156 1.1.2.2 skrll return octeon_xkphys_read_8(ptr); 157 1.1.2.2 skrll } 158 1.1.2.2 skrll 159 1.1.2.2 skrll /* POW Memory Loads */ 160 1.1.2.2 skrll 161 1.1.2.2 skrll /* 162 1.1.2.2 skrll * a) get_des == 0, get_wqp == 0 (tag) 163 1.1.2.2 skrll * b) get_des == 0, get_wqp == 1 (wqe) 164 1.1.2.2 skrll * c) get_des == 1 (desched) 165 1.1.2.2 skrll */ 166 1.1.2.2 skrll 167 1.1.2.2 skrll static inline uint64_t 168 1.1.2.2 skrll octeon_pow_ops_pow_memory( 169 1.1.2.2 skrll int index, /* 0-2047 */ 170 1.1.2.2 skrll int get_des, /* 0-1 */ 171 1.1.2.2 skrll int get_wqp) /* 0-1 */ 172 1.1.2.2 skrll { 173 1.1.2.2 skrll uint64_t ptr = 174 1.1.2.2 skrll POW_OPERATION_BASE_IO_BIT | 175 1.1.2.2 skrll __BITS64_SET(POW_OPERATION_BASE_MAJOR_DID, 0x0c) | 176 1.1.2.2 skrll __BITS64_SET(POW_OPERATION_BASE_SUB_DID, 0x02) | 177 1.1.2.2 skrll __BITS64_SET(POW_MEMORY_LOAD_INDEX, index) | 178 1.1.2.2 skrll __BITS64_SET(POW_MEMORY_LOAD_GET_DES, get_des) | 179 1.1.2.2 skrll __BITS64_SET(POW_MEMORY_LOAD_GET_WQP, get_wqp); 180 1.1.2.2 skrll 181 1.1.2.2 skrll return octeon_xkphys_read_8(ptr); 182 1.1.2.2 skrll } 183 1.1.2.2 skrll 184 1.1.2.2 skrll /* POW Index/Pointer Loads */ 185 1.1.2.2 skrll 186 1.1.2.2 skrll /* 187 1.1.2.2 skrll * a) get_rmt == 0, get_des_get_tail == 0 188 1.1.2.2 skrll * b) get_rmt == 0, get_des_get_tail == 1 189 1.1.2.2 skrll * c) get_rmt == 1, get_des_get_tail == 0 190 1.1.2.2 skrll * d) get_rmt == 1, get_des_get_tail == 1 191 1.1.2.2 skrll */ 192 1.1.2.2 skrll 193 1.1.2.2 skrll static inline uint64_t 194 1.1.2.2 skrll octeon_pow_ops_pow_idxptr( 195 1.1.2.2 skrll int qosgrp, /* 0-7 */ 196 1.1.2.2 skrll int get_des_get_tail, /* 0-1 */ 197 1.1.2.2 skrll int get_rmt) /* 0-1 */ 198 1.1.2.2 skrll { 199 1.1.2.2 skrll uint64_t ptr = 200 1.1.2.2 skrll POW_OPERATION_BASE_IO_BIT | 201 1.1.2.2 skrll __BITS64_SET(POW_OPERATION_BASE_MAJOR_DID, 0x0c) | 202 1.1.2.2 skrll __BITS64_SET(POW_OPERATION_BASE_SUB_DID, 0x03) | 203 1.1.2.2 skrll __BITS64_SET(POW_IDXPTR_LOAD_QOSGRP, qosgrp) | 204 1.1.2.2 skrll __BITS64_SET(POW_IDXPTR_LOAD_GET_DES_GET_TAIL, get_des_get_tail) | 205 1.1.2.2 skrll __BITS64_SET(POW_IDXPTR_LOAD_GET_RMT, get_rmt); 206 1.1.2.2 skrll 207 1.1.2.2 skrll return octeon_xkphys_read_8(ptr); 208 1.1.2.2 skrll } 209 1.1.2.2 skrll 210 1.1.2.2 skrll /* NULL_RD Loads */ 211 1.1.2.2 skrll 212 1.1.2.2 skrll static inline uint64_t 213 1.1.2.2 skrll octeon_pow_ops_null_rd_load(void) 214 1.1.2.2 skrll { 215 1.1.2.2 skrll uint64_t ptr = 216 1.1.2.2 skrll POW_OPERATION_BASE_IO_BIT | 217 1.1.2.2 skrll __BITS64_SET(POW_OPERATION_BASE_MAJOR_DID, 0x0c) | 218 1.1.2.2 skrll __BITS64_SET(POW_OPERATION_BASE_SUB_DID, 0x04); 219 1.1.2.2 skrll 220 1.1.2.2 skrll return octeon_xkphys_read_8(ptr); 221 1.1.2.2 skrll } 222 1.1.2.2 skrll 223 1.1.2.2 skrll /* IOBDMA Operations */ 224 1.1.2.2 skrll 225 1.1.2.2 skrll /* ``subdid'' values are inverted between ``get_work_addr'' and ``null_read_id'' */ 226 1.1.2.2 skrll 227 1.1.2.2 skrll /* The ``scraddr'' part is index in 8 byte words, not address. */ 228 1.1.2.2 skrll 229 1.1.2.2 skrll /* GET_WORK IOBDMAs */ 230 1.1.2.2 skrll 231 1.1.2.2 skrll static inline void 232 1.1.2.2 skrll octeon_pow_ops_get_work_iobdma( 233 1.1.2.2 skrll int scraddr, /* 0-2047 */ 234 1.1.2.2 skrll int wait) /* 0-1 */ 235 1.1.2.2 skrll { 236 1.1.2.2 skrll /* ``scraddr'' part is index in 64-bit words, not address */ 237 1.1.2.2 skrll const int scrindex = scraddr / sizeof(uint64_t); 238 1.1.2.2 skrll 239 1.1.2.2 skrll uint64_t args = 240 1.1.2.2 skrll __BITS64_SET(POW_IOBDMA_GET_WORK_WAIT, wait); 241 1.1.2.2 skrll uint64_t value = 242 1.1.2.2 skrll __BITS64_SET(POW_IOBDMA_BASE_SCRADDR, scrindex) | 243 1.1.2.2 skrll __BITS64_SET(POW_IOBDMA_BASE_LEN, 0x01) | 244 1.1.2.2 skrll __BITS64_SET(POW_IOBDMA_BASE_MAJOR_DID, 0x0c) | 245 1.1.2.2 skrll __BITS64_SET(POW_IOBDMA_BASE_SUB_DID, 0x00) | 246 1.1.2.2 skrll __BITS64_SET(POW_IOBDMA_BASE_39_0, args); 247 1.1.2.2 skrll 248 1.1.2.2 skrll octeon_iobdma_write_8(value); 249 1.1.2.2 skrll } 250 1.1.2.2 skrll 251 1.1.2.2 skrll /* NULL_RD IOBDMAs */ 252 1.1.2.2 skrll 253 1.1.2.2 skrll static inline void 254 1.1.2.2 skrll octeon_pow_ops_null_rd_iobdma( 255 1.1.2.2 skrll int scraddr) /* 0-2047 */ 256 1.1.2.2 skrll { 257 1.1.2.2 skrll /* ``scraddr'' part is index in 64-bit words, not address */ 258 1.1.2.2 skrll const int scrindex = scraddr / sizeof(uint64_t); 259 1.1.2.2 skrll 260 1.1.2.2 skrll uint64_t value = 261 1.1.2.2 skrll __BITS64_SET(POW_IOBDMA_BASE_SCRADDR, scrindex) | 262 1.1.2.2 skrll __BITS64_SET(POW_IOBDMA_BASE_LEN, 0x01) | 263 1.1.2.2 skrll __BITS64_SET(POW_IOBDMA_BASE_MAJOR_DID, 0x0c) | 264 1.1.2.2 skrll __BITS64_SET(POW_IOBDMA_BASE_SUB_DID, 0x04) | 265 1.1.2.2 skrll __BITS64_SET(POW_IOBDMA_BASE_39_0, 0); 266 1.1.2.2 skrll 267 1.1.2.2 skrll octeon_iobdma_write_8(value); 268 1.1.2.2 skrll } 269 1.1.2.2 skrll 270 1.1.2.2 skrll /* Store Operations */ 271 1.1.2.2 skrll 272 1.1.2.2 skrll static inline void 273 1.1.2.2 skrll octeon_pow_store( 274 1.1.2.2 skrll int subdid, /* 0, 1, 3 */ 275 1.1.2.2 skrll uint64_t addr, /* 0-0x0000.000f.ffff.ffff */ 276 1.1.2.2 skrll int no_sched, /* 0, 1 */ 277 1.1.2.2 skrll int index, /* 0-8191 */ 278 1.1.2.2 skrll int op, /* 0-15 */ 279 1.1.2.2 skrll int qos, /* 0-7 */ 280 1.1.2.2 skrll int grp, /* 0-7 */ 281 1.1.2.2 skrll int type, /* 0-7 */ 282 1.1.2.2 skrll uint32_t tag) /* 0-0xffff.ffff */ 283 1.1.2.2 skrll { 284 1.1.2.2 skrll /* Physical Address to Store to POW */ 285 1.1.2.2 skrll uint64_t ptr = 286 1.1.2.2 skrll POW_OPERATION_BASE_IO_BIT | 287 1.1.2.2 skrll __BITS64_SET(POW_OPERATION_BASE_MAJOR_DID, 0x0c) | 288 1.1.2.2 skrll __BITS64_SET(POW_OPERATION_BASE_SUB_DID, subdid) | 289 1.1.2.3 skrll __BITS64_SET(POW_PHY_ADDR_STORE_ADDR, addr); 290 1.1.2.2 skrll 291 1.1.2.2 skrll /* Store Data on Store to POW */ 292 1.1.2.2 skrll uint64_t args = 293 1.1.2.2 skrll __BITS64_SET(POW_STORE_DATA_NO_SCHED, no_sched) | 294 1.1.2.2 skrll __BITS64_SET(POW_STORE_DATA_INDEX, index) | 295 1.1.2.2 skrll __BITS64_SET(POW_STORE_DATA_OP, op) | 296 1.1.2.2 skrll __BITS64_SET(POW_STORE_DATA_QOS, qos) | 297 1.1.2.2 skrll __BITS64_SET(POW_STORE_DATA_GRP, grp) | 298 1.1.2.2 skrll __BITS64_SET(POW_STORE_DATA_TYPE, type) | 299 1.1.2.3 skrll __BITS64_SET(POW_STORE_DATA_TAG, tag); 300 1.1.2.2 skrll 301 1.1.2.2 skrll octeon_xkphys_write_8(ptr, args); 302 1.1.2.2 skrll } 303 1.1.2.2 skrll 304 1.1.2.2 skrll /* SWTAG */ 305 1.1.2.2 skrll 306 1.1.2.2 skrll static inline void 307 1.1.2.2 skrll octeon_pow_ops_swtag(int type, uint32_t tag) 308 1.1.2.2 skrll { 309 1.1.2.2 skrll octeon_pow_store( 310 1.1.2.2 skrll 1, /* subdid == 1 */ 311 1.1.2.2 skrll 0, /* addr (not used for SWTAG) */ 312 1.1.2.2 skrll 0, /* no_sched (not used for SWTAG) */ 313 1.1.2.2 skrll 0, /* index (not used for SWTAG) */ 314 1.1.2.2 skrll POW_TAG_OP_SWTAG, /* op == SWTAG */ 315 1.1.2.2 skrll 0, /* qos (not used for SWTAG) */ 316 1.1.2.2 skrll 0, /* grp (not used for SWTAG) */ 317 1.1.2.2 skrll type, 318 1.1.2.2 skrll tag); 319 1.1.2.2 skrll /* switch to NULL completes immediately */ 320 1.1.2.2 skrll } 321 1.1.2.2 skrll 322 1.1.2.2 skrll /* SWTAG_FULL */ 323 1.1.2.2 skrll 324 1.1.2.2 skrll static inline void 325 1.1.2.2 skrll octeon_pow_ops_swtag_full(paddr_t addr, int grp, int type, uint32_t tag) 326 1.1.2.2 skrll { 327 1.1.2.2 skrll octeon_pow_store( 328 1.1.2.2 skrll 0, /* subdid == 0 */ 329 1.1.2.2 skrll addr, 330 1.1.2.2 skrll 0, /* no_sched (not used for SWTAG_FULL) */ 331 1.1.2.2 skrll 0, /* index (not used for SWTAG_FULL) */ 332 1.1.2.2 skrll POW_TAG_OP_SWTAG_FULL, /* op == SWTAG_FULL */ 333 1.1.2.2 skrll 0, /* qos (not used for SWTAG_FULL) */ 334 1.1.2.2 skrll grp, 335 1.1.2.2 skrll type, 336 1.1.2.2 skrll tag); 337 1.1.2.2 skrll } 338 1.1.2.2 skrll 339 1.1.2.2 skrll /* SWTAG_DESCHED */ 340 1.1.2.2 skrll 341 1.1.2.2 skrll static inline void 342 1.1.2.2 skrll octeon_pow_ops_swtag_desched(int no_sched, int grp, int type, uint32_t tag) 343 1.1.2.2 skrll { 344 1.1.2.2 skrll octeon_pow_store( 345 1.1.2.2 skrll 3, /* subdid == 3 */ 346 1.1.2.2 skrll 0, /* addr (not used for SWTAG_DESCHED) */ 347 1.1.2.2 skrll no_sched, 348 1.1.2.2 skrll 0, /* index (not used for SWTAG_DESCHED) */ 349 1.1.2.2 skrll POW_TAG_OP_SWTAG_DESCHED, /* op == SWTAG_DESCHED */ 350 1.1.2.2 skrll 0, /* qos (not used for SWTAG_DESCHED) */ 351 1.1.2.2 skrll grp, 352 1.1.2.2 skrll type, 353 1.1.2.2 skrll tag); 354 1.1.2.2 skrll } 355 1.1.2.2 skrll 356 1.1.2.2 skrll /* DESCHED */ 357 1.1.2.2 skrll 358 1.1.2.2 skrll static inline void 359 1.1.2.2 skrll octeon_pow_ops_desched(int no_sched) 360 1.1.2.2 skrll { 361 1.1.2.2 skrll octeon_pow_store( 362 1.1.2.2 skrll 3, /* subdid == 3 */ 363 1.1.2.2 skrll 0, /* addr (not used for DESCHED) */ 364 1.1.2.2 skrll no_sched, 365 1.1.2.2 skrll 0, /* index (not used for DESCHED) */ 366 1.1.2.2 skrll POW_TAG_OP_DESCHED, /* op == DESCHED */ 367 1.1.2.2 skrll 0, /* qos (not used for DESCHED) */ 368 1.1.2.2 skrll 0, /* grp (not used for DESCHED) */ 369 1.1.2.2 skrll 0, /* type (not used for DESCHED) */ 370 1.1.2.2 skrll 0); /* tag (not used for DESCHED) */ 371 1.1.2.2 skrll } 372 1.1.2.2 skrll 373 1.1.2.2 skrll /* ADDWQ */ 374 1.1.2.2 skrll 375 1.1.2.2 skrll static inline void 376 1.1.2.2 skrll octeon_pow_ops_addwq(paddr_t addr, int qos, int grp, int type, uint32_t tag) 377 1.1.2.2 skrll { 378 1.1.2.2 skrll octeon_pow_store( 379 1.1.2.2 skrll 1, /* subdid == 1 */ 380 1.1.2.2 skrll addr, 381 1.1.2.2 skrll 0, /* no_sched (not used for ADDWQ) */ 382 1.1.2.2 skrll 0, /* index (not used for ADDWQ) */ 383 1.1.2.2 skrll POW_TAG_OP_ADDWQ, /* op == ADDWQ */ 384 1.1.2.2 skrll qos, 385 1.1.2.2 skrll grp, 386 1.1.2.2 skrll type, 387 1.1.2.2 skrll tag); 388 1.1.2.2 skrll } 389 1.1.2.2 skrll 390 1.1.2.2 skrll /* UPD_WQP_GRP */ 391 1.1.2.2 skrll 392 1.1.2.2 skrll static inline void 393 1.1.2.2 skrll octeon_pow_ops_upd_wqp_grp(paddr_t addr, int grp) 394 1.1.2.2 skrll { 395 1.1.2.2 skrll octeon_pow_store( 396 1.1.2.2 skrll 1, /* subdid == 1 */ 397 1.1.2.2 skrll addr, 398 1.1.2.2 skrll 0, /* no_sched (not used for UPD_WQP_GRP) */ 399 1.1.2.2 skrll 0, /* index (not used for UPD_WQP_GRP) */ 400 1.1.2.2 skrll POW_TAG_OP_UPD_WQP_GRP, /* op == UPD_WQP_GRP */ 401 1.1.2.2 skrll 0, /* qos (not used for UPD_WQP_GRP) */ 402 1.1.2.2 skrll grp, 403 1.1.2.2 skrll 0, /* type (not used for UPD_WQP_GRP) */ 404 1.1.2.2 skrll 0); /* tag (not used for UPD_WQP_GRP) */ 405 1.1.2.2 skrll } 406 1.1.2.2 skrll 407 1.1.2.2 skrll /* CLR_NSCHED */ 408 1.1.2.2 skrll 409 1.1.2.2 skrll static inline void 410 1.1.2.2 skrll octeon_pow_ops_clr_nsched(paddr_t addr, int index) 411 1.1.2.2 skrll { 412 1.1.2.2 skrll octeon_pow_store( 413 1.1.2.2 skrll 1, /* subdid == 1 */ 414 1.1.2.2 skrll addr, 415 1.1.2.2 skrll 0, /* no_sched (not used for CLR_NSCHED) */ 416 1.1.2.2 skrll index, 417 1.1.2.2 skrll POW_TAG_OP_CLR_NSCHED, /* op == CLR_NSCHED */ 418 1.1.2.2 skrll 0, /* qos (not used for CLR_NSCHED) */ 419 1.1.2.2 skrll 0, /* grp (not used for CLR_NSCHED) */ 420 1.1.2.2 skrll 0, /* type (not used for CLR_NSCHED) */ 421 1.1.2.2 skrll 0); /* tag (not used for CLR_NSCHED) */ 422 1.1.2.2 skrll } 423 1.1.2.2 skrll 424 1.1.2.2 skrll /* NOP */ 425 1.1.2.2 skrll 426 1.1.2.2 skrll static inline void 427 1.1.2.2 skrll octeon_pow_ops_nop(void) 428 1.1.2.2 skrll { 429 1.1.2.2 skrll octeon_pow_store( 430 1.1.2.2 skrll 1, /* subdid == 1 */ 431 1.1.2.2 skrll 0, /* addr (not used for NOP) */ 432 1.1.2.2 skrll 0, /* no_sched (not used for NOP) */ 433 1.1.2.2 skrll 0, /* index (not used for NOP) */ 434 1.1.2.2 skrll POW_TAG_OP_NOP, /* op == NOP */ 435 1.1.2.2 skrll 0, /* qos (not used for NOP) */ 436 1.1.2.2 skrll 0, /* grp (not used for NOP) */ 437 1.1.2.2 skrll 0, /* type (not used for NOP) */ 438 1.1.2.2 skrll 0); /* tag (not used for NOP) */ 439 1.1.2.2 skrll } 440 1.1.2.2 skrll 441 1.1.2.2 skrll /* -------------------------------------------------------------------------- */ 442 1.1.2.2 skrll 443 1.1.2.2 skrll /* 444 1.1.2.2 skrll * global functions 445 1.1.2.2 skrll */ 446 1.1.2.2 skrll static inline void 447 1.1.2.2 skrll octeon_pow_work_request_async(uint64_t scraddr, uint64_t wait) 448 1.1.2.2 skrll { 449 1.1.2.2 skrll octeon_pow_ops_get_work_iobdma(scraddr, wait); 450 1.1.2.2 skrll } 451 1.1.2.2 skrll 452 1.1.2.2 skrll static inline uint64_t * 453 1.1.2.2 skrll octeon_pow_work_response_async(uint64_t scraddr) 454 1.1.2.2 skrll { 455 1.1.2.2 skrll uint64_t result; 456 1.1.2.2 skrll 457 1.1.2.2 skrll OCTEON_SYNCIOBDMA; 458 1.1.2.2 skrll result = octeon_cvmseg_read_8(scraddr); 459 1.1.2.2 skrll 460 1.1.2.3 skrll paddr_t addr = result & POW_IOBDMA_GET_WORK_RESULT_ADDR; 461 1.1.2.3 skrll 462 1.1.2.3 skrll if (result & POW_IOBDMA_GET_WORK_RESULT_NO_WORK) 463 1.1.2.3 skrll return NULL; 464 1.1.2.3 skrll #ifdef __mips_n32 465 1.1.2.3 skrll KASSERT(addr < MIPS_PHYS_MASK); 466 1.1.2.3 skrll //if (addr < MIPS_PHYS_MASK) 467 1.1.2.3 skrll return (uint64_t *)MIPS_PHYS_TO_KSEG0(addr); 468 1.1.2.3 skrll #else 469 1.1.2.3 skrll return (uint64_t *)MIPS_PHYS_TO_XKPHYS_CACHED(addr); 470 1.1.2.3 skrll #endif 471 1.1.2.2 skrll } 472 1.1.2.2 skrll 473 1.1.2.2 skrll static inline void 474 1.1.2.2 skrll octeon_pow_config_int_pc(struct octeon_pow_softc *sc, int unit) 475 1.1.2.2 skrll { 476 1.1.2.2 skrll uint64_t wq_int_pc; 477 1.1.2.2 skrll uint64_t pc_thr; 478 1.1.2.2 skrll static uint64_t cpu_clock_hz; 479 1.1.2.2 skrll 480 1.1.2.2 skrll if (cpu_clock_hz == 0) 481 1.1.2.2 skrll cpu_clock_hz = curcpu()->ci_cpu_freq; 482 1.1.2.3 skrll 483 1.1.2.2 skrll /* from SDK */ 484 1.1.2.2 skrll pc_thr = (cpu_clock_hz) / (unit * 16 * 256); 485 1.1.2.2 skrll 486 1.1.2.2 skrll wq_int_pc = pc_thr << POW_WQ_INT_PC_PC_THR_SHIFT; 487 1.1.2.2 skrll _POW_WR8(sc, POW_WQ_INT_PC_OFFSET, wq_int_pc); 488 1.1.2.2 skrll } 489 1.1.2.2 skrll 490 1.1.2.2 skrll static inline void 491 1.1.2.2 skrll octeon_pow_config_int_pc_rate(struct octeon_pow_softc *sc, int rate) 492 1.1.2.2 skrll { 493 1.1.2.2 skrll octeon_pow_config_int_pc(sc, sc->sc_int_pc_base / rate); 494 1.1.2.2 skrll } 495 1.1.2.2 skrll 496 1.1.2.2 skrll /* wait until ready */ 497 1.1.2.2 skrll static inline void 498 1.1.2.2 skrll octeon_pow_tag_sw_wait(void) 499 1.1.2.2 skrll { 500 1.1.2.2 skrll __asm __volatile ( 501 1.1.2.2 skrll " .set push \n" 502 1.1.2.2 skrll " .set noreorder \n" 503 1.1.2.2 skrll " .set arch=octeon \n" 504 1.1.2.2 skrll "1: rdhwr $2, $30 \n" 505 1.1.2.2 skrll " beqz $2, 1b \n" 506 1.1.2.2 skrll " nop \n" 507 1.1.2.2 skrll " .set pop \n" 508 1.1.2.2 skrll ); 509 1.1.2.2 skrll } 510 1.1.2.2 skrll 511 1.1.2.2 skrll #endif /* _OCTEON_POWVAR_H_ */ 512
Indexes created Fri Oct 03 02:09:57 GMT 2025