octeon_twsi.c revision 1.1.2.2
1 1.1.2.2 skrll /* $NetBSD: octeon_twsi.c,v 1.1.2.2 2015/06/06 14:40:01 skrll Exp $ */ 2 1.1.2.2 skrll 3 1.1.2.2 skrll /* 4 1.1.2.2 skrll * Copyright (c) 2007 Internet Initiative Japan, Inc. 5 1.1.2.2 skrll * All rights reserved. 6 1.1.2.2 skrll * 7 1.1.2.2 skrll * Redistribution and use in source and binary forms, with or without 8 1.1.2.2 skrll * modification, are permitted provided that the following conditions 9 1.1.2.2 skrll * are met: 10 1.1.2.2 skrll * 1. Redistributions of source code must retain the above copyright 11 1.1.2.2 skrll * notice, this list of conditions and the following disclaimer. 12 1.1.2.2 skrll * 2. Redistributions in binary form must reproduce the above copyright 13 1.1.2.2 skrll * notice, this list of conditions and the following disclaimer in the 14 1.1.2.2 skrll * documentation and/or other materials provided with the distribution. 15 1.1.2.2 skrll * 16 1.1.2.2 skrll * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 17 1.1.2.2 skrll * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 1.1.2.2 skrll * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 1.1.2.2 skrll * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 20 1.1.2.2 skrll * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 1.1.2.2 skrll * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 1.1.2.2 skrll * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 1.1.2.2 skrll * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 1.1.2.2 skrll * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 1.1.2.2 skrll * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 1.1.2.2 skrll * SUCH DAMAGE. 27 1.1.2.2 skrll */ 28 1.1.2.2 skrll 29 1.1.2.2 skrll #undef TWSIDEBUG 30 1.1.2.2 skrll #undef TWSITEST 31 1.1.2.2 skrll 32 1.1.2.2 skrll #include <sys/cdefs.h> 33 1.1.2.2 skrll __KERNEL_RCSID(0, "$NetBSD: octeon_twsi.c,v 1.1.2.2 2015/06/06 14:40:01 skrll Exp $"); 34 1.1.2.2 skrll 35 1.1.2.2 skrll #include "opt_octeon.h" 36 1.1.2.2 skrll 37 1.1.2.2 skrll #include <sys/param.h> 38 1.1.2.2 skrll #include <sys/systm.h> 39 1.1.2.2 skrll #include <sys/types.h> 40 1.1.2.2 skrll #include <sys/device.h> 41 1.1.2.2 skrll #include <sys/lock.h> 42 1.1.2.2 skrll 43 1.1.2.2 skrll #include <sys/bus.h> 44 1.1.2.2 skrll 45 1.1.2.2 skrll #include <dev/i2c/i2cvar.h> 46 1.1.2.2 skrll 47 1.1.2.2 skrll #include <mips/cavium/include/iobusvar.h> 48 1.1.2.2 skrll #include <mips/cavium/dev/octeon_twsireg.h> 49 1.1.2.2 skrll 50 1.1.2.2 skrll #ifdef TWSIDEBUG 51 1.1.2.2 skrll #define DPRINTF(x) printf x 52 1.1.2.2 skrll #else 53 1.1.2.2 skrll #define DPRINTF(x) 54 1.1.2.2 skrll #endif 55 1.1.2.2 skrll 56 1.1.2.2 skrll struct octeon_twsi_reg; 57 1.1.2.2 skrll 58 1.1.2.2 skrll struct octeon_twsi_softc { 59 1.1.2.2 skrll device_t sc_dev; 60 1.1.2.2 skrll bus_space_tag_t sc_regt; 61 1.1.2.2 skrll bus_space_handle_t sc_regh; 62 1.1.2.2 skrll 63 1.1.2.2 skrll void *sc_ih; 64 1.1.2.2 skrll 65 1.1.2.2 skrll struct i2c_controller sc_i2c; 66 1.1.2.2 skrll struct lock sc_lock; 67 1.1.2.2 skrll 68 1.1.2.2 skrll /* ... */ 69 1.1.2.2 skrll }; 70 1.1.2.2 skrll 71 1.1.2.2 skrll /* Auto-configuration */ 72 1.1.2.2 skrll 73 1.1.2.2 skrll static int octeon_twsi_match(device_t, struct cfdata *, 74 1.1.2.2 skrll void *); 75 1.1.2.2 skrll static void octeon_twsi_attach(device_t, device_t, 76 1.1.2.2 skrll void *); 77 1.1.2.2 skrll 78 1.1.2.2 skrll /* High-Level Controller Master */ 79 1.1.2.2 skrll 80 1.1.2.2 skrll #ifdef notyet 81 1.1.2.2 skrll static uint8_t octeon_twsi_hlcm_read_1(struct octeon_twsi_softc *, 82 1.1.2.2 skrll ...) 83 1.1.2.2 skrll static uint64_t octeon_twsi_hlcm_read_4(struct octeon_twsi_softc *, 84 1.1.2.2 skrll ...) 85 1.1.2.2 skrll static void octeon_twsi_hlcm_read(struct octeon_twsi_softc *, 86 1.1.2.2 skrll ...) 87 1.1.2.2 skrll static void octeon_twsi_hlcm_write_1(struct octeon_twsi_softc *, 88 1.1.2.2 skrll ...) 89 1.1.2.2 skrll static void octeon_twsi_hlcm_write_4(struct octeon_twsi_softc *, 90 1.1.2.2 skrll ...) 91 1.1.2.2 skrll static void octeon_twsi_hlcm_write(struct octeon_twsi_softc *, 92 1.1.2.2 skrll ...) 93 1.1.2.2 skrll #endif 94 1.1.2.2 skrll 95 1.1.2.2 skrll /* High-Level Controller Slave */ 96 1.1.2.2 skrll 97 1.1.2.2 skrll /* XXX */ 98 1.1.2.2 skrll 99 1.1.2.2 skrll /* Control Register */ 100 1.1.2.2 skrll 101 1.1.2.2 skrll #ifdef notyet 102 1.1.2.2 skrll #define _CONTROL_READ(sc, reg) \ 103 1.1.2.2 skrll octeon_twsi_control_read((sc), MIO_TWS_SW_TWSI_EOP_IA_##reg) 104 1.1.2.2 skrll #define _CONTROL_WRITE(sc, reg, value) \ 105 1.1.2.2 skrll octeon_twsi_control_write((sc), MIO_TWS_SW_TWSI_EOP_IA_##reg, value) 106 1.1.2.2 skrll static uint8_t octeon_twsi_control_read(struct octeon_twsi_softc *sc, 107 1.1.2.2 skrll uint64_t); 108 1.1.2.2 skrll static void octeon_twsi_control_write(struct octeon_twsi_softc *sc, 109 1.1.2.2 skrll uint64_t, uint8_t); 110 1.1.2.2 skrll #endif 111 1.1.2.2 skrll 112 1.1.2.2 skrll /* Register accessors */ 113 1.1.2.2 skrll 114 1.1.2.2 skrll static inline uint64_t octeon_twsi_reg_rd(struct octeon_twsi_softc *, int); 115 1.1.2.2 skrll static inline void octeon_twsi_reg_wr(struct octeon_twsi_softc *, int, 116 1.1.2.2 skrll uint64_t); 117 1.1.2.2 skrll #ifdef TWSIDEBUG 118 1.1.2.2 skrll static inline void octeon_twsi_reg_dump(struct octeon_twsi_softc *, int); 119 1.1.2.2 skrll #endif 120 1.1.2.2 skrll 121 1.1.2.2 skrll /* Test functions */ 122 1.1.2.2 skrll 123 1.1.2.2 skrll #ifdef TWSIDEBUG 124 1.1.2.2 skrll static void octeon_twsi_test(struct octeon_twsi_softc *); 125 1.1.2.2 skrll #endif 126 1.1.2.2 skrll 127 1.1.2.2 skrll /* Debug functions */ 128 1.1.2.2 skrll 129 1.1.2.2 skrll #ifdef TWSIDEBUG 130 1.1.2.2 skrll static inline void octeon_twsi_debug_reg_dump(struct octeon_twsi_softc *, 131 1.1.2.2 skrll int); 132 1.1.2.2 skrll static void octeon_twsi_debug_dumpregs(struct octeon_twsi_softc *); 133 1.1.2.2 skrll static void octeon_twsi_debug_dumpreg(struct octeon_twsi_softc *, 134 1.1.2.2 skrll const struct octeon_twsi_reg *); 135 1.1.2.2 skrll #endif 136 1.1.2.2 skrll 137 1.1.2.2 skrll /* -------------------------------------------------------------------------- */ 138 1.1.2.2 skrll 139 1.1.2.2 skrll /* 140 1.1.2.2 skrll * Auto-configuration 141 1.1.2.2 skrll */ 142 1.1.2.2 skrll 143 1.1.2.2 skrll CFATTACH_DECL_NEW(octeon_twsi, sizeof(struct octeon_twsi_softc), 144 1.1.2.2 skrll octeon_twsi_match, octeon_twsi_attach, NULL, NULL); 145 1.1.2.2 skrll 146 1.1.2.2 skrll static int 147 1.1.2.2 skrll octeon_twsi_match(device_t parent, struct cfdata *cf, void *aux) 148 1.1.2.2 skrll { 149 1.1.2.2 skrll struct iobus_attach_args *aa = aux; 150 1.1.2.2 skrll 151 1.1.2.2 skrll if (strcmp(cf->cf_name, aa->aa_name) != 0) 152 1.1.2.2 skrll return 0; 153 1.1.2.2 skrll return 1; 154 1.1.2.2 skrll } 155 1.1.2.2 skrll 156 1.1.2.2 skrll static void 157 1.1.2.2 skrll octeon_twsi_attach(device_t parent, device_t self, void *aux) 158 1.1.2.2 skrll { 159 1.1.2.2 skrll struct octeon_twsi_softc *sc = device_private(self); 160 1.1.2.2 skrll struct iobus_attach_args *aa = aux; 161 1.1.2.2 skrll int status; 162 1.1.2.2 skrll 163 1.1.2.2 skrll sc->sc_dev = self; 164 1.1.2.2 skrll sc->sc_regt = aa->aa_bust; 165 1.1.2.2 skrll 166 1.1.2.2 skrll status = bus_space_map(sc->sc_regt, MIO_TWS_BASE_0, MIO_TWS_SIZE, 0, 167 1.1.2.2 skrll &sc->sc_regh); 168 1.1.2.2 skrll if (status != 0) 169 1.1.2.2 skrll panic(": can't map register"); 170 1.1.2.2 skrll 171 1.1.2.2 skrll aprint_normal("\n"); 172 1.1.2.2 skrll 173 1.1.2.2 skrll #ifdef TWSITEST 174 1.1.2.2 skrll octeon_twsi_test(sc); 175 1.1.2.2 skrll #endif 176 1.1.2.2 skrll } 177 1.1.2.2 skrll 178 1.1.2.2 skrll /* -------------------------------------------------------------------------- */ 179 1.1.2.2 skrll 180 1.1.2.2 skrll /* 181 1.1.2.2 skrll * Initialization, basic operations 182 1.1.2.2 skrll */ 183 1.1.2.2 skrll 184 1.1.2.2 skrll #ifdef notyet 185 1.1.2.2 skrll 186 1.1.2.2 skrll static void 187 1.1.2.2 skrll octeon_twsi_wait(struct octeon_twsi_softc *sc) 188 1.1.2.2 skrll { 189 1.1.2.2 skrll } 190 1.1.2.2 skrll 191 1.1.2.2 skrll static void 192 1.1.2.2 skrll octeon_twsi_intr(struct octeon_twsi_softc *sc) 193 1.1.2.2 skrll { 194 1.1.2.2 skrll } 195 1.1.2.2 skrll 196 1.1.2.2 skrll static void 197 1.1.2.2 skrll octeon_twsi_lock(struct octeon_twsi_softc *sc) 198 1.1.2.2 skrll { 199 1.1.2.2 skrll } 200 1.1.2.2 skrll 201 1.1.2.2 skrll static void 202 1.1.2.2 skrll octeon_twsi_unlock(struct octeon_twsi_softc *sc) 203 1.1.2.2 skrll { 204 1.1.2.2 skrll } 205 1.1.2.2 skrll 206 1.1.2.2 skrll #endif 207 1.1.2.2 skrll 208 1.1.2.2 skrll /* -------------------------------------------------------------------------- */ 209 1.1.2.2 skrll 210 1.1.2.2 skrll /* 211 1.1.2.2 skrll * High-Level Controller as a Master 212 1.1.2.2 skrll */ 213 1.1.2.2 skrll 214 1.1.2.2 skrll #ifdef notyet 215 1.1.2.2 skrll 216 1.1.2.2 skrll #define _BUFTOLE32(buf) \ 217 1.1.2.2 skrll ((buf[0] << 24) | (buf[1] << 16) | (buf[2] << 8) | (buf[3] << 0)) 218 1.1.2.2 skrll #define _LE32TOBUF(buf, x) \ 219 1.1.2.2 skrll do { \ 220 1.1.2.2 skrll buf[0] = (char)((x) >> 24); \ 221 1.1.2.2 skrll buf[1] = (char)((x) >> 16); \ 222 1.1.2.2 skrll buf[2] = (char)((x) >> 8); \ 223 1.1.2.2 skrll buf[3] = (char)((x) >> 0); \ 224 1.1.2.2 skrll } while (0) 225 1.1.2.2 skrll 226 1.1.2.2 skrll static void 227 1.1.2.2 skrll octeon_twsi_hlcm_read(struct octeon_twsi_softc *sc, int addr, char *buf, 228 1.1.2.2 skrll size_t len) 229 1.1.2.2 skrll { 230 1.1.2.2 skrll uint64_t cmd; 231 1.1.2.2 skrll size_t resid; 232 1.1.2.2 skrll 233 1.1.2.2 skrll octeon_twsi_lock(sc); 234 1.1.2.2 skrll 235 1.1.2.2 skrll #ifdef notyet 236 1.1.2.2 skrll 237 1.1.2.2 skrll octeon_twsi_hlcm_setup(sc); 238 1.1.2.2 skrll 239 1.1.2.2 skrll resid = len; 240 1.1.2.2 skrll 241 1.1.2.2 skrll while (resid > 4) { 242 1.1.2.2 skrll cmd = MIO_TWS_SW_TWSI_OP_FOUR | MIO_TWS_SW_TWSI_R 243 1.1.2.2 skrll | (addr << MIO_TWS_SW_TWSI_A_SHIFT); 244 1.1.2.2 skrll octeon_twsi_reg_wr(sc, MIO_TWS_SW_TWSI_OFFSET, cmd); 245 1.1.2.2 skrll octeon_twsi_wait(sc); 246 1.1.2.2 skrll cmd = octeon_twsi_reg_rd(sc); 247 1.1.2.2 skrll _LE32TOBUF(&buf[len - 1 - resid], (uint32_t)cmd); 248 1.1.2.2 skrll resid -= 4; 249 1.1.2.2 skrll } 250 1.1.2.2 skrll 251 1.1.2.2 skrll while (resid > 0) { 252 1.1.2.2 skrll cmd = MIO_TWS_SW_TWSI_OP_ONE | MIO_TWS_SW_TWSI_R 253 1.1.2.2 skrll | (addr << MIO_TWS_SW_TWSI_A_SHIFT); 254 1.1.2.2 skrll octeon_twsi_reg_wr(sc, MIO_TWS_SW_TWSI_OFFSET, cmd); 255 1.1.2.2 skrll octeon_twsi_wait(sc); 256 1.1.2.2 skrll cmd = octeon_twsi_reg_rd(sc); 257 1.1.2.2 skrll buf[len - 1 - resid] = (uint8_t)cmd; 258 1.1.2.2 skrll resid--; 259 1.1.2.2 skrll } 260 1.1.2.2 skrll 261 1.1.2.2 skrll #endif 262 1.1.2.2 skrll 263 1.1.2.2 skrll octeon_twsi_unlock(sc); 264 1.1.2.2 skrll } 265 1.1.2.2 skrll 266 1.1.2.2 skrll static void 267 1.1.2.2 skrll octeon_twsi_hlcm_write(struct octeon_twsi_softc *sc, int addr, char *buf, 268 1.1.2.2 skrll size_t len) 269 1.1.2.2 skrll { 270 1.1.2.2 skrll uint64_t cmd; 271 1.1.2.2 skrll size_t resid; 272 1.1.2.2 skrll 273 1.1.2.2 skrll octeon_twsi_lock(sc); 274 1.1.2.2 skrll 275 1.1.2.2 skrll #ifdef notyet 276 1.1.2.2 skrll 277 1.1.2.2 skrll octeon_twsi_hlcm_setup(sc); 278 1.1.2.2 skrll 279 1.1.2.2 skrll resid = len; 280 1.1.2.2 skrll 281 1.1.2.2 skrll while (resid > 4) { 282 1.1.2.2 skrll cmd = MIO_TWS_SW_TWSI_OP_FOUR 283 1.1.2.2 skrll | (addr << MIO_TWS_SW_TWSI_A_SHIFT) 284 1.1.2.2 skrll | _BUFTOLE32(&buf[len - 1 - resid]); 285 1.1.2.2 skrll octeon_twsi_reg_wr(sc, MIO_TWS_SW_TWSI_OFFSET, cmd); 286 1.1.2.2 skrll octeon_twsi_wait(sc); 287 1.1.2.2 skrll resid -= 4; 288 1.1.2.2 skrll } 289 1.1.2.2 skrll 290 1.1.2.2 skrll while (resid > 0) { 291 1.1.2.2 skrll cmd = MIO_TWS_SW_TWSI_OP_ONE 292 1.1.2.2 skrll | (addr << MIO_TWS_SW_TWSI_A_SHIFT) 293 1.1.2.2 skrll | buf[len - 1 - resid]; 294 1.1.2.2 skrll octeon_twsi_reg_wr(sc, MIO_TWS_SW_TWSI_OFFSET, cmd); 295 1.1.2.2 skrll octeon_twsi_wait(sc); 296 1.1.2.2 skrll resid--; 297 1.1.2.2 skrll } 298 1.1.2.2 skrll 299 1.1.2.2 skrll /* MIO_TWS_SW_TWSI:V must be zero */ 300 1.1.2.2 skrll 301 1.1.2.2 skrll /* check error */ 302 1.1.2.2 skrll if (MIO_TWS_SW_TWSI:R == 0) { 303 1.1.2.2 skrll code = MIO_TWS_SW_TWSI:D; 304 1.1.2.2 skrll } 305 1.1.2.2 skrll #endif 306 1.1.2.2 skrll 307 1.1.2.2 skrll octeon_twsi_unlock(sc); 308 1.1.2.2 skrll } 309 1.1.2.2 skrll 310 1.1.2.2 skrll static void 311 1.1.2.2 skrll octeon_twsi_hlcm_setup(struct octeon_twsi_softc *sc, ...) 312 1.1.2.2 skrll { 313 1.1.2.2 skrll /* XXX */ 314 1.1.2.2 skrll 315 1.1.2.2 skrll _CONTROL_WR(sc, TWSI_CTL, TWSI_CTL_CE | TWSI_CTL_ENAB | TWSI_AAK); 316 1.1.2.2 skrll } 317 1.1.2.2 skrll 318 1.1.2.2 skrll static uint8_t 319 1.1.2.2 skrll octeon_twsi_hlcm_read_1(struct octeon_twsi_softc *sc, ...) 320 1.1.2.2 skrll { 321 1.1.2.2 skrll /* XXX */ 322 1.1.2.2 skrll return 0; 323 1.1.2.2 skrll } 324 1.1.2.2 skrll 325 1.1.2.2 skrll static uint64_t 326 1.1.2.2 skrll octeon_twsi_hlcm_read_4(struct octeon_twsi_softc *sc, ...) 327 1.1.2.2 skrll { 328 1.1.2.2 skrll /* XXX */ 329 1.1.2.2 skrll return 0; 330 1.1.2.2 skrll } 331 1.1.2.2 skrll 332 1.1.2.2 skrll static void 333 1.1.2.2 skrll octeon_twsi_hlcm_write_1(struct octeon_twsi_softc *sc, ...) 334 1.1.2.2 skrll { 335 1.1.2.2 skrll /* XXX */ 336 1.1.2.2 skrll } 337 1.1.2.2 skrll 338 1.1.2.2 skrll static void 339 1.1.2.2 skrll octeon_twsi_hlcm_write_4(struct octeon_twsi_softc *sc, ...) 340 1.1.2.2 skrll { 341 1.1.2.2 skrll /* XXX */ 342 1.1.2.2 skrll } 343 1.1.2.2 skrll 344 1.1.2.2 skrll #endif 345 1.1.2.2 skrll 346 1.1.2.2 skrll /* -------------------------------------------------------------------------- */ 347 1.1.2.2 skrll 348 1.1.2.2 skrll /* 349 1.1.2.2 skrll * High-Level Controller as a Slave 350 1.1.2.2 skrll */ 351 1.1.2.2 skrll 352 1.1.2.2 skrll #ifdef notyet 353 1.1.2.2 skrll 354 1.1.2.2 skrll static void 355 1.1.2.2 skrll octeon_twsi_hlcs_setup(struct octeon_twsi_softc *sc, ...) 356 1.1.2.2 skrll { 357 1.1.2.2 skrll /* XXX */ 358 1.1.2.2 skrll } 359 1.1.2.2 skrll 360 1.1.2.2 skrll #endif 361 1.1.2.2 skrll 362 1.1.2.2 skrll /* -------------------------------------------------------------------------- */ 363 1.1.2.2 skrll 364 1.1.2.2 skrll /* 365 1.1.2.2 skrll * TWSI Control Register operations 366 1.1.2.2 skrll */ 367 1.1.2.2 skrll 368 1.1.2.2 skrll #ifdef notyet 369 1.1.2.2 skrll 370 1.1.2.2 skrll static uint8_t 371 1.1.2.2 skrll octeon_twsi_control_read(struct octeon_twsi_softc *sc, uint64_t eop_ia) 372 1.1.2.2 skrll { 373 1.1.2.2 skrll uint64_t cmd; 374 1.1.2.2 skrll 375 1.1.2.2 skrll cmd = MIO_TWS_SW_TWSI_OP_EXTEND 376 1.1.2.2 skrll | (addr << MIO_TWS_SW_TWSI_A_SHIFT) 377 1.1.2.2 skrll | eop_ia; 378 1.1.2.2 skrll octeon_twsi_reg_wr(sc, MIO_TWS_SW_TWSI_OFFSET, cmd); 379 1.1.2.2 skrll octeon_twsi_wait(sc); 380 1.1.2.2 skrll return (uint8_t)octeon_twsi_reg_rd(sc, MIO_TWS_SW_TWSI_OFFSET); 381 1.1.2.2 skrll } 382 1.1.2.2 skrll 383 1.1.2.2 skrll static void 384 1.1.2.2 skrll octeon_twsi_control_write(struct octeon_twsi_softc *sc, uint64_t eop_ia, 385 1.1.2.2 skrll char *buf, size_t len) 386 1.1.2.2 skrll { 387 1.1.2.2 skrll uint64_t cmd; 388 1.1.2.2 skrll 389 1.1.2.2 skrll cmd = MIO_TWS_SW_TWSI_OP_EXTEND 390 1.1.2.2 skrll | (addr << MIO_TWS_SW_TWSI_A_SHIFT) 391 1.1.2.2 skrll | eop_ia 392 1.1.2.2 skrll | _BUFTOLE32(&buf[len - 1 - resid]); 393 1.1.2.2 skrll octeon_twsi_reg_wr(sc, MIO_TWS_SW_TWSI_OFFSET, cmd); 394 1.1.2.2 skrll octeon_twsi_wait(sc); 395 1.1.2.2 skrll } 396 1.1.2.2 skrll 397 1.1.2.2 skrll #endif 398 1.1.2.2 skrll 399 1.1.2.2 skrll /* -------------------------------------------------------------------------- */ 400 1.1.2.2 skrll 401 1.1.2.2 skrll /* 402 1.1.2.2 skrll * Send / receive operations 403 1.1.2.2 skrll */ 404 1.1.2.2 skrll 405 1.1.2.2 skrll /* Send (== software to TWSI) */ 406 1.1.2.2 skrll 407 1.1.2.2 skrll #ifdef notyet 408 1.1.2.2 skrll 409 1.1.2.2 skrll static void 410 1.1.2.2 skrll octeon_twsi_send(struct octeon_twsi_softc *sc, ...) 411 1.1.2.2 skrll { 412 1.1.2.2 skrll octeon_twsi_reg_wr(sc, MIO_TWS_SW_TWSI_OFFSET, ...); 413 1.1.2.2 skrll } 414 1.1.2.2 skrll 415 1.1.2.2 skrll /* Receive (== TWSI to software) */ 416 1.1.2.2 skrll 417 1.1.2.2 skrll static void 418 1.1.2.2 skrll octeon_twsi_recv(struct octeon_twsi_softc *sc, ...) 419 1.1.2.2 skrll { 420 1.1.2.2 skrll /* XXX */ 421 1.1.2.2 skrll octeon_twsi_reg_wr(sc, MIO_TWS_SW_TWSI_OFFSET, ...); 422 1.1.2.2 skrll octeon_twsi_wait(sc, MIO_TWS_SW_TWSI_OFFSET, ...); 423 1.1.2.2 skrll octeon_twsi_reg_rd(sc, MIO_TWS_SW_TWSI_OFFSET, ...); 424 1.1.2.2 skrll } 425 1.1.2.2 skrll 426 1.1.2.2 skrll #endif 427 1.1.2.2 skrll 428 1.1.2.2 skrll /* -------------------------------------------------------------------------- */ 429 1.1.2.2 skrll 430 1.1.2.2 skrll /* 431 1.1.2.2 skrll * Register accessors 432 1.1.2.2 skrll */ 433 1.1.2.2 skrll 434 1.1.2.2 skrll static inline uint64_t 435 1.1.2.2 skrll octeon_twsi_reg_rd(struct octeon_twsi_softc *sc, int offset) 436 1.1.2.2 skrll { 437 1.1.2.2 skrll return bus_space_read_8(sc->sc_regt, sc->sc_regh, offset); 438 1.1.2.2 skrll } 439 1.1.2.2 skrll 440 1.1.2.2 skrll static inline void 441 1.1.2.2 skrll octeon_twsi_reg_wr(struct octeon_twsi_softc *sc, int offset, uint64_t value) 442 1.1.2.2 skrll { 443 1.1.2.2 skrll bus_space_write_8(sc->sc_regt, sc->sc_regh, offset, value); 444 1.1.2.2 skrll } 445 1.1.2.2 skrll 446 1.1.2.2 skrll #ifdef TWSIDEBUG 447 1.1.2.2 skrll 448 1.1.2.2 skrll void 449 1.1.2.2 skrll octeon_twsi_reg_dump(struct octeon_twsi_softc *sc, int offset) 450 1.1.2.2 skrll { 451 1.1.2.2 skrll octeon_twsi_debug_reg_dump(sc, offset); 452 1.1.2.2 skrll } 453 1.1.2.2 skrll 454 1.1.2.2 skrll #endif 455 1.1.2.2 skrll 456 1.1.2.2 skrll /* -------------------------------------------------------------------------- */ 457 1.1.2.2 skrll 458 1.1.2.2 skrll /* 459 1.1.2.2 skrll * Test functions 460 1.1.2.2 skrll */ 461 1.1.2.2 skrll 462 1.1.2.2 skrll #ifdef TWSITEST 463 1.1.2.2 skrll 464 1.1.2.2 skrll void 465 1.1.2.2 skrll octeon_twsi_test(struct octeon_twsi_softc *sc) 466 1.1.2.2 skrll { 467 1.1.2.2 skrll octeon_twsi_debug_dumpregs(sc); 468 1.1.2.2 skrll } 469 1.1.2.2 skrll 470 1.1.2.2 skrll #endif 471 1.1.2.2 skrll 472 1.1.2.2 skrll /* -------------------------------------------------------------------------- */ 473 1.1.2.2 skrll 474 1.1.2.2 skrll #ifdef TWSIDEBUG 475 1.1.2.2 skrll 476 1.1.2.2 skrll /* 477 1.1.2.2 skrll * Debug functions 478 1.1.2.2 skrll * 479 1.1.2.2 skrll * octeon_twsi_debug_reg_dump 480 1.1.2.2 skrll * octeon_twsi_debug_dumpregs 481 1.1.2.2 skrll * octeon_twsi_debug_dumpreg 482 1.1.2.2 skrll */ 483 1.1.2.2 skrll 484 1.1.2.2 skrll struct octeon_twsi_reg { 485 1.1.2.2 skrll const char *name; 486 1.1.2.2 skrll int offset; 487 1.1.2.2 skrll const char *format; 488 1.1.2.2 skrll }; 489 1.1.2.2 skrll 490 1.1.2.2 skrll static const struct octeon_twsi_reg octeon_twsi_regs[] = { 491 1.1.2.2 skrll #define _ENTRY(x) { #x, x##_OFFSET, x##_BITS } 492 1.1.2.2 skrll _ENTRY(MIO_TWS_SW_TWSI), 493 1.1.2.2 skrll _ENTRY(MIO_TWS_TWSI_SW), 494 1.1.2.2 skrll _ENTRY(MIO_TWS_INT), 495 1.1.2.2 skrll _ENTRY(MIO_TWS_SW_TWSI_EXT) 496 1.1.2.2 skrll #undef _ENTRY 497 1.1.2.2 skrll }; 498 1.1.2.2 skrll 499 1.1.2.2 skrll void 500 1.1.2.2 skrll octeon_twsi_debug_reg_dump(struct octeon_twsi_softc *sc, int offset) 501 1.1.2.2 skrll { 502 1.1.2.2 skrll int i; 503 1.1.2.2 skrll const struct octeon_twsi_reg *reg; 504 1.1.2.2 skrll 505 1.1.2.2 skrll reg = NULL; 506 1.1.2.2 skrll for (i = 0; i < (int)__arraycount(octeon_twsi_regs); i++) 507 1.1.2.2 skrll if (octeon_twsi_regs[i].offset == offset) { 508 1.1.2.2 skrll reg = &octeon_twsi_regs[i]; 509 1.1.2.2 skrll break; 510 1.1.2.2 skrll } 511 1.1.2.2 skrll KASSERT(reg != NULL); 512 1.1.2.2 skrll 513 1.1.2.2 skrll octeon_twsi_debug_dumpreg(sc, reg); 514 1.1.2.2 skrll } 515 1.1.2.2 skrll 516 1.1.2.2 skrll void 517 1.1.2.2 skrll octeon_twsi_debug_dumpregs(struct octeon_twsi_softc *sc) 518 1.1.2.2 skrll { 519 1.1.2.2 skrll int i; 520 1.1.2.2 skrll 521 1.1.2.2 skrll for (i = 0; i < (int)__arraycount(octeon_twsi_regs); i++) 522 1.1.2.2 skrll octeon_twsi_debug_dumpreg(sc, &octeon_twsi_regs[i]); 523 1.1.2.2 skrll } 524 1.1.2.2 skrll 525 1.1.2.2 skrll void 526 1.1.2.2 skrll octeon_twsi_debug_dumpreg(struct octeon_twsi_softc *sc, 527 1.1.2.2 skrll const struct octeon_twsi_reg *reg) 528 1.1.2.2 skrll { 529 1.1.2.2 skrll uint64_t value; 530 1.1.2.2 skrll char buf[256]; 531 1.1.2.2 skrll 532 1.1.2.2 skrll value = octeon_twsi_reg_rd(sc, reg->offset); 533 1.1.2.2 skrll snprintb(buf, sizeof(buf), reg->format, value); 534 1.1.2.2 skrll printf("\t%-24s: %s\n", reg->name, buf); 535 1.1.2.2 skrll } 536 1.1.2.2 skrll 537 1.1.2.2 skrll #endif 538
Indexes created Thu Oct 02 14:10:14 GMT 2025