octeon_twsireg.h revision 1.1
1 /* $NetBSD: octeon_twsireg.h,v 1.1 2015/04/29 08:32:01 hikaru Exp $ */ 2 3 /* 4 * Copyright (c) 2007 Internet Initiative Japan, Inc. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 /* 30 * TWSI Registers 31 */ 32 33 #ifndef _OCTEON_TWSIREG_H_ 34 #define _OCTEON_TWSIREG_H_ 35 36 /* ---- register addresses */ 37 38 #define MIO_TWS_SW_TWSI 0x0001180000001000ULL 39 #define MIO_TWS_TWSI_SW 0x0001180000001008ULL 40 #define MIO_TWS_INT 0x0001180000001010ULL 41 #define MIO_TWS_SW_TWSI_EXT 0x0001180000001018ULL 42 43 /* ---- register bits */ 44 45 #define MIO_TWS_SW_TWSI_V UINT64_C(0x8000000000000000) 46 #define MIO_TWS_SW_TWSI_SLONLY UINT64_C(0x4000000000000000) 47 #define MIO_TWS_SW_TWSI_EIA UINT64_C(0x2000000000000000) 48 #define MIO_TWS_SW_TWSI_OP UINT64_C(0x1e00000000000000) 49 #define MIO_TWS_SW_TWSI_OP_SHIFT 57 50 #define MIO_TWS_SW_TWSI_OP_ONE (0x0 << MIO_TWS_SW_TWSI_OP_SHIFT) 51 #define MIO_TWS_SW_TWSI_OP_MCLK (0x4 << MIO_TWS_SW_TWSI_OP_SHIFT) 52 #define MIO_TWS_SW_TWSI_OP_EXTEND (0x6 << MIO_TWS_SW_TWSI_OP_SHIFT) 53 #define MIO_TWS_SW_TWSI_OP_FOUR (0x8 << MIO_TWS_SW_TWSI_OP_SHIFT) 54 #define MIO_TWS_SW_TWSI_OP_COMBR (0x1 << MIO_TWS_SW_TWSI_OP_SHIFT) 55 #define MIO_TWS_SW_TWSI_OP_10BIT (0x2 << MIO_TWS_SW_TWSI_OP_SHIFT) 56 #define MIO_TWS_SW_TWSI_R UINT64_C(0x0100000000000000) 57 #define MIO_TWS_SW_TWSI_SOVR UINT64_C(0x0080000000000000) 58 #define MIO_TWS_SW_TWSI_SIZE UINT64_C(0x0070000000000000) 59 #define MIO_TWS_SW_TWSI_SCR UINT64_C(0x000c000000000000) 60 #define MIO_TWS_SW_TWSI_A UINT64_C(0x0003ff0000000000) 61 #define MIO_TWS_SW_TWSI_A_SHIFT 40 62 #define MIO_TWS_SW_TWSI_IA UINT64_C(0x000000f800000000) 63 #define MIO_TWS_SW_TWSI_EOP_IA UINT64_C(0x0000000700000000) 64 #define MIO_TWS_SW_TWSI_EOP_IA_SHIFT 32 65 #define MIO_TWS_SW_TWSI_EOP_IA_TWSI_SLAVE_ADD (0x0 << MIO_TWS_SW_TWSI_EOP_IA_SHIFT) 66 #define MIO_TWS_SW_TWSI_EOP_IA_TWSI_DATA (0x1 << MIO_TWS_SW_TWSI_EOP_IA_SHIFT) 67 #define MIO_TWS_SW_TWSI_EOP_IA_TWSI_CTL (0x2 << MIO_TWS_SW_TWSI_EOP_IA_SHIFT) 68 #define MIO_TWS_SW_TWSI_EOP_IA_TWSI_CLKCTL (0x3 << MIO_TWS_SW_TWSI_EOP_IA_SHIFT) 69 #define MIO_TWS_SW_TWSI_EOP_IA_TWSI_STAT (0x3 << MIO_TWS_SW_TWSI_EOP_IA_SHIFT) 70 #define MIO_TWS_SW_TWSI_EOP_IA_TWSI_SLAVE_ADD_EXT \ 71 (0x4 << MIO_TWS_SW_TWSI_EOP_IA_SHIFT) 72 #define MIO_TWS_SW_TWSI_EOP_IA_TWSI_RST (0x7 << MIO_TWS_SW_TWSI_EOP_IA_SHIFT) 73 #define MIO_TWS_SW_TWSI_D UINT64_C(0x00000000ffffffff) 74 75 #define MIO_TWS_TWSI_SW_V UINT64_C(0xc000000000000000) 76 #define MIO_TWS_TWSI_SW_XXX_61_32 UINT64_C(0x3fffffff00000000) 77 #define MIO_TWS_TWSI_SW_D UINT64_C(0x00000000ffffffff) 78 79 #define MIO_TWS_INT_XXX_63_12 UINT64_C(0xfffffffffffff000) 80 #define MIO_TWS_INT_SCL UINT64_C(0x0000000000000800) 81 #define MIO_TWS_INT_SDA UINT64_C(0x0000000000000400) 82 #define MIO_TWS_INT_SCL_OVR UINT64_C(0x0000000000000200) 83 #define MIO_TWS_INT_SDA_OVR UINT64_C(0x0000000000000100) 84 #define MIO_TWS_INT_XXX_7 UINT64_C(0x0000000000000080) 85 #define MIO_TWS_INT_CORE_EN UINT64_C(0x0000000000000040) 86 #define MIO_TWS_INT_TS_EN UINT64_C(0x0000000000000020) 87 #define MIO_TWS_INT_ST_EN UINT64_C(0x0000000000000010) 88 #define MIO_TWS_INT_XXX_3 UINT64_C(0x0000000000000008) 89 #define MIO_TWS_INT_CORE_INT UINT64_C(0x0000000000000004) 90 #define MIO_TWS_INT_TS_INT UINT64_C(0x0000000000000002) 91 #define MIO_TWS_INT_ST_INT UINT64_C(0x0000000000000001) 92 93 #define MIO_TWS_SW_TWSI_EXT_XXX_63_40 UINT64_C(0xffffff0000000000) 94 #define MIO_TWS_SW_TWSI_EXT_IA UINT64_C(0x000000ff00000000) 95 #define MIO_TWS_SW_TWSI_EXT_D UINT64_C(0x00000000ffffffff) 96 97 /* 98 * TWSI Control Registers 99 */ 100 101 /* TWSI Slave Address Registers */ 102 103 #define TWSI_SLAVE_ADD_ADDR 0xfe 104 #define TWSI_SLAVE_ADD_GCE UINT8_C(0x01) 105 106 /* TWSI Slave Extended-Address Registers */ 107 108 /* TWSI Data Register */ 109 110 /* TWSI Control Register */ 111 112 #define TWSI_CTL_CE UINT8_C(0x80) 113 #define TWSI_CTL_ENAB UINT8_C(0x40) 114 #define TWSI_CTL_STA UINT8_C(0x20) 115 #define TWSI_CTL_STP UINT8_C(0x10) 116 #define TWSI_CTL_IFLG UINT8_C(0x08) 117 #define TWSI_CTL_AAK UINT8_C(0x04) 118 #define TWSI_CTL_XXX_1_0 0x03 119 120 /* TWSI Status Register */ 121 122 /* ---- snprintb */ 123 124 #define MIO_TWS_SW_TWSI_BITS \ 125 "\177" /* new format */ \ 126 "\020" /* hex display */ \ 127 "\020" /* %016x format */ \ 128 "b\x3f" "V\0" \ 129 "b\x3e" "SLONLY\0" \ 130 "b\x3d" "EIA\0" \ 131 "f\x39\x04" "OP\0" \ 132 "b\x38" "R\0" \ 133 "b\x37" "SOVR\0" \ 134 "f\x34\x03" "SIZE\0" \ 135 "f\x32\x02" "SCR\0" \ 136 "f\x28\x0a" "A\0" \ 137 "f\x23\x05" "IA\0" \ 138 "f\x20\x03" "EOP_IA\0" \ 139 "f\x00\x20" "D\0" 140 141 #define MIO_TWS_TWSI_SW_BITS \ 142 "\177" /* new format */ \ 143 "\020" /* hex display */ \ 144 "\020" /* %016x format */ \ 145 "f\x3e\x02" "V\0" \ 146 "f\x00\x20" "D\0" 147 148 #define MIO_TWS_INT_BITS \ 149 "\177" /* new format */ \ 150 "\020" /* hex display */ \ 151 "\020" /* %016x format */ \ 152 "b\x0b" "SCL\0" \ 153 "b\x0a" "SDA\0" \ 154 "b\x09" "SCL_OVR\0" \ 155 "b\x08" "SDA_OVR\0" \ 156 "b\x06" "CORE_EN\0" \ 157 "b\x05" "TS_EN\0" \ 158 "b\x04" "ST_EN\0" \ 159 "b\x02" "CORE_INT\0" \ 160 "b\x01" "TS_INT\0" \ 161 "b\x00" "ST_INT\0" 162 163 #define MIO_TWS_SW_TWSI_EXT_BITS \ 164 "\177" /* new format */ \ 165 "\020" /* hex display */ \ 166 "\020" /* %016x format */ \ 167 "f\x20\x08" "IA\0" \ 168 "f\x00\x20" "D\0" 169 170 /* ---- bus_space */ 171 172 #define MIO_TWS_NUNITS 1 173 #define MIO_TWS_BASE_0 0x0001180000001000ULL 174 #define MIO_TWS_SIZE 0x0020 175 176 #define MIO_TWS_SW_TWSI_OFFSET 0x0000 177 #define MIO_TWS_TWSI_SW_OFFSET 0x0008 178 #define MIO_TWS_INT_OFFSET 0x0010 179 #define MIO_TWS_SW_TWSI_EXT_OFFSET 0x0018 180 181 #endif /* _OCTEON_TWSIREG_H_ */ 182
Indexes created Mon Sep 29 21:09:56 GMT 2025