octeon_uart.c revision 1.3.2.2
1 1.3.2.2 skrll /* $NetBSD: octeon_uart.c,v 1.3.2.2 2015/06/06 14:40:01 skrll Exp $ */ 2 1.3.2.2 skrll 3 1.3.2.2 skrll /* 4 1.3.2.2 skrll * Copyright (c) 2007 Internet Initiative Japan, Inc. 5 1.3.2.2 skrll * All rights reserved. 6 1.3.2.2 skrll * 7 1.3.2.2 skrll * Redistribution and use in source and binary forms, with or without 8 1.3.2.2 skrll * modification, are permitted provided that the following conditions 9 1.3.2.2 skrll * are met: 10 1.3.2.2 skrll * 1. Redistributions of source code must retain the above copyright 11 1.3.2.2 skrll * notice, this list of conditions and the following disclaimer. 12 1.3.2.2 skrll * 2. Redistributions in binary form must reproduce the above copyright 13 1.3.2.2 skrll * notice, this list of conditions and the following disclaimer in the 14 1.3.2.2 skrll * documentation and/or other materials provided with the distribution. 15 1.3.2.2 skrll * 16 1.3.2.2 skrll * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 17 1.3.2.2 skrll * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 1.3.2.2 skrll * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 1.3.2.2 skrll * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 20 1.3.2.2 skrll * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 1.3.2.2 skrll * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 1.3.2.2 skrll * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 1.3.2.2 skrll * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 1.3.2.2 skrll * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 1.3.2.2 skrll * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 1.3.2.2 skrll * SUCH DAMAGE. 27 1.3.2.2 skrll */ 28 1.3.2.2 skrll 29 1.3.2.2 skrll #include <sys/cdefs.h> 30 1.3.2.2 skrll __KERNEL_RCSID(0, "$NetBSD: octeon_uart.c,v 1.3.2.2 2015/06/06 14:40:01 skrll Exp $"); 31 1.3.2.2 skrll 32 1.3.2.2 skrll #include "opt_octeon.h" 33 1.3.2.2 skrll 34 1.3.2.2 skrll #include <sys/param.h> 35 1.3.2.2 skrll #include <sys/systm.h> 36 1.3.2.2 skrll #include <sys/types.h> 37 1.3.2.2 skrll #include <sys/device.h> 38 1.3.2.2 skrll #include <sys/tty.h> 39 1.3.2.2 skrll 40 1.3.2.2 skrll #include <sys/bus.h> 41 1.3.2.2 skrll #include <sys/cpu.h> 42 1.3.2.2 skrll #include <machine/intr.h> 43 1.3.2.2 skrll 44 1.3.2.2 skrll #include <dev/ic/comreg.h> 45 1.3.2.2 skrll #include <dev/ic/comvar.h> 46 1.3.2.2 skrll 47 1.3.2.2 skrll #include <mips/cavium/include/iobusvar.h> 48 1.3.2.2 skrll #include <mips/cavium/dev/octeon_uartreg.h> 49 1.3.2.2 skrll #include <mips/cavium/dev/octeon_ciureg.h> 50 1.3.2.2 skrll 51 1.3.2.2 skrll struct octeon_uart_iobus_softc { 52 1.3.2.2 skrll struct com_softc sc_com; 53 1.3.2.2 skrll int sc_irq; 54 1.3.2.2 skrll void *sc_ih; 55 1.3.2.2 skrll }; 56 1.3.2.2 skrll 57 1.3.2.2 skrll static int octeon_uart_iobus_match(device_t, struct cfdata *, void *); 58 1.3.2.2 skrll static void octeon_uart_iobus_attach(device_t, device_t, void *); 59 1.3.2.2 skrll static int octeon_uart_com_enable(struct com_softc *); 60 1.3.2.2 skrll static void octeon_uart_com_disable(struct com_softc *); 61 1.3.2.2 skrll 62 1.3.2.2 skrll 63 1.3.2.2 skrll #define CN30XXUART_BUSYDETECT 0x7 64 1.3.2.2 skrll 65 1.3.2.2 skrll 66 1.3.2.2 skrll /* XXX */ 67 1.3.2.2 skrll int octeon_uart_com_cnattach(bus_space_tag_t, int, int); 68 1.3.2.2 skrll 69 1.3.2.2 skrll /* XXX */ 70 1.3.2.2 skrll const bus_addr_t octeon_uart_com_bases[] = { 71 1.3.2.2 skrll MIO_UART0_BASE, 72 1.3.2.2 skrll MIO_UART1_BASE 73 1.3.2.2 skrll }; 74 1.3.2.2 skrll const struct com_regs octeon_uart_com_regs = { 75 1.3.2.2 skrll .cr_nports = COM_NPORTS, 76 1.3.2.2 skrll .cr_map = { 77 1.3.2.2 skrll [COM_REG_RXDATA] = MIO_UART_RBR_OFFSET, 78 1.3.2.2 skrll [COM_REG_TXDATA] = MIO_UART_THR_OFFSET, 79 1.3.2.2 skrll [COM_REG_DLBL] = MIO_UART_DLL_OFFSET, 80 1.3.2.2 skrll [COM_REG_DLBH] = MIO_UART_DLH_OFFSET, 81 1.3.2.2 skrll [COM_REG_IER] = MIO_UART_IER_OFFSET, 82 1.3.2.2 skrll [COM_REG_IIR] = MIO_UART_IIR_OFFSET, 83 1.3.2.2 skrll [COM_REG_FIFO] = MIO_UART_FCR_OFFSET, 84 1.3.2.2 skrll [COM_REG_EFR] = 0, 85 1.3.2.2 skrll [COM_REG_LCR] = MIO_UART_LCR_OFFSET, 86 1.3.2.2 skrll [COM_REG_MCR] = MIO_UART_MCR_OFFSET, 87 1.3.2.2 skrll [COM_REG_LSR] = MIO_UART_LSR_OFFSET, 88 1.3.2.2 skrll [COM_REG_MSR] = MIO_UART_MSR_OFFSET, 89 1.3.2.2 skrll #if 0 /* XXX COM_TYPE_16750_NOERS */ 90 1.3.2.2 skrll [COM_REG_USR] = MIO_UART_USR_OFFSET, 91 1.3.2.2 skrll [COM_REG_SRR] = MIO_UART_SRR_OFFSET 92 1.3.2.2 skrll #endif 93 1.3.2.2 skrll } 94 1.3.2.2 skrll }; 95 1.3.2.2 skrll 96 1.3.2.2 skrll CFATTACH_DECL_NEW(octeon_uart_iobus, sizeof(struct octeon_uart_iobus_softc), 97 1.3.2.2 skrll octeon_uart_iobus_match, octeon_uart_iobus_attach, NULL, NULL); 98 1.3.2.2 skrll 99 1.3.2.2 skrll int 100 1.3.2.2 skrll octeon_uart_iobus_match(device_t parent, struct cfdata *cf, void *aux) 101 1.3.2.2 skrll { 102 1.3.2.2 skrll struct iobus_attach_args *aa = aux; 103 1.3.2.2 skrll int result = 0; 104 1.3.2.2 skrll 105 1.3.2.2 skrll if (strcmp(cf->cf_name, aa->aa_name) != 0) 106 1.3.2.2 skrll goto out; 107 1.3.2.2 skrll if (cf->cf_unit != aa->aa_unitno) 108 1.3.2.2 skrll goto out; 109 1.3.2.2 skrll result = 1; 110 1.3.2.2 skrll 111 1.3.2.2 skrll out: 112 1.3.2.2 skrll return result; 113 1.3.2.2 skrll } 114 1.3.2.2 skrll 115 1.3.2.2 skrll void 116 1.3.2.2 skrll octeon_uart_iobus_attach(device_t parent, device_t self, void *aux) 117 1.3.2.2 skrll { 118 1.3.2.2 skrll struct octeon_uart_iobus_softc *sc = device_private(self); 119 1.3.2.2 skrll struct com_softc *sc_com = &sc->sc_com; 120 1.3.2.2 skrll struct iobus_attach_args *aa = aux; 121 1.3.2.2 skrll int status; 122 1.3.2.2 skrll 123 1.3.2.2 skrll sc_com->sc_dev = self; 124 1.3.2.2 skrll sc_com->sc_regs = octeon_uart_com_regs; 125 1.3.2.2 skrll sc_com->sc_regs.cr_iot = aa->aa_bust; 126 1.3.2.2 skrll sc_com->sc_regs.cr_iobase = aa->aa_unit->addr; 127 1.3.2.2 skrll 128 1.3.2.2 skrll sc->sc_irq = aa->aa_unit->irq; 129 1.3.2.2 skrll 130 1.3.2.2 skrll status = bus_space_map( 131 1.3.2.2 skrll aa->aa_bust, 132 1.3.2.2 skrll aa->aa_unit->addr, 133 1.3.2.2 skrll COM_NPORTS, 134 1.3.2.2 skrll 0, 135 1.3.2.2 skrll &sc_com->sc_regs.cr_ioh); 136 1.3.2.2 skrll if (status != 0) { 137 1.3.2.2 skrll aprint_error(": can't map i/o space\n"); 138 1.3.2.2 skrll return; 139 1.3.2.2 skrll } 140 1.3.2.2 skrll 141 1.3.2.2 skrll sc_com->sc_type = COM_TYPE_16550_NOERS; 142 1.3.2.2 skrll sc_com->sc_frequency = curcpu()->ci_cpu_freq; 143 1.3.2.2 skrll sc_com->enable = octeon_uart_com_enable; 144 1.3.2.2 skrll sc_com->disable = octeon_uart_com_disable; 145 1.3.2.2 skrll 146 1.3.2.2 skrll octeon_uart_com_enable(sc_com); 147 1.3.2.2 skrll sc_com->enabled = 1; 148 1.3.2.2 skrll 149 1.3.2.2 skrll com_attach_subr(sc_com); 150 1.3.2.2 skrll 151 1.3.2.2 skrll /* XXX pass intr mask via _attach_args -- uebayasi */ 152 1.3.2.2 skrll sc->sc_ih = octeon_intr_establish(ffs64(CIU_INTX_SUM0_UART_0) - 1/* XXX */ + device_unit(self), 153 1.3.2.2 skrll IPL_SERIAL, comintr, sc_com); 154 1.3.2.2 skrll if (sc->sc_ih == NULL) 155 1.3.2.2 skrll panic("%s: can't establish interrupt\n", 156 1.3.2.2 skrll device_xname(self)); 157 1.3.2.2 skrll 158 1.3.2.2 skrll /* XXX disable if kgdb? */ 159 1.3.2.2 skrll } 160 1.3.2.2 skrll 161 1.3.2.2 skrll #if 0 162 1.3.2.2 skrll void 163 1.3.2.2 skrll octeon_uart_iobus_detach(device_t self, ...) 164 1.3.2.2 skrll { 165 1.3.2.2 skrll struct octeon_uart_iobus_softc *sc = (void *)self; 166 1.3.2.2 skrll 167 1.3.2.2 skrll octeon_intr_disestablish(sc->ih); 168 1.3.2.2 skrll } 169 1.3.2.2 skrll #endif 170 1.3.2.2 skrll 171 1.3.2.2 skrll int 172 1.3.2.2 skrll octeon_uart_com_enable(struct com_softc *sc_com) 173 1.3.2.2 skrll { 174 1.3.2.2 skrll struct com_regs *regsp = &sc_com->sc_regs; 175 1.3.2.2 skrll 176 1.3.2.2 skrll /* XXX Clear old busy detect interrupts */ 177 1.3.2.2 skrll bus_space_read_1(regsp->cr_iot, regsp->cr_ioh, 178 1.3.2.2 skrll MIO_UART_USR_OFFSET); 179 1.3.2.2 skrll 180 1.3.2.2 skrll return 0; 181 1.3.2.2 skrll } 182 1.3.2.2 skrll 183 1.3.2.2 skrll void 184 1.3.2.2 skrll octeon_uart_com_disable(struct com_softc *sc_com) 185 1.3.2.2 skrll { 186 1.3.2.2 skrll /* 187 1.3.2.2 skrll * XXX chip specific procedure 188 1.3.2.2 skrll */ 189 1.3.2.2 skrll } 190 1.3.2.2 skrll 191 1.3.2.2 skrll 192 1.3.2.2 skrll #ifndef CONMODE 193 1.3.2.2 skrll #define CONMODE ((TTYDEF_CFLAG & ~(CSIZE | CSTOPB | PARENB)) | CS8) /* 8N1 */ 194 1.3.2.2 skrll #endif 195 1.3.2.2 skrll 196 1.3.2.2 skrll int 197 1.3.2.2 skrll octeon_uart_com_cnattach(bus_space_tag_t bust, int portno, int speed) 198 1.3.2.2 skrll { 199 1.3.2.2 skrll struct com_regs regs; 200 1.3.2.2 skrll 201 1.3.2.2 skrll (void)memcpy(®s, &octeon_uart_com_regs, sizeof(regs)); 202 1.3.2.2 skrll regs.cr_iot = bust; 203 1.3.2.2 skrll regs.cr_iobase = octeon_uart_com_bases[portno]; 204 1.3.2.2 skrll 205 1.3.2.2 skrll return comcnattach1( 206 1.3.2.2 skrll ®s, 207 1.3.2.2 skrll speed, 208 1.3.2.2 skrll curcpu()->ci_cpu_freq, 209 1.3.2.2 skrll COM_TYPE_16550_NOERS, 210 1.3.2.2 skrll CONMODE); 211 1.3.2.2 skrll } 212
Indexes created Tue Sep 30 20:09:53 GMT 2025