octeon_uart.c revision 1.5
1 /* $NetBSD: octeon_uart.c,v 1.5 2020/05/31 14:05:21 simonb Exp $ */ 2 3 /* 4 * Copyright (c) 2007 Internet Initiative Japan, Inc. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 __KERNEL_RCSID(0, "$NetBSD: octeon_uart.c,v 1.5 2020/05/31 14:05:21 simonb Exp $"); 31 32 #include "opt_octeon.h" 33 34 #include <sys/param.h> 35 #include <sys/systm.h> 36 #include <sys/types.h> 37 #include <sys/device.h> 38 #include <sys/tty.h> 39 40 #include <sys/bus.h> 41 #include <sys/cpu.h> 42 #include <machine/intr.h> 43 44 #include <dev/ic/comreg.h> 45 #include <dev/ic/comvar.h> 46 47 #include <mips/cavium/include/iobusvar.h> 48 #include <mips/cavium/dev/octeon_uartreg.h> 49 #include <mips/cavium/dev/octeon_ciureg.h> 50 51 struct octuart_iobus_softc { 52 struct com_softc sc_com; 53 int sc_irq; 54 void *sc_ih; 55 }; 56 57 static int octuart_iobus_match(device_t, struct cfdata *, void *); 58 static void octuart_iobus_attach(device_t, device_t, void *); 59 static int octuart_com_enable(struct com_softc *); 60 static void octuart_com_disable(struct com_softc *); 61 62 63 #define CN30XXUART_BUSYDETECT 0x7 64 65 66 /* XXX */ 67 int octuart_com_cnattach(bus_space_tag_t, int, int); 68 69 /* XXX */ 70 const bus_addr_t octuart_com_bases[] = { 71 MIO_UART0_BASE, 72 MIO_UART1_BASE 73 }; 74 const struct com_regs octuart_com_regs = { 75 .cr_nports = COM_NPORTS, 76 .cr_map = { 77 [COM_REG_RXDATA] = MIO_UART_RBR_OFFSET, 78 [COM_REG_TXDATA] = MIO_UART_THR_OFFSET, 79 [COM_REG_DLBL] = MIO_UART_DLL_OFFSET, 80 [COM_REG_DLBH] = MIO_UART_DLH_OFFSET, 81 [COM_REG_IER] = MIO_UART_IER_OFFSET, 82 [COM_REG_IIR] = MIO_UART_IIR_OFFSET, 83 [COM_REG_FIFO] = MIO_UART_FCR_OFFSET, 84 [COM_REG_EFR] = 0, 85 [COM_REG_LCR] = MIO_UART_LCR_OFFSET, 86 [COM_REG_MCR] = MIO_UART_MCR_OFFSET, 87 [COM_REG_LSR] = MIO_UART_LSR_OFFSET, 88 [COM_REG_MSR] = MIO_UART_MSR_OFFSET, 89 #if 0 /* XXX COM_TYPE_16750_NOERS */ 90 [COM_REG_USR] = MIO_UART_USR_OFFSET, 91 [COM_REG_SRR] = MIO_UART_SRR_OFFSET 92 #endif 93 } 94 }; 95 96 CFATTACH_DECL_NEW(com_iobus, sizeof(struct octuart_iobus_softc), 97 octuart_iobus_match, octuart_iobus_attach, NULL, NULL); 98 99 int 100 octuart_iobus_match(device_t parent, struct cfdata *cf, void *aux) 101 { 102 struct iobus_attach_args *aa = aux; 103 int result = 0; 104 105 if (strcmp(cf->cf_name, aa->aa_name) != 0) 106 goto out; 107 if (cf->cf_unit != aa->aa_unitno) 108 goto out; 109 result = 1; 110 111 out: 112 return result; 113 } 114 115 void 116 octuart_iobus_attach(device_t parent, device_t self, void *aux) 117 { 118 struct octuart_iobus_softc *sc = device_private(self); 119 struct com_softc *sc_com = &sc->sc_com; 120 struct iobus_attach_args *aa = aux; 121 int status; 122 123 sc_com->sc_dev = self; 124 sc_com->sc_regs = octuart_com_regs; 125 sc_com->sc_regs.cr_iot = aa->aa_bust; 126 sc_com->sc_regs.cr_iobase = aa->aa_unit->addr; 127 128 sc->sc_irq = aa->aa_unit->irq; 129 130 status = bus_space_map( 131 aa->aa_bust, 132 aa->aa_unit->addr, 133 COM_NPORTS, 134 0, 135 &sc_com->sc_regs.cr_ioh); 136 if (status != 0) { 137 aprint_error(": can't map i/o space\n"); 138 return; 139 } 140 141 sc_com->sc_type = COM_TYPE_16550_NOERS; 142 sc_com->sc_frequency = curcpu()->ci_cpu_freq; 143 sc_com->enable = octuart_com_enable; 144 sc_com->disable = octuart_com_disable; 145 146 octuart_com_enable(sc_com); 147 sc_com->enabled = 1; 148 149 com_attach_subr(sc_com); 150 151 /* XXX pass intr mask via _attach_args -- uebayasi */ 152 sc->sc_ih = octeon_intr_establish(ffs64(CIU_INTX_SUM0_UART_0) - 1/* XXX */ + device_unit(self), 153 IPL_SERIAL, comintr, sc_com); 154 if (sc->sc_ih == NULL) 155 panic("%s: can't establish interrupt\n", 156 device_xname(self)); 157 158 /* XXX disable if kgdb? */ 159 } 160 161 #if 0 162 void 163 octuart_iobus_detach(device_t self, ...) 164 { 165 struct octuart_iobus_softc *sc = (void *)self; 166 167 octeon_intr_disestablish(sc->ih); 168 } 169 #endif 170 171 int 172 octuart_com_enable(struct com_softc *sc_com) 173 { 174 struct com_regs *regsp = &sc_com->sc_regs; 175 176 /* XXX Clear old busy detect interrupts */ 177 bus_space_read_1(regsp->cr_iot, regsp->cr_ioh, 178 MIO_UART_USR_OFFSET); 179 180 return 0; 181 } 182 183 void 184 octuart_com_disable(struct com_softc *sc_com) 185 { 186 /* 187 * XXX chip specific procedure 188 */ 189 } 190 191 192 #ifndef CONMODE 193 #define CONMODE ((TTYDEF_CFLAG & ~(CSIZE | CSTOPB | PARENB)) | CS8) /* 8N1 */ 194 #endif 195 196 int 197 octuart_com_cnattach(bus_space_tag_t bust, int portno, int speed) 198 { 199 struct com_regs regs; 200 201 (void)memcpy(®s, &octuart_com_regs, sizeof(regs)); 202 regs.cr_iot = bust; 203 regs.cr_iobase = octuart_com_bases[portno]; 204 205 return comcnattach1( 206 ®s, 207 speed, 208 curcpu()->ci_cpu_freq, 209 COM_TYPE_16550_NOERS, 210 CONMODE); 211 } 212
Indexes created Tue Sep 23 22:09:46 GMT 2025