octeon_usbnreg.h revision 1.1
1 /* $NetBSD: octeon_usbnreg.h,v 1.1 2015/04/29 08:32:01 hikaru Exp $ */ 2 3 /* 4 * Copyright (c) 2007 Internet Initiative Japan, Inc. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 /* 30 * USBN Registers 31 */ 32 33 #ifndef _OCTEON_USBNREG_H_ 34 #define _OCTEON_USBNREG_H_ 35 36 /* ---- register addresses */ 37 38 #define USBN_INT_SUM 0x0001180068000000ULL 39 #define USBN_INT_ENB 0x0001180068000008ULL 40 #define USBN_CLK_CTL 0x0001180068000010ULL 41 #define USBN_USBP_CTL_STATUS 0x0001180068000018ULL 42 #define USBN_BIST_STATUS 0x00011800680007f8ULL 43 #define USBN_CTL_STATUS 0x00016F0000000800ULL 44 #define USBN_DMA_TEST 0x00016F0000000808ULL 45 #define USBN_DMA0_INB_CHN0 0x00016F0000000818ULL 46 #define USBN_DMA0_INB_CHN1 0x00016F0000000820ULL 47 #define USBN_DMA0_INB_CHN2 0x00016F0000000828ULL 48 #define USBN_DMA0_INB_CHN3 0x00016F0000000830ULL 49 #define USBN_DMA0_INB_CHN4 0x00016F0000000838ULL 50 #define USBN_DMA0_INB_CHN5 0x00016F0000000840ULL 51 #define USBN_DMA0_INB_CHN6 0x00016F0000000848ULL 52 #define USBN_DMA0_INB_CHN7 0x00016F0000000850ULL 53 #define USBN_DMA0_OUTB_CHN0 0x00016F0000000858ULL 54 #define USBN_DMA0_OUTB_CHN1 0x00016F0000000860ULL 55 #define USBN_DMA0_OUTB_CHN2 0x00016F0000000868ULL 56 #define USBN_DMA0_OUTB_CHN3 0x00016F0000000870ULL 57 #define USBN_DMA0_OUTB_CHN4 0x00016F0000000878ULL 58 #define USBN_DMA0_OUTB_CHN5 0x00016F0000000880ULL 59 #define USBN_DMA0_OUTB_CHN6 0x00016F0000000888ULL 60 #define USBN_DMA0_OUTB_CHN7 0x00016F0000000890ULL 61 62 /* ---- register bits */ 63 64 /* for USBN_INT_SUM and USBN_INT_ENB */ 65 #define USBN_INT_XXX_63_38 UINT64_C(0xffffffc000000000) 66 #define USBN_INT_ND4O_DPF UINT64_C(0x0000002000000000) 67 #define USBN_INT_ND4O_DPE UINT64_C(0x0000001000000000) 68 #define USBN_INT_ND4O_RPF UINT64_C(0x0000000800000000) 69 #define USBN_INT_ND4O_RPE UINT64_C(0x0000000400000000) 70 #define USBN_INT_LTL_F_PF UINT64_C(0x0000000200000000) 71 #define USBN_INT_LTL_F_PE UINT64_C(0x0000000100000000) 72 #define USBN_INT_U2N_C_PE UINT64_C(0x0000000080000000) 73 #define USBN_INT_U2N_C_PF UINT64_C(0x0000000040000000) 74 #define USBN_INT_U2N_D_PF UINT64_C(0x0000000020000000) 75 #define USBN_INT_U2N_D_PE UINT64_C(0x0000000010000000) 76 #define USBN_INT_N2U_PE UINT64_C(0x0000000008000000) 77 #define USBN_INT_N2U_PF UINT64_C(0x0000000004000000) 78 #define USBN_INT_UOD_PF UINT64_C(0x0000000002000000) 79 #define USBN_INT_UOD_PE UINT64_C(0x0000000001000000) 80 #define USBN_INT_RQ_Q3_E UINT64_C(0x0000000000800000) 81 #define USBN_INT_RQ_Q3_F UINT64_C(0x0000000000400000) 82 #define USBN_INT_RQ_Q2_E UINT64_C(0x0000000000200000) 83 #define USBN_INT_RQ_Q2_F UINT64_C(0x0000000000100000) 84 #define USBN_INT_RG_FI_F UINT64_C(0x0000000000080000) 85 #define USBN_INT_RG_FI_E UINT64_C(0x0000000000040000) 86 #define USBN_INT_LT_FI_F UINT64_C(0x0000000000020000) 87 #define USBN_INT_LT_FI_E UINT64_C(0x0000000000010000) 88 #define USBN_INT_L2C_A_F UINT64_C(0x0000000000008000) 89 #define USBN_INT_L2C_S_E UINT64_C(0x0000000000004000) 90 #define USBN_INT_DCRED_F UINT64_C(0x0000000000002000) 91 #define USBN_INT_DCRED_E UINT64_C(0x0000000000001000) 92 #define USBN_INT_LT_PU_F UINT64_C(0x0000000000000800) 93 #define USBN_INT_LT_PO_E UINT64_C(0x0000000000000400) 94 #define USBN_INT_NT_PU_F UINT64_C(0x0000000000000200) 95 #define USBN_INT_NT_PO_E UINT64_C(0x0000000000000100) 96 #define USBN_INT_PT_PU_F UINT64_C(0x0000000000000080) 97 #define USBN_INT_PT_PO_E UINT64_C(0x0000000000000040) 98 #define USBN_INT_LR_PU_F UINT64_C(0x0000000000000020) 99 #define USBN_INT_LR_PO_E UINT64_C(0x0000000000000010) 100 #define USBN_INT_NR_PU_F UINT64_C(0x0000000000000008) 101 #define USBN_INT_NR_PO_E UINT64_C(0x0000000000000004) 102 #define USBN_INT_PR_PU_F UINT64_C(0x0000000000000002) 103 #define USBN_INT_PR_PO_E UINT64_C(0x0000000000000001) 104 105 #define USBN_CLK_CTL_XXX_63_18 UINT64_C(0xfffffffffffc0000) 106 #define USBN_CLK_CTL_HCLK_RST UINT64_C(0x0000000000020000) 107 #define USBN_CLK_CTL_P_X_ON UINT64_C(0x0000000000010000) 108 #define USBN_CLK_CTL_P_RCLK UINT64_C(0x0000000000008000) 109 #define USBN_CLK_CTL_P_XENBN UINT64_C(0x0000000000004000) 110 #define USBN_CLK_CTL_P_COM_ON UINT64_C(0x0000000000002000) 111 #define USBN_CLK_CTL_P_C_SEL UINT64_C(0x0000000000001800) 112 #define SET_USBN_CLK_CTL_P_C_SEL(v) (((v)<<11) & USBN_CLK_CTL_P_C_SEL) 113 #define GET_USBN_CLK_CTL_P_C_SEL(v) (((v) & USBN_CLK_CTL_P_C_SEL) >> 11) 114 #define USBN_CLK_CTL_CDIV_BYP UINT64_C(0x0000000000000400) 115 #define USBN_CLK_CTL_SD_MODE UINT64_C(0x0000000000000300) 116 #define USBN_CLK_CTL_S_BIST UINT64_C(0x0000000000000080) 117 #define USBN_CLK_CTL_POR UINT64_C(0x0000000000000040) 118 #define USBN_CLK_CTL_ENABLE UINT64_C(0x0000000000000020) 119 #define USBN_CLK_CTL_PRST UINT64_C(0x0000000000000010) 120 #define USBN_CLK_CTL_HRST UINT64_C(0x0000000000000008) 121 #define USBN_CLK_CTL_DIVIDE UINT64_C(0x0000000000000007) 122 #define SET_USBN_CLK_CTL_DIVIDE(v) (((v)<<0) & USBN_CLK_CTL_DIVIDE) 123 #define GET_USBN_CLK_CTL_DIVIDE(v) (((v) & USBN_CLK_CTL_DIVIDE) >> 0) 124 /* CN50xx extension */ 125 #define USBN_CLK_CTL_DIVIDE2 UINT64_C(0x00000000000c0000) 126 #define SET_USBN_CLK_CTL_DIVIDE2(v) (((v)<<18) & USBN_CLK_CTL_DIVIDE2) 127 #define GET_USBN_CLK_CTL_DIVIDE2(v) (((v) & USBN_CLK_CTL_DIVIDE2) >> 18) 128 #define USBN_CLK_CTL_P_RTYPE UINT64_C(0x000000000000c000) 129 #define SET_USBN_CLK_CTL_P_RTYPE(v) (((v)<<14) & USBN_CLK_CTL_P_RTYPE) 130 #define GET_USBN_CLK_CTL_P_RTYPE(v) (((v) & USBN_CLK_CTL_P_RTYPE) >> 14) 131 132 #define USBN_USBP_CTL_STATUS_XXX_63_38 UINT64_C(0xffffffc000000000) 133 #define USBN_USBP_CTL_STATUS_BIST_DONE UINT64_C(0x0000002000000000) 134 #define USBN_USBP_CTL_STATUS_BIST_ERR UINT64_C(0x0000001000000000) 135 #define USBN_USBP_CTL_STATUS_TDATA_OUT UINT64_C(0x0000000f00000000) 136 #define USBN_USBP_CTL_STATUS_SPARES UINT64_C(0x00000000e0000000) 137 #define USBN_USBP_CTL_STATUS_USBC_END UINT64_C(0x0000000010000000) 138 #define USBN_USBP_CTL_STATUS_USBP_BIST UINT64_C(0x0000000008000000) 139 #define USBN_USBP_CTL_STATUS_TCLK UINT64_C(0x0000000004000000) 140 #define USBN_USBP_CTL_STATUS_DP_PULLD UINT64_C(0x0000000002000000) 141 #define USBN_USBP_CTL_STATUS_DM_PULLD UINT64_C(0x0000000001000000) 142 #define USBN_USBP_CTL_STATUS_HST_MODE UINT64_C(0x0000000000800000) 143 #define USBN_USBP_CTL_STATUS_TUNING UINT64_C(0x0000000000780000) 144 #define USBN_USBP_CTL_STATUS_TX_BS_ENH UINT64_C(0x0000000000040000) 145 #define USBN_USBP_CTL_STATUS_TX_BS_EN UINT64_C(0x0000000000020000) 146 #define USBN_USBP_CTL_STATUS_LOOP_ENB UINT64_C(0x0000000000010000) 147 #define USBN_USBP_CTL_STATUS_VTEST_ENB UINT64_C(0x0000000000008000) 148 #define USBN_USBP_CTL_STATUS_BIST_ENB UINT64_C(0x0000000000004000) 149 #define USBN_USBP_CTL_STATUS_TDATA_SEL UINT64_C(0x0000000000002000) 150 #define USBN_USBP_CTL_STATUS_TADDR_IN UINT64_C(0x0000000000001e00) 151 #define USBN_USBP_CTL_STATUS_TDATA_IN UINT64_C(0x00000000000001fe) 152 #define USBN_USBP_CTL_STATUS_ATE_RESET UINT64_C(0x0000000000000001) 153 /* CN50xx extension */ 154 #define USBN_USBP_CTL_STATUS_TXRISETUNE UINT64_C(0x8000000000000000) 155 #define USBN_USBP_CTL_STATUS_TXVREFTUNE UINT64_C(0x7800000000000000) 156 #define USBN_USBP_CTL_STATUS_TXFSLSTUNE UINT64_C(0x0780000000000000) 157 #define USBN_USBP_CTL_STATUS_TXHSXVTUNE UINT64_C(0x0060000000000000) 158 #define USBN_USBP_CTL_STATUS_SQRXTUNE UINT64_C(0x001c000000000000) 159 #define USBN_USBP_CTL_STATUS_COMPDISTUNE UINT64_C(0x0003800000000000) 160 #define USBN_USBP_CTL_STATUS_OTGTUNE UINT64_C(0x0000700000000000) 161 #define USBN_USBP_CTL_STATUS_OTGDISABLE UINT64_C(0x0000080000000000) 162 #define USBN_USBP_CTL_STATUS_PORTRESET UINT64_C(0x0000040000000000) 163 #define USBN_USBP_CTL_STATUS_DRVVBUS UINT64_C(0x0000020000000000) 164 #define USBN_USBP_CTL_STATUS_LSBIST UINT64_C(0x0000010000000000) 165 #define USBN_USBP_CTL_STATUS_FSBIST UINT64_C(0x0000008000000000) 166 #define USBN_USBP_CTL_STATUS_HSBIST UINT64_C(0x0000004000000000) 167 168 #define USBN_BIST_STATUS_XXX_63_3 UINT64_C(0xfffffffffffffff8) 169 #define USBN_BIST_STATUS_USBC_BIS UINT64_C(0x0000000000000004) 170 #define USBN_BIST_STATUS_NIF_BIS UINT64_C(0x0000000000000002) 171 #define USBN_BIST_STATUS_NOF_BIS UINT64_C(0x0000000000000001) 172 /* CN50xx extension */ 173 #define USBN_BIST_STATUS_U2NC_BIS UINT64_C(0x0000000000000040) 174 #define USBN_BIST_STATUS_U2NF_BIS UINT64_C(0x0000000000000020) 175 #define USBN_BIST_STATUS_E2HC_BIS UINT64_C(0x0000000000000010) 176 #define USBN_BIST_STATUS_N2UF_BIS UINT64_C(0x0000000000000008) 177 178 #define USBN_CTL_STATUS_XXX_63_6 UINT64_C(0xffffffffffffffc0) 179 #define USBN_CTL_STATUS_DMA_0PAG UINT64_C(0x0000000000000020) 180 #define USBN_CTL_STATUS_DMA_STT UINT64_C(0x0000000000000010) 181 #define USBN_CTL_STATUS_DMA_TEST UINT64_C(0x0000000000000008) 182 #define USBN_CTL_STATUS_INV_A2 UINT64_C(0x0000000000000004) 183 #define USBN_CTL_STATUS_L2C_EMOD UINT64_C(0x0000000000000003) 184 185 #define USBN_DMA_TEST_XXX_63_40 UINT64_C(0xffffff0000000000) 186 #define USBN_DMA_TEST_DONE UINT64_C(0x0000008000000000) 187 #define USBN_DMA_TEST_REQ UINT64_C(0x0000004000000000) 188 #define USBN_DMA_TEST_F_ADDR UINT64_C(0x0000003ffff00000) 189 #define USBN_DMA_TEST_COUNT UINT64_C(0x00000000000ffe00) 190 #define USBN_DMA_TEST_CHANNEL UINT64_C(0x00000000000001f0) 191 #define USBN_DMA_TEST_BURST UINT64_C(0x000000000000000f) 192 193 /* for USBN_DMA0_INB_CHN(0..7) */ 194 #define USBN_DMA0_INB_CHNX_XXX_63_36 UINT64_C(0xfffffff000000000) 195 #define USBN_DMA0_INB_CHNX_ADDR UINT64_C(0x0000000fffffffff) 196 197 /* for USBN_DMA0_OUTB_CHN(0..7) */ 198 #define USBN_DMA0_OUTB_CHNX_XXX_63_36 UINT64_C(0xfffffff000000000) 199 #define USBN_DMA0_OUTB_CHNX_ADDR UINT64_C(0x0000000fffffffff) 200 201 /* ---- snprintb */ 202 203 #define USBN_INT_BITS \ 204 "\177" /* new format */ \ 205 "\020" /* hex display */ \ 206 "\020" /* %016x format */ \ 207 "b\x25" "ND4O_DPF\0" \ 208 "b\x24" "ND4O_DPE\0" \ 209 "b\x23" "ND4O_RPF\0" \ 210 "b\x22" "ND4O_RPE\0" \ 211 "b\x21" "LTL_F_PF\0" \ 212 "b\x20" "LTL_F_PE\0" \ 213 "b\x1f" "U2N_C_PE\0" \ 214 "b\x1e" "U2N_C_PF\0" \ 215 "b\x1d" "U2N_D_PF\0" \ 216 "b\x1c" "U2N_D_PE\0" \ 217 "b\x1b" "N2U_PE\0" \ 218 "b\x1a" "N2U_PF\0" \ 219 "b\x19" "UOD_PF\0" \ 220 "b\x18" "UOD_PE\0" \ 221 "b\x17" "RQ_Q3_E\0" \ 222 "b\x16" "RQ_Q3_F\0" \ 223 "b\x15" "RQ_Q2_E\0" \ 224 "b\x14" "RQ_Q2_F\0" \ 225 "b\x13" "RG_FI_F\0" \ 226 "b\x12" "RG_FI_E\0" \ 227 "b\x11" "LT_FI_F\0" \ 228 "b\x10" "LT_FI_E\0" \ 229 "b\x0f" "L2C_A_F\0" \ 230 "b\x0e" "L2C_S_E\0" \ 231 "b\x0d" "DCRED_F\0" \ 232 "b\x0c" "DCRED_E\0" \ 233 "b\x0b" "LT_PU_F\0" \ 234 "b\x0a" "LT_PO_E\0" \ 235 "b\x09" "NT_PU_F\0" \ 236 "b\x08" "NT_PO_E\0" \ 237 "b\x07" "PT_PU_F\0" \ 238 "b\x06" "PT_PO_E\0" \ 239 "b\x05" "LR_PU_F\0" \ 240 "b\x04" "LR_PO_E\0" \ 241 "b\x03" "NR_PU_F\0" \ 242 "b\x02" "NR_PO_E\0" \ 243 "b\x01" "PR_PU_F\0" \ 244 "b\x00" "PR_PO_E\0" 245 246 #define USBN_CLK_CTL_BITS \ 247 "\177" /* new format */ \ 248 "\020" /* hex display */ \ 249 "\020" /* %016x format */ \ 250 "f\x12\x02" "DIVIDE2\0" \ 251 "b\x11" "HCLK_RST\0" \ 252 "b\x10" "P_X_ON\0" \ 253 "b\x0f" "P_RCLK\0" \ 254 "f\x0e\x02" "P_RTYPE\0" \ 255 "b\x0e" "P_XENBN\0" \ 256 "b\x0d" "P_COM_ON\0" \ 257 "f\x0b\x02" "P_C_SEL\0" \ 258 "b\x0a" "CDIV_BYP\0" \ 259 "f\x08\x02" "SD_MODE\0" \ 260 "b\x07" "S_BIST\0" \ 261 "b\x06" "POR\0" \ 262 "b\x05" "ENABLE\0" \ 263 "b\x04" "PRST\0" \ 264 "b\x03" "HRST\0" \ 265 "f\x00\x03" "DIVIDE\0" 266 267 #define USBN_USBP_CTL_STATUS_BITS \ 268 "\177" /* new format */ \ 269 "\020" /* hex display */ \ 270 "\020" /* %016x format */ \ 271 "b\x3f" "TXRISETUNE\0" \ 272 "f\x3b\x04" "TXVREFTUNE\0" \ 273 "f\x37\x04" "TXFSLSTUNE\0" \ 274 "f\x35\x02" "TXHSXVTUNE\0" \ 275 "f\x32\x03" "SQRXTUNE\0" \ 276 "f\x2f\x03" "COMPDISTUNE\0" \ 277 "f\x2c\x03" "OTGTUNE\0" \ 278 "b\x2b" "OTGDISABLE\0" \ 279 "b\x2a" "PORTRESET\0" \ 280 "b\x29" "DRVVBUS\0" \ 281 "b\x28" "LSBIST\0" \ 282 "b\x27" "FSBIST\0" \ 283 "b\x26" "HSBIST\0" \ 284 "b\x25" "BIST_DONE\0" \ 285 "b\x24" "BIST_ERR\0" \ 286 "f\x20\x04" "TDATA_OUT\0" \ 287 "f\x1d\x03" "SPARES\0" \ 288 "b\x1c" "USBC_END\0" \ 289 "b\x1b" "USBP_BIST\0" \ 290 "b\x1a" "TCLK\0" \ 291 "b\x19" "DP_PULLD\0" \ 292 "b\x18" "DM_PULLD\0" \ 293 "b\x17" "HST_MODE\0" \ 294 "f\x13\x04" "TUNING\0" \ 295 "b\x12" "TX_BS_ENH\0" \ 296 "b\x11" "TX_BS_EN\0" \ 297 "b\x10" "LOOP_ENB\0" \ 298 "b\x0f" "VTEST_ENB\0" \ 299 "b\x0e" "BIST_ENB\0" \ 300 "b\x0d" "TDATA_SEL\0" \ 301 "f\x09\x04" "TADDR_IN\0" \ 302 "f\x01\x08" "TDATA_IN\0" \ 303 "b\x00" "ATE_RESET\0" 304 305 #define USBN_BIST_STATUS_BITS \ 306 "\177" /* new format */ \ 307 "\020" /* hex display */ \ 308 "\020" /* %016x format */ \ 309 "b\x06" "U2NC_BIS\0" \ 310 "b\x05" "U2NF_BIS\0" \ 311 "b\x04" "E2HC_BIS\0" \ 312 "b\x03" "N2UF_BIS\0" \ 313 "b\x02" "USBC_BIS\0" \ 314 "b\x01" "NIF_BIS\0" \ 315 "b\x00" "NOF_BIS\0" 316 317 #define USBN_CTL_STATUS_BITS \ 318 "\177" /* new format */ \ 319 "\020" /* hex display */ \ 320 "\020" /* %016x format */ \ 321 "b\x05" "DMA_0PAG\0" \ 322 "b\x04" "DMA_STT\0" \ 323 "b\x03" "DMA_TEST\0" \ 324 "b\x02" "INV_A2\0" \ 325 "f\x00\x02" "L2C_EMOD\0" 326 327 #define USBN_DMA_TEST_BITS \ 328 "\177" /* new format */ \ 329 "\020" /* hex display */ \ 330 "\020" /* %016x format */ \ 331 "b\x27" "DONE\0" \ 332 "b\x26" "REQ\0" \ 333 "f\x14\x12" "F_ADDR\0" \ 334 "f\x09\x0b" "COUNT\0" \ 335 "f\x04\x05" "CHANNEL\0" \ 336 "f\x00\x04" "BURST\0" 337 338 /* ---- bus_space */ 339 340 #define USBN_NUNITS 1 341 #define USBN_BASE 0x0001180068000000ULL 342 #define USBN_SIZE 0x800 343 344 #define USBN_INT_SUM_OFFSET 0x00000000 345 #define USBN_INT_ENB_OFFSET 0x00000008 346 #define USBN_CLK_CTL_OFFSET 0x00000010 347 #define USBN_USBP_CTL_STATUS_OFFSET 0x00000018 348 #define USBN_BIST_STATUS_OFFSET 0x000007f8 349 350 351 /* ---- bus_space 2 */ 352 353 #define USBN_2_NUNITS 1 354 #define USBN_2_BASE 0x00016F0000000800ULL 355 #define USBN_2_SIZE 0x098 356 357 #define USBN_CTL_STATUS_OFFSET 0x00000000 358 #define USBN_DMA_TEST_OFFSET 0x00000008 359 #define USBN_DMA0_INB_CHN0_OFFSET 0x00000018 360 #define USBN_DMA0_INB_CHN1_OFFSET 0x00000020 361 #define USBN_DMA0_INB_CHN2_OFFSET 0x00000028 362 #define USBN_DMA0_INB_CHN3_OFFSET 0x00000030 363 #define USBN_DMA0_INB_CHN4_OFFSET 0x00000038 364 #define USBN_DMA0_INB_CHN5_OFFSET 0x00000040 365 #define USBN_DMA0_INB_CHN6_OFFSET 0x00000048 366 #define USBN_DMA0_INB_CHN7_OFFSET 0x00000050 367 #define USBN_DMA0_OUTB_CHN0_OFFSET 0x00000058 368 #define USBN_DMA0_OUTB_CHN1_OFFSET 0x00000060 369 #define USBN_DMA0_OUTB_CHN2_OFFSET 0x00000068 370 #define USBN_DMA0_OUTB_CHN3_OFFSET 0x00000070 371 #define USBN_DMA0_OUTB_CHN4_OFFSET 0x00000078 372 #define USBN_DMA0_OUTB_CHN5_OFFSET 0x00000080 373 #define USBN_DMA0_OUTB_CHN6_OFFSET 0x00000088 374 #define USBN_DMA0_OUTB_CHN7_OFFSET 0x00000090 375 376 #endif /* _OCTEON_USBNREG_H_ */ 377
Indexes created Mon Sep 29 21:09:56 GMT 2025