octeon_usbnreg.h revision 1.3
1 /* $NetBSD: octeon_usbnreg.h,v 1.3 2020/06/23 05:14:18 simonb Exp $ */ 2 3 /* 4 * Copyright (c) 2007 Internet Initiative Japan, Inc. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 /* 30 * USBN Registers 31 */ 32 33 #ifndef _OCTEON_USBNREG_H_ 34 #define _OCTEON_USBNREG_H_ 35 36 /* ---- register addresses */ 37 38 #define USBN_INT_SUM 0x0001180068000000ULL 39 #define USBN_INT_ENB 0x0001180068000008ULL 40 #define USBN_CLK_CTL 0x0001180068000010ULL 41 #define USBN_USBP_CTL_STATUS 0x0001180068000018ULL 42 #define USBN_BIST_STATUS 0x00011800680007f8ULL 43 #define USBN_CTL_STATUS 0x00016F0000000800ULL 44 #define USBN_DMA_TEST 0x00016F0000000808ULL 45 #define USBN_DMA0_INB_CHN0 0x00016F0000000818ULL 46 #define USBN_DMA0_INB_CHN1 0x00016F0000000820ULL 47 #define USBN_DMA0_INB_CHN2 0x00016F0000000828ULL 48 #define USBN_DMA0_INB_CHN3 0x00016F0000000830ULL 49 #define USBN_DMA0_INB_CHN4 0x00016F0000000838ULL 50 #define USBN_DMA0_INB_CHN5 0x00016F0000000840ULL 51 #define USBN_DMA0_INB_CHN6 0x00016F0000000848ULL 52 #define USBN_DMA0_INB_CHN7 0x00016F0000000850ULL 53 #define USBN_DMA0_OUTB_CHN0 0x00016F0000000858ULL 54 #define USBN_DMA0_OUTB_CHN1 0x00016F0000000860ULL 55 #define USBN_DMA0_OUTB_CHN2 0x00016F0000000868ULL 56 #define USBN_DMA0_OUTB_CHN3 0x00016F0000000870ULL 57 #define USBN_DMA0_OUTB_CHN4 0x00016F0000000878ULL 58 #define USBN_DMA0_OUTB_CHN5 0x00016F0000000880ULL 59 #define USBN_DMA0_OUTB_CHN6 0x00016F0000000888ULL 60 #define USBN_DMA0_OUTB_CHN7 0x00016F0000000890ULL 61 62 /* ---- register bits */ 63 64 /* for USBN_INT_SUM and USBN_INT_ENB */ 65 #define USBN_INT_XXX_63_38 UINT64_C(0xffffffc000000000) 66 #define USBN_INT_ND4O_DPF UINT64_C(0x0000002000000000) 67 #define USBN_INT_ND4O_DPE UINT64_C(0x0000001000000000) 68 #define USBN_INT_ND4O_RPF UINT64_C(0x0000000800000000) 69 #define USBN_INT_ND4O_RPE UINT64_C(0x0000000400000000) 70 #define USBN_INT_LTL_F_PF UINT64_C(0x0000000200000000) 71 #define USBN_INT_LTL_F_PE UINT64_C(0x0000000100000000) 72 #define USBN_INT_U2N_C_PE UINT64_C(0x0000000080000000) 73 #define USBN_INT_U2N_C_PF UINT64_C(0x0000000040000000) 74 #define USBN_INT_U2N_D_PF UINT64_C(0x0000000020000000) 75 #define USBN_INT_U2N_D_PE UINT64_C(0x0000000010000000) 76 #define USBN_INT_N2U_PE UINT64_C(0x0000000008000000) 77 #define USBN_INT_N2U_PF UINT64_C(0x0000000004000000) 78 #define USBN_INT_UOD_PF UINT64_C(0x0000000002000000) 79 #define USBN_INT_UOD_PE UINT64_C(0x0000000001000000) 80 #define USBN_INT_RQ_Q3_E UINT64_C(0x0000000000800000) 81 #define USBN_INT_RQ_Q3_F UINT64_C(0x0000000000400000) 82 #define USBN_INT_RQ_Q2_E UINT64_C(0x0000000000200000) 83 #define USBN_INT_RQ_Q2_F UINT64_C(0x0000000000100000) 84 #define USBN_INT_RG_FI_F UINT64_C(0x0000000000080000) 85 #define USBN_INT_RG_FI_E UINT64_C(0x0000000000040000) 86 #define USBN_INT_LT_FI_F UINT64_C(0x0000000000020000) 87 #define USBN_INT_LT_FI_E UINT64_C(0x0000000000010000) 88 #define USBN_INT_L2C_A_F UINT64_C(0x0000000000008000) 89 #define USBN_INT_L2C_S_E UINT64_C(0x0000000000004000) 90 #define USBN_INT_DCRED_F UINT64_C(0x0000000000002000) 91 #define USBN_INT_DCRED_E UINT64_C(0x0000000000001000) 92 #define USBN_INT_LT_PU_F UINT64_C(0x0000000000000800) 93 #define USBN_INT_LT_PO_E UINT64_C(0x0000000000000400) 94 #define USBN_INT_NT_PU_F UINT64_C(0x0000000000000200) 95 #define USBN_INT_NT_PO_E UINT64_C(0x0000000000000100) 96 #define USBN_INT_PT_PU_F UINT64_C(0x0000000000000080) 97 #define USBN_INT_PT_PO_E UINT64_C(0x0000000000000040) 98 #define USBN_INT_LR_PU_F UINT64_C(0x0000000000000020) 99 #define USBN_INT_LR_PO_E UINT64_C(0x0000000000000010) 100 #define USBN_INT_NR_PU_F UINT64_C(0x0000000000000008) 101 #define USBN_INT_NR_PO_E UINT64_C(0x0000000000000004) 102 #define USBN_INT_PR_PU_F UINT64_C(0x0000000000000002) 103 #define USBN_INT_PR_PO_E UINT64_C(0x0000000000000001) 104 105 #define USBN_CLK_CTL_XXX_63_18 UINT64_C(0xfffffffffffc0000) 106 #define USBN_CLK_CTL_HCLK_RST UINT64_C(0x0000000000020000) 107 #define USBN_CLK_CTL_P_X_ON UINT64_C(0x0000000000010000) 108 #define USBN_CLK_CTL_P_RCLK UINT64_C(0x0000000000008000) 109 #define USBN_CLK_CTL_P_XENBN UINT64_C(0x0000000000004000) 110 #define USBN_CLK_CTL_P_COM_ON UINT64_C(0x0000000000002000) 111 #define USBN_CLK_CTL_P_C_SEL UINT64_C(0x0000000000001800) 112 #define USBN_CLK_CTL_P_C_SEL_12MHZ 0 113 #define USBN_CLK_CTL_P_C_SEL_24MHZ 1 114 #define USBN_CLK_CTL_P_C_SEL_48MHZ 2 115 #define USBN_CLK_CTL_CDIV_BYP UINT64_C(0x0000000000000400) 116 #define USBN_CLK_CTL_SD_MODE UINT64_C(0x0000000000000300) 117 #define USBN_CLK_CTL_S_BIST UINT64_C(0x0000000000000080) 118 #define USBN_CLK_CTL_POR UINT64_C(0x0000000000000040) 119 #define USBN_CLK_CTL_ENABLE UINT64_C(0x0000000000000020) 120 #define USBN_CLK_CTL_PRST UINT64_C(0x0000000000000010) 121 #define USBN_CLK_CTL_HRST UINT64_C(0x0000000000000008) 122 #define USBN_CLK_CTL_DIVIDE UINT64_C(0x0000000000000007) 123 /* CN50xx extension */ 124 #define USBN_CLK_CTL_DIVIDE2 UINT64_C(0x00000000000c0000) 125 #define USBN_CLK_CTL_P_RTYPE UINT64_C(0x000000000000c000) 126 127 #define USBN_USBP_CTL_STATUS_XXX_63_38 UINT64_C(0xffffffc000000000) 128 #define USBN_USBP_CTL_STATUS_BIST_DONE UINT64_C(0x0000002000000000) 129 #define USBN_USBP_CTL_STATUS_BIST_ERR UINT64_C(0x0000001000000000) 130 #define USBN_USBP_CTL_STATUS_TDATA_OUT UINT64_C(0x0000000f00000000) 131 #define USBN_USBP_CTL_STATUS_SPARES UINT64_C(0x00000000e0000000) 132 #define USBN_USBP_CTL_STATUS_USBC_END UINT64_C(0x0000000010000000) 133 #define USBN_USBP_CTL_STATUS_USBP_BIST UINT64_C(0x0000000008000000) 134 #define USBN_USBP_CTL_STATUS_TCLK UINT64_C(0x0000000004000000) 135 #define USBN_USBP_CTL_STATUS_DP_PULLD UINT64_C(0x0000000002000000) 136 #define USBN_USBP_CTL_STATUS_DM_PULLD UINT64_C(0x0000000001000000) 137 #define USBN_USBP_CTL_STATUS_HST_MODE UINT64_C(0x0000000000800000) 138 #define USBN_USBP_CTL_STATUS_TUNING UINT64_C(0x0000000000780000) 139 #define USBN_USBP_CTL_STATUS_TX_BS_ENH UINT64_C(0x0000000000040000) 140 #define USBN_USBP_CTL_STATUS_TX_BS_EN UINT64_C(0x0000000000020000) 141 #define USBN_USBP_CTL_STATUS_LOOP_ENB UINT64_C(0x0000000000010000) 142 #define USBN_USBP_CTL_STATUS_VTEST_ENB UINT64_C(0x0000000000008000) 143 #define USBN_USBP_CTL_STATUS_BIST_ENB UINT64_C(0x0000000000004000) 144 #define USBN_USBP_CTL_STATUS_TDATA_SEL UINT64_C(0x0000000000002000) 145 #define USBN_USBP_CTL_STATUS_TADDR_IN UINT64_C(0x0000000000001e00) 146 #define USBN_USBP_CTL_STATUS_TDATA_IN UINT64_C(0x00000000000001fe) 147 #define USBN_USBP_CTL_STATUS_ATE_RESET UINT64_C(0x0000000000000001) 148 /* CN50xx extension */ 149 #define USBN_USBP_CTL_STATUS_TXRISETUNE UINT64_C(0x8000000000000000) 150 #define USBN_USBP_CTL_STATUS_TXVREFTUNE UINT64_C(0x7800000000000000) 151 #define USBN_USBP_CTL_STATUS_TXFSLSTUNE UINT64_C(0x0780000000000000) 152 #define USBN_USBP_CTL_STATUS_TXHSXVTUNE UINT64_C(0x0060000000000000) 153 #define USBN_USBP_CTL_STATUS_SQRXTUNE UINT64_C(0x001c000000000000) 154 #define USBN_USBP_CTL_STATUS_COMPDISTUNE UINT64_C(0x0003800000000000) 155 #define USBN_USBP_CTL_STATUS_OTGTUNE UINT64_C(0x0000700000000000) 156 #define USBN_USBP_CTL_STATUS_OTGDISABLE UINT64_C(0x0000080000000000) 157 #define USBN_USBP_CTL_STATUS_PORTRESET UINT64_C(0x0000040000000000) 158 #define USBN_USBP_CTL_STATUS_DRVVBUS UINT64_C(0x0000020000000000) 159 #define USBN_USBP_CTL_STATUS_LSBIST UINT64_C(0x0000010000000000) 160 #define USBN_USBP_CTL_STATUS_FSBIST UINT64_C(0x0000008000000000) 161 #define USBN_USBP_CTL_STATUS_HSBIST UINT64_C(0x0000004000000000) 162 163 #define USBN_BIST_STATUS_XXX_63_3 UINT64_C(0xfffffffffffffff8) 164 #define USBN_BIST_STATUS_USBC_BIS UINT64_C(0x0000000000000004) 165 #define USBN_BIST_STATUS_NIF_BIS UINT64_C(0x0000000000000002) 166 #define USBN_BIST_STATUS_NOF_BIS UINT64_C(0x0000000000000001) 167 /* CN50xx extension */ 168 #define USBN_BIST_STATUS_U2NC_BIS UINT64_C(0x0000000000000040) 169 #define USBN_BIST_STATUS_U2NF_BIS UINT64_C(0x0000000000000020) 170 #define USBN_BIST_STATUS_E2HC_BIS UINT64_C(0x0000000000000010) 171 #define USBN_BIST_STATUS_N2UF_BIS UINT64_C(0x0000000000000008) 172 173 #define USBN_CTL_STATUS_XXX_63_6 UINT64_C(0xffffffffffffffc0) 174 #define USBN_CTL_STATUS_DMA_0PAG UINT64_C(0x0000000000000020) 175 #define USBN_CTL_STATUS_DMA_STT UINT64_C(0x0000000000000010) 176 #define USBN_CTL_STATUS_DMA_TEST UINT64_C(0x0000000000000008) 177 #define USBN_CTL_STATUS_INV_A2 UINT64_C(0x0000000000000004) 178 #define USBN_CTL_STATUS_L2C_EMOD UINT64_C(0x0000000000000003) 179 180 #define USBN_DMA_TEST_XXX_63_40 UINT64_C(0xffffff0000000000) 181 #define USBN_DMA_TEST_DONE UINT64_C(0x0000008000000000) 182 #define USBN_DMA_TEST_REQ UINT64_C(0x0000004000000000) 183 #define USBN_DMA_TEST_F_ADDR UINT64_C(0x0000003ffff00000) 184 #define USBN_DMA_TEST_COUNT UINT64_C(0x00000000000ffe00) 185 #define USBN_DMA_TEST_CHANNEL UINT64_C(0x00000000000001f0) 186 #define USBN_DMA_TEST_BURST UINT64_C(0x000000000000000f) 187 188 /* for USBN_DMA0_INB_CHN(0..7) */ 189 #define USBN_DMA0_INB_CHNX_XXX_63_36 UINT64_C(0xfffffff000000000) 190 #define USBN_DMA0_INB_CHNX_ADDR UINT64_C(0x0000000fffffffff) 191 192 /* for USBN_DMA0_OUTB_CHN(0..7) */ 193 #define USBN_DMA0_OUTB_CHNX_XXX_63_36 UINT64_C(0xfffffff000000000) 194 #define USBN_DMA0_OUTB_CHNX_ADDR UINT64_C(0x0000000fffffffff) 195 196 /* ---- bus_space */ 197 198 #define USBN_NUNITS 1 199 #define USBN_BASE 0x0001180068000000ULL 200 #define USBN_SIZE 0x800 201 202 #define USBN_INT_SUM_OFFSET 0x00000000 203 #define USBN_INT_ENB_OFFSET 0x00000008 204 #define USBN_CLK_CTL_OFFSET 0x00000010 205 #define USBN_USBP_CTL_STATUS_OFFSET 0x00000018 206 #define USBN_BIST_STATUS_OFFSET 0x000007f8 207 208 209 /* ---- bus_space 2 */ 210 211 #define USBN_2_NUNITS 1 212 #define USBN_2_BASE 0x00016F0000000800ULL 213 #define USBN_2_SIZE 0x098 214 215 #define USBN_CTL_STATUS_OFFSET 0x00000000 216 #define USBN_DMA_TEST_OFFSET 0x00000008 217 #define USBN_DMA0_INB_CHN0_OFFSET 0x00000018 218 #define USBN_DMA0_INB_CHN1_OFFSET 0x00000020 219 #define USBN_DMA0_INB_CHN2_OFFSET 0x00000028 220 #define USBN_DMA0_INB_CHN3_OFFSET 0x00000030 221 #define USBN_DMA0_INB_CHN4_OFFSET 0x00000038 222 #define USBN_DMA0_INB_CHN5_OFFSET 0x00000040 223 #define USBN_DMA0_INB_CHN6_OFFSET 0x00000048 224 #define USBN_DMA0_INB_CHN7_OFFSET 0x00000050 225 #define USBN_DMA0_OUTB_CHN0_OFFSET 0x00000058 226 #define USBN_DMA0_OUTB_CHN1_OFFSET 0x00000060 227 #define USBN_DMA0_OUTB_CHN2_OFFSET 0x00000068 228 #define USBN_DMA0_OUTB_CHN3_OFFSET 0x00000070 229 #define USBN_DMA0_OUTB_CHN4_OFFSET 0x00000078 230 #define USBN_DMA0_OUTB_CHN5_OFFSET 0x00000080 231 #define USBN_DMA0_OUTB_CHN6_OFFSET 0x00000088 232 #define USBN_DMA0_OUTB_CHN7_OFFSET 0x00000090 233 234 #endif /* _OCTEON_USBNREG_H_ */ 235
Indexes created Mon Sep 29 21:09:56 GMT 2025