octeon_xhci.c revision 1.5
1 /* $NetBSD: octeon_xhci.c,v 1.5 2021/04/24 23:36:42 thorpej Exp $ */ 2 /* $OpenBSD: octxhci.c,v 1.4 2019/09/29 04:32:23 visa Exp $ */ 3 4 /* 5 * Copyright (c) 2017 Visa Hankala 6 * Copyright (c) 2020 Jared McNeill <jmcneill (at) invisible.ca> 7 * 8 * Permission to use, copy, modify, and distribute this software for any 9 * purpose with or without fee is hereby granted, provided that the above 10 * copyright notice and this permission notice appear in all copies. 11 * 12 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 13 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 14 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 15 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 16 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 17 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 18 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 19 */ 20 21 /* 22 * Driver for OCTEON USB3 controller bridge. 23 */ 24 25 #include <sys/param.h> 26 #include <sys/systm.h> 27 #include <sys/device.h> 28 #include <sys/malloc.h> 29 30 #include <mips/cavium/octeonvar.h> 31 32 #include <mips/cavium/dev/octeon_xhcireg.h> 33 34 #include <dev/usb/usb.h> 35 #include <dev/usb/usbdi.h> 36 #include <dev/usb/usbdivar.h> 37 #include <dev/usb/usb_mem.h> 38 #include <dev/usb/xhcireg.h> 39 #include <dev/usb/xhcivar.h> 40 41 #include <dev/fdt/fdtvar.h> 42 43 #define XCTL_RD_8(sc, reg) \ 44 bus_space_read_8((sc)->sc_iot, (sc)->sc_ioh, (reg)) 45 #define XCTL_WR_8(sc, reg, val) \ 46 bus_space_write_8((sc)->sc_iot, (sc)->sc_ioh, (reg), (val)) 47 48 struct octxhci_softc { 49 struct xhci_softc sc_xhci; 50 bus_space_tag_t sc_iot; 51 bus_space_handle_t sc_ioh; 52 struct fdtbus_gpio_pin *sc_power_gpio; 53 int sc_unit; 54 }; 55 56 static int octxhci_match(device_t, cfdata_t, void *); 57 static void octxhci_attach(device_t, device_t, void *); 58 59 static int octxhci_dwc3_init(struct xhci_softc *); 60 static void octxhci_uctl_init(struct octxhci_softc *, uint64_t, uint64_t); 61 62 static void octxhci_bus_io_init(bus_space_tag_t, void *); 63 64 static struct mips_bus_space octxhci_bus_tag; 65 66 CFATTACH_DECL_NEW(octxhci, sizeof(struct octxhci_softc), 67 octxhci_match, octxhci_attach, NULL, NULL); 68 69 static const struct device_compatible_entry compat_data[] = { 70 { .compat = "cavium,octeon-7130-usb-uctl" }, 71 DEVICE_COMPAT_EOL 72 }; 73 74 int 75 octxhci_match(device_t parent, cfdata_t cf, void *aux) 76 { 77 struct fdt_attach_args * const faa = aux; 78 79 return of_compatible_match(faa->faa_phandle, compat_data); 80 } 81 82 void 83 octxhci_attach(device_t parent, device_t self, void *aux) 84 { 85 struct octxhci_softc *osc = device_private(self); 86 struct xhci_softc *sc = &osc->sc_xhci; 87 struct fdt_attach_args * const faa = aux; 88 const int phandle = faa->faa_phandle; 89 const char *clock_type_hs; 90 const char *clock_type_ss; 91 u_int clock_freq, clock_sel; 92 char intrstr[128]; 93 int child, error; 94 bus_addr_t addr; 95 bus_size_t size; 96 void *ih; 97 98 osc->sc_iot = faa->faa_bst; 99 100 if (fdtbus_get_reg(phandle, 0, &addr, &size) != 0) { 101 aprint_error(": couldn't get bridge registers\n"); 102 return; 103 } 104 if (bus_space_map(osc->sc_iot, addr, size, 0, &osc->sc_ioh) != 0) { 105 aprint_error(": couldn't map bridge registers\n"); 106 return; 107 } 108 osc->sc_power_gpio = fdtbus_gpio_acquire(phandle, "power", 109 GPIO_PIN_OUTPUT); 110 osc->sc_unit = (addr >> 24) & 0x1; 111 112 octxhci_bus_io_init(&octxhci_bus_tag, NULL); 113 114 sc->sc_dev = self; 115 sc->sc_bus.ub_hcpriv = sc; 116 sc->sc_bus.ub_dmatag = faa->faa_dmat; 117 sc->sc_iot = &octxhci_bus_tag; 118 sc->sc_ios = size; 119 120 child = of_find_bycompat(phandle, "synopsys,dwc3"); 121 if (child == -1) { 122 aprint_error(": couldn't find dwc3 child node\n"); 123 return; 124 } 125 if (fdtbus_get_reg(child, 0, &addr, &size) != 0) { 126 aprint_error(": couldn't get xhci registers\n"); 127 return; 128 } 129 if (bus_space_map(sc->sc_iot, addr, size, 0, &sc->sc_ioh) != 0) { 130 aprint_error(": couldn't map xhci registers\n"); 131 return; 132 } 133 134 if (of_getprop_uint32(phandle, "refclk-frequency", &clock_freq) != 0) { 135 aprint_error(": couldn't get refclk-frequency property\n"); 136 return; 137 } 138 clock_type_hs = fdtbus_get_string(phandle, "refclk-type-hs"); 139 if (clock_type_hs == NULL) { 140 aprint_error(": couldn't get refclk-type-hs property\n"); 141 return; 142 } 143 clock_type_ss = fdtbus_get_string(phandle, "refclk-type-ss"); 144 if (clock_type_ss == NULL) { 145 aprint_error(": couldn't get refclk-type-ss property\n"); 146 return; 147 } 148 149 clock_sel = 0; 150 if (strcmp(clock_type_ss, "dlmc_ref_clk1") == 0) 151 clock_sel |= 1; 152 if (strcmp(clock_type_hs, "pll_ref_clk") == 0) 153 clock_sel |= 2; 154 155 octxhci_uctl_init(osc, clock_freq, clock_sel); 156 157 if (octxhci_dwc3_init(sc) != 0) { 158 /* Error message has been printed already. */ 159 return; 160 } 161 162 if (!fdtbus_intr_str(child, 0, intrstr, sizeof(intrstr))) { 163 aprint_error_dev(self, "failed to decode interrupt\n"); 164 return; 165 } 166 167 ih = fdtbus_intr_establish(child, 0, IPL_USB, FDT_INTR_MPSAFE, 168 xhci_intr, sc); 169 if (ih == NULL) { 170 aprint_error_dev(self, "couldn't establish interrupt on %s\n", 171 intrstr); 172 return; 173 } 174 aprint_normal_dev(self, "interrupting on %s\n", intrstr); 175 176 sc->sc_bus.ub_revision = USBREV_3_0; 177 error = xhci_init(sc); 178 if (error != 0) { 179 aprint_error_dev(self, "init failed, error = %d\n", error); 180 return; 181 } 182 183 sc->sc_child = config_found(self, &sc->sc_bus, usbctlprint, CFARG_EOL); 184 sc->sc_child2 = config_found(self, &sc->sc_bus2, usbctlprint, 185 CFARG_EOL); 186 } 187 188 void 189 octxhci_uctl_init(struct octxhci_softc *sc, uint64_t clock_freq, 190 uint64_t clock_sel) 191 { 192 static const uint32_t clock_divs[] = { 1, 2, 4, 6, 8, 16, 24, 32 }; 193 uint64_t i, val; 194 uint64_t ioclock = octeon_ioclock_speed(); 195 uint64_t mpll_mult; 196 uint64_t refclk_fsel; 197 #if notyet 198 int output_sel; 199 #endif 200 201 /* 202 * Put the bridge controller, USB core, PHY, and clock divider 203 * into reset. 204 */ 205 val = XCTL_RD_8(sc, XCTL_CTL); 206 val |= XCTL_CTL_UCTL_RST; 207 val |= XCTL_CTL_UAHC_RST; 208 val |= XCTL_CTL_UPHY_RST; 209 XCTL_WR_8(sc, XCTL_CTL, val); 210 val = XCTL_RD_8(sc, XCTL_CTL); 211 val |= XCTL_CTL_CLKDIV_RST; 212 XCTL_WR_8(sc, XCTL_CTL, val); 213 214 /* Select IO clock divisor. */ 215 for (i = 0; i < __arraycount(clock_divs); i++) { 216 if (ioclock / clock_divs[i] < 300000000) 217 break; 218 } 219 220 /* Update the divisor and enable the clock. */ 221 val = XCTL_RD_8(sc, XCTL_CTL); 222 val &= ~XCTL_CTL_CLKDIV_SEL; 223 val |= (i << XCTL_CTL_CLKDIV_SEL_SHIFT) & XCTL_CTL_CLKDIV_SEL; 224 val |= XCTL_CTL_CLK_EN; 225 XCTL_WR_8(sc, XCTL_CTL, val); 226 227 /* Take the clock divider out of reset. */ 228 val = XCTL_RD_8(sc, XCTL_CTL); 229 val &= ~XCTL_CTL_CLKDIV_RST; 230 XCTL_WR_8(sc, XCTL_CTL, val); 231 232 /* Select the reference clock. */ 233 switch (clock_freq) { 234 case 50000000: 235 refclk_fsel = 0x07; 236 mpll_mult = 0x32; 237 break; 238 case 125000000: 239 refclk_fsel = 0x07; 240 mpll_mult = 0x28; 241 break; 242 case 100000000: 243 default: 244 if (clock_sel < 2) 245 refclk_fsel = 0x27; 246 else 247 refclk_fsel = 0x07; 248 mpll_mult = 0x19; 249 break; 250 } 251 252 /* Set the clock and power up PHYs. */ 253 val = XCTL_RD_8(sc, XCTL_CTL); 254 val &= ~XCTL_CTL_REFCLK_SEL; 255 val |= clock_sel << XCTL_CTL_REFCLK_SEL_SHIFT; 256 val &= ~XCTL_CTL_REFCLK_DIV2; 257 val &= ~XCTL_CTL_REFCLK_FSEL; 258 val |= refclk_fsel << XCTL_CTL_REFCLK_FSEL_SHIFT; 259 val &= ~XCTL_CTL_MPLL_MULT; 260 val |= mpll_mult << XCTL_CTL_MPLL_MULT_SHIFT; 261 val |= XCTL_CTL_SSC_EN; 262 val |= XCTL_CTL_REFCLK_SSP_EN; 263 val |= XCTL_CTL_SSPOWER_EN; 264 val |= XCTL_CTL_HSPOWER_EN; 265 XCTL_WR_8(sc, XCTL_CTL, val); 266 267 delay(100); 268 269 /* Take the bridge out of reset. */ 270 val = XCTL_RD_8(sc, XCTL_CTL); 271 val &= ~XCTL_CTL_UCTL_RST; 272 XCTL_WR_8(sc, XCTL_CTL, val); 273 274 delay(100); 275 276 #if notyet 277 if (sc->sc_power_gpio[0] != 0) { 278 if (sc->sc_unit == 0) 279 output_sel = GPIO_CONFIG_MD_USB0_VBUS_CTRL; 280 else 281 output_sel = GPIO_CONFIG_MD_USB1_VBUS_CTRL; 282 gpio_controller_config_pin(sc->sc_power_gpio, 283 GPIO_CONFIG_OUTPUT | output_sel); 284 285 /* Enable port power control. */ 286 val = XCTL_RD_8(sc, XCTL_HOST_CFG); 287 val |= XCTL_HOST_CFG_PPC_EN; 288 if (sc->sc_power_gpio[2] & GPIO_ACTIVE_LOW) 289 val &= ~XCTL_HOST_CFG_PPC_ACTIVE_HIGH_EN; 290 else 291 val |= XCTL_HOST_CFG_PPC_ACTIVE_HIGH_EN; 292 XCTL_WR_8(sc, XCTL_HOST_CFG, val); 293 } else { 294 /* Disable port power control. */ 295 val = XCTL_RD_8(sc, XCTL_HOST_CFG); 296 val &= ~XCTL_HOST_CFG_PPC_EN; 297 XCTL_WR_8(sc, XCTL_HOST_CFG, val); 298 } 299 #else 300 /* Disable port power control. */ 301 val = XCTL_RD_8(sc, XCTL_HOST_CFG); 302 val &= ~XCTL_HOST_CFG_PPC_EN; 303 XCTL_WR_8(sc, XCTL_HOST_CFG, val); 304 #endif 305 306 /* Enable host-only mode. */ 307 val = XCTL_RD_8(sc, XCTL_CTL); 308 val &= ~XCTL_CTL_DRD_MODE; 309 XCTL_WR_8(sc, XCTL_CTL, val); 310 311 delay(100); 312 313 /* Take the USB core out of reset. */ 314 val = XCTL_RD_8(sc, XCTL_CTL); 315 val &= ~XCTL_CTL_UAHC_RST; 316 XCTL_WR_8(sc, XCTL_CTL, val); 317 318 delay(100); 319 320 val = XCTL_RD_8(sc, XCTL_CTL); 321 val |= XCTL_CTL_CSCLK_EN; 322 XCTL_WR_8(sc, XCTL_CTL, val); 323 324 /* Take the PHY out of reset. */ 325 val = XCTL_RD_8(sc, XCTL_CTL); 326 val &= ~XCTL_CTL_UPHY_RST; 327 XCTL_WR_8(sc, XCTL_CTL, val); 328 (void)XCTL_RD_8(sc, XCTL_CTL); 329 330 /* Fix endianess. */ 331 val = XCTL_RD_8(sc, XCTL_SHIM_CFG); 332 val &= ~XCTL_SHIM_CFG_CSR_BYTE_SWAP; 333 val &= ~XCTL_SHIM_CFG_DMA_BYTE_SWAP; 334 val |= __SHIFTIN(XCTL_SHIM_ENDIAN_BIG, XCTL_SHIM_CFG_DMA_BYTE_SWAP); 335 val |= __SHIFTIN(XCTL_SHIM_ENDIAN_BIG, XCTL_SHIM_CFG_CSR_BYTE_SWAP); 336 XCTL_WR_8(sc, XCTL_SHIM_CFG, val); 337 (void)XCTL_RD_8(sc, XCTL_SHIM_CFG); 338 } 339 340 int 341 octxhci_dwc3_init(struct xhci_softc *sc) 342 { 343 bus_space_handle_t ioh = sc->sc_ioh; 344 uint32_t rev; 345 uint32_t val; 346 347 val = bus_space_read_4(sc->sc_iot, ioh, DWC3_GSNPSID); 348 if ((val & 0xffff0000u) != 0x55330000u) { 349 aprint_error(": no DWC3 core (DWC3_GSNPSID=%08x)\n", val); 350 return EIO; 351 } 352 rev = val & 0xffffu; 353 aprint_normal(": DWC3 rev 0x%04x\n", rev); 354 355 val = bus_space_read_4(sc->sc_iot, ioh, DWC3_GUSB3PIPECTL(0)); 356 val &= ~DWC3_GUSB3PIPECTL_UX_EXIT_PX; 357 val |= DWC3_GUSB3PIPECTL_SUSPHY; 358 bus_space_write_4(sc->sc_iot, ioh, DWC3_GUSB3PIPECTL(0), val); 359 360 val = bus_space_read_4(sc->sc_iot, ioh, DWC3_GUSB2PHYCFG(0)); 361 val |= DWC3_GUSB2PHYCFG_SUSPHY; 362 bus_space_write_4(sc->sc_iot, ioh, DWC3_GUSB2PHYCFG(0), val); 363 364 /* Set the controller into host mode. */ 365 val = bus_space_read_4(sc->sc_iot, ioh, DWC3_GCTL); 366 val &= ~DWC3_GCTL_PRTCAP_MASK; 367 val |= DWC3_GCTL_PRTCAP_HOST; 368 bus_space_write_4(sc->sc_iot, ioh, DWC3_GCTL, val); 369 370 val = bus_space_read_4(sc->sc_iot, ioh, DWC3_GCTL); 371 val &= ~DWC3_GCTL_SCALEDOWN_MASK; 372 val &= ~DWC3_GCTL_DISSCRAMBLE; 373 if (rev >= DWC3_REV_210A && rev <= DWC3_REV_250A) 374 val |= DWC3_GCTL_DSBLCLKGTNG | DWC3_GCTL_SOFITPSYNC; 375 else 376 val &= ~DWC3_GCTL_DSBLCLKGTNG; 377 bus_space_write_4(sc->sc_iot, ioh, DWC3_GCTL, val); 378 379 return 0; 380 } 381 382 /* ---- bus_space(9) */ 383 #define CHIP octxhci 384 #define CHIP_IO 385 #define CHIP_LITTLE_ENDIAN 386 387 #define CHIP_W1_BUS_START(v) 0x0000000000000000ULL 388 #define CHIP_W1_BUS_END(v) 0x7fffffffffffffffULL 389 #define CHIP_W1_SYS_START(v) 0x8000000000000000ULL 390 #define CHIP_W1_SYS_END(v) 0xffffffffffffffffULL 391 392 #include <mips/mips/bus_space_alignstride_chipdep.c> 393
Indexes created Mon Sep 29 03:10:08 GMT 2025