octeon_cpunode.c revision 1.1
1 /*- 2 * Copyright (c) 2014 The NetBSD Foundation, Inc. 3 * All rights reserved. 4 * 5 * This code is derived from software contributed to The NetBSD Foundation 6 * by Matt Thomas of 3am Software Foundry. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 18 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 19 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 20 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 21 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 22 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 23 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 24 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 25 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 26 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 27 * POSSIBILITY OF SUCH DAMAGE. 28 */ 29 #define __INTR_PRIVATE 30 #include <sys/cdefs.h> 31 32 __KERNEL_RCSID(0, "$NetBSD"); 33 34 #include "locators.h" 35 36 #include <sys/param.h> 37 #include <sys/device.h> 38 #include <sys/lwp.h> 39 #include <sys/cpu.h> 40 41 #include <mips/cache.h> 42 #include <mips/cpuset.h> 43 #include <mips/mips_opcode.h> 44 45 #include <mips/cavium/octeonvar.h> 46 #include <mips/cavium/dev/octeon_ciureg.h> 47 #include <mips/cavium/dev/octeon_corereg.h> 48 49 struct cpunode_attach_args { 50 const char *cnaa_name; 51 int cnaa_cpunum; 52 }; 53 54 static int cpunode_mainbus_match(device_t, cfdata_t, void *); 55 static void cpunode_mainbus_attach(device_t, device_t, void *); 56 57 static int cpu_cpunode_match(device_t, cfdata_t, void *); 58 static void cpu_cpunode_attach(device_t, device_t, void *); 59 60 CFATTACH_DECL_NEW(cpunode, 0, 61 cpunode_mainbus_match, cpunode_mainbus_attach, NULL, NULL); 62 63 CFATTACH_DECL_NEW(cpunode_cpu, 0, 64 cpu_cpunode_match, cpu_cpunode_attach, NULL, NULL); 65 66 volatile __cpuset_t cpus_booted = 1; 67 68 static int 69 cpunode_mainbus_print(void *aux, const char *pnp) 70 { 71 struct cpunode_attach_args * const cnaa = aux; 72 73 aprint_normal(" core %d", cnaa->cnaa_cpunum); 74 75 return UNCONF; 76 } 77 78 int 79 cpunode_mainbus_match(device_t parent, cfdata_t cf, void *aux) 80 { 81 82 return 1; 83 } 84 85 void 86 cpunode_mainbus_attach(device_t parent, device_t self, void *aux) 87 { 88 uint64_t fuse = octeon_xkphys_read_8(CIU_FUSE); 89 int cpunum = 0; 90 91 aprint_naive(": %u core%s\n", 92 popcount32((uint32_t)fuse), 93 fuse == 1 ? "" : "s"); 94 95 aprint_normal(": %u core%s", 96 popcount32((uint32_t)fuse), 97 fuse == 1 ? "" : "s"); 98 const uint64_t cvmctl = mips_cp0_cvmctl_read(); 99 aprint_normal(", %scrypto", (cvmctl & CP0_CVMCTL_NOCRYPTO) ? "no " : ""); 100 aprint_normal((cvmctl & CP0_CVMCTL_KASUMI) ? "+kasumi" : ""); 101 aprint_normal(", %s64bit-mul", (cvmctl & CP0_CVMCTL_NOMUL) ? "no " : ""); 102 if (cvmctl & CP0_CVMCTL_REPUN) 103 aprint_normal(", unaligned-access ok"); 104 aprint_normal("\n"); 105 106 for (; fuse != 0; fuse >>= 1, cpunum++) { 107 struct cpunode_attach_args cnaa = { 108 .cnaa_name = "cpu", 109 .cnaa_cpunum = cpunum, 110 }; 111 config_found(self, &cnaa, cpunode_mainbus_print); 112 } 113 } 114 115 int 116 cpu_cpunode_match(device_t parent, cfdata_t cf, void *aux) 117 { 118 struct cpunode_attach_args * const cnaa = aux; 119 const int cpunum = cf->cf_loc[CPUNODECF_CORE]; 120 121 return cpunum == CPUNODECF_CORE_DEFAULT 122 || cpunum == cnaa->cnaa_cpunum; 123 } 124 125 #if defined(MULTIPROCESSOR) 126 static bool 127 octeon_fixup_cpu_info_references(int32_t load_addr, uint32_t new_insns[2], 128 void *arg) 129 { 130 struct cpu_info * const ci = arg; 131 132 KASSERT(MIPS_KSEG0_P(load_addr)); 133 KASSERT(!MIPS_CACHE_VIRTUAL_ALIAS); 134 #ifdef MULTIPROCESSOR 135 KASSERT(!CPU_IS_PRIMARY(curcpu())); 136 #endif 137 load_addr += (intptr_t)ci - (intptr_t)&cpu_info_store; 138 139 KASSERT((intptr_t)ci <= load_addr); 140 KASSERT(load_addr < (intptr_t)(ci + 1)); 141 142 KASSERT(INSN_LUI_P(new_insns[0])); 143 KASSERT(INSN_LOAD_P(new_insns[1]) || INSN_STORE_P(new_insns[1])); 144 145 /* 146 * Use the lui and load/store instruction as a prototype and 147 * make it refer to cpu1_info_store instead of cpu_info_store. 148 */ 149 new_insns[0] &= __BITS(31,16); 150 new_insns[1] &= __BITS(31,16); 151 new_insns[0] |= (uint16_t)((load_addr + 0x8000) >> 16); 152 new_insns[1] |= (uint16_t)load_addr; 153 #ifdef DEBUG_VERBOSE 154 printf("%s: %08x: insn#1 %08x: lui r%u, %d\n", 155 __func__, (int32_t)load_addr, new_insns[0], 156 (new_insns[0] >> 16) & 31, 157 (int16_t)new_insns[0]); 158 printf("%s: %08x: insn#2 %08x: %c%c r%u, %d(r%u)\n", 159 __func__, (int32_t)load_addr, new_insns[0], 160 INSN_LOAD_P(new_insns[1]) ? 'l' : 's', 161 INSN_LW_P(new_insns[1]) ? 'w' : 'd', 162 (new_insns[0] >> 16) & 31, 163 (int16_t)new_insns[1], 164 (new_insns[0] >> 21) & 31); 165 #endif 166 return true; 167 } 168 169 static void 170 octeon_cpu_init(struct cpu_info *ci) 171 { 172 bool ok __diagused; 173 174 // First thing is setup the execption vectors for this cpu. 175 mips64r2_vector_init(&mips_splsw); 176 177 // Next rewrite those exceptions to use this cpu's cpu_info. 178 ok = mips_fixup_exceptions(octeon_fixup_cpu_info_references, ci); 179 KASSERT(ok); 180 181 (void) splhigh(); 182 183 #ifdef DEBUG 184 KASSERT((mipsNN_cp0_ebase_read() & MIPS_EBASE_CPUNUM) == ci->ci_cpuid); 185 KASSERT(curcpu() == ci); 186 #endif 187 } 188 189 static void 190 octeon_cpu_run(struct cpu_info *ci) 191 { 192 } 193 #endif /* MULTIPROCESSOR */ 194 195 static void 196 cpu_cpunode_attach_common(device_t self, struct cpu_info *ci) 197 { 198 ci->ci_dev = self; 199 self->dv_private = ci; 200 201 aprint_normal(": %lu.%02luMHz (hz cycles = %lu, delay divisor = %lu)\n", 202 ci->ci_cpu_freq / 1000000, 203 (ci->ci_cpu_freq % 1000000) / 10000, 204 ci->ci_cycles_per_hz, ci->ci_divisor_delay); 205 206 aprint_normal("%s: ", device_xname(self)); 207 cpu_identify(self); 208 cpu_attach_common(self, ci); 209 } 210 211 void 212 cpu_cpunode_attach(device_t parent, device_t self, void *aux) 213 { 214 struct cpunode_attach_args * const cnaa = aux; 215 const int cpunum = cnaa->cnaa_cpunum; 216 217 if (cpunum == 0) { 218 cpu_cpunode_attach_common(self, curcpu()); 219 #ifdef MULTIPROCESSOR 220 mips_locoresw.lsw_cpu_init = octeon_cpu_init; 221 mips_locoresw.lsw_cpu_run = octeon_cpu_run; 222 #endif 223 return; 224 } 225 #ifdef MULTIPROCESSOR 226 KASSERTMSG(cpunum == 1, "cpunum %d", cpunum); 227 if (!CPUSET_HAS_P(cpus_booted, cpunum)) { 228 aprint_naive(" disabled\n"); 229 aprint_normal(" disabled (unresponsive)\n"); 230 return; 231 } 232 struct cpu_info * const ci = cpu_info_alloc(NULL, cpunum, 0, cpunum, 0); 233 234 ci->ci_softc = &octeon_cpu1_softc; 235 ci->ci_softc->cpu_ci = ci; 236 237 cpu_cpunode_attach_common(self, ci); 238 #else 239 aprint_naive(": disabled\n"); 240 aprint_normal(": disabled (uniprocessor kernel)\n"); 241 #endif 242 } 243
Indexes created Mon Oct 13 05:10:05 GMT 2025