octeon_iobus.c revision 1.4
1 /* $NetBSD: octeon_iobus.c,v 1.4 2020/06/23 05:14:18 simonb Exp $ */ 2 3 /* 4 * Copyright (c) 2007 5 * Internet Initiative Japan, Inc. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 __KERNEL_RCSID(0, "$NetBSD: octeon_iobus.c,v 1.4 2020/06/23 05:14:18 simonb Exp $"); 31 32 #include "locators.h" 33 34 #include <sys/param.h> 35 #include <sys/systm.h> 36 #include <sys/device.h> 37 38 #define _MIPS_BUS_DMA_PRIVATE 39 #include <sys/bus.h> 40 41 #include <mips/cavium/include/iobusvar.h> 42 43 struct iobus_softc { 44 device_t sc_dev; 45 46 /* XXX load/IOBDMA/store operations */ 47 bus_space_handle_t sc_ops_bush; 48 }; 49 50 static int iobus_match(device_t, struct cfdata *, void *); 51 static void iobus_attach(device_t, device_t, void *); 52 static int iobus_submatch(device_t, struct cfdata *, const int *, void *); 53 static int iobus_print(void *, const char *); 54 static void iobus_init(struct iobus_softc *); 55 static void iobus_init_map(struct iobus_softc *); 56 static void iobus_init_local(struct iobus_softc *); 57 static void iobus_init_local_pow(struct iobus_softc *); 58 static void iobus_init_local_fpa(struct iobus_softc *); 59 60 static void iobus_bus_io_init(bus_space_tag_t, void *); 61 62 static struct mips_bus_space *iobus_bust; 63 static struct mips_bus_dma_tag *iobus_dmat; 64 65 void 66 iobus_bootstrap(struct octeon_config *mcp) 67 { 68 iobus_bus_io_init(&mcp->mc_iobus_bust, mcp); 69 70 iobus_bust = &mcp->mc_iobus_bust; 71 iobus_dmat = &mcp->mc_iobus_dmat; 72 } 73 74 /* ---- autoconf */ 75 76 CFATTACH_DECL_NEW(iobus, sizeof(struct iobus_softc), 77 iobus_match, iobus_attach, NULL, NULL); 78 79 static int 80 iobus_match(device_t parent, struct cfdata *match, void *aux) 81 { 82 return 1; 83 } 84 85 static void 86 iobus_attach(device_t parent, device_t self, void *aux) 87 { 88 struct iobus_softc *sc = device_private(self); 89 const struct iobus_dev *dev; 90 struct iobus_attach_args aa; 91 int i, j; 92 93 sc->sc_dev = self; 94 95 aprint_normal("\n"); 96 97 iobus_init(sc); 98 99 /* XXX should only attach Octeon 1 and Octeon Plus drivers */ 100 for (i = 0; i < (int)iobus_ndevs; i++) { 101 dev = iobus_devs[i]; 102 for (j = 0; j < dev->nunits; j++) { 103 aa.aa_name = dev->name; 104 aa.aa_unitno = j; 105 aa.aa_unit = &dev->units[j]; 106 aa.aa_bust = iobus_bust; 107 aa.aa_dmat = iobus_dmat; 108 109 (void)config_found_sm_loc( 110 self, 111 "iobus", 112 NULL, 113 &aa, 114 iobus_print, 115 iobus_submatch); 116 } 117 } 118 } 119 120 static int 121 iobus_submatch(device_t parent, struct cfdata *cf, const int *ldesc, void *aux) 122 { 123 124 return config_match(parent, cf, aux); 125 } 126 127 static int 128 iobus_print(void *aux, const char *pnp) 129 { 130 struct iobus_attach_args *aa = aux; 131 132 if (pnp) 133 aprint_normal("%s at %s", aa->aa_name, pnp); 134 135 aprint_normal(" address 0x%016" PRIx64, aa->aa_unit->addr); 136 137 return UNCONF; 138 } 139 140 /* ---- */ 141 142 void 143 iobus_init(struct iobus_softc *sc) 144 { 145 146 iobus_init_map(sc); 147 iobus_init_local(sc); 148 } 149 150 void 151 iobus_init_map(struct iobus_softc *sc) 152 { 153 154 /* XXX map all ``operations'' space at once */ 155 bus_space_map( 156 iobus_bust, 157 0x0001280000000000ULL, 158 0x0001800000000000ULL - 0x0001280000000000ULL, 159 0, 160 &sc->sc_ops_bush); 161 } 162 163 void 164 iobus_init_local(struct iobus_softc *sc) 165 { 166 167 iobus_init_local_pow(sc); 168 iobus_init_local_fpa(sc); 169 } 170 171 extern struct octeon_config octeon_configuration; 172 173 void 174 iobus_init_local_pow(struct iobus_softc *sc) 175 { 176 177 void octpow_bootstrap(struct octeon_config *); 178 179 aprint_normal("%s: initializing POW\n", device_xname(sc->sc_dev)); 180 181 octpow_bootstrap(&octeon_configuration); 182 } 183 184 void 185 iobus_init_local_fpa(struct iobus_softc *sc) 186 { 187 188 void octfpa_bootstrap(struct octeon_config *); 189 190 aprint_normal("%s: initializing FPA\n", device_xname(sc->sc_dev)); 191 192 octfpa_bootstrap(&octeon_configuration); 193 } 194 195 /* ---- bus_space(9) */ 196 197 #define CHIP iobus 198 #define CHIP_IO 199 #define CHIP_ACCESS_SIZE 8 200 201 /* CIU and GPIO NCB type CSRs */ 202 #define CHIP_W1_BUS_START(v) 0x0001070000000000ULL 203 #define CHIP_W1_BUS_END(v) 0x00010700ffffffffULL 204 #define CHIP_W1_SYS_START(v) 0x8001070000000000ULL 205 #define CHIP_W1_SYS_END(v) 0x80010700ffffffffULL 206 207 /* a number of RSL type CSRs */ 208 #define CHIP_W2_BUS_START(v) 0x0001180000000000ULL 209 #define CHIP_W2_BUS_END(v) 0x000118ffffffffffULL 210 #define CHIP_W2_SYS_START(v) 0x8001180000000000ULL 211 #define CHIP_W2_SYS_END(v) 0x800118ffffffffffULL 212 213 /* load/IOBDMA/store operations */ 214 #define CHIP_W3_BUS_START(v) 0x0001280000000000ULL 215 #define CHIP_W3_BUS_END(v) 0x00017fffffffffffULL 216 #define CHIP_W3_SYS_START(v) 0x8001280000000000ULL 217 #define CHIP_W3_SYS_END(v) 0x80017fffffffffffULL 218 219 #include <mips/mips/bus_space_alignstride_chipdep.c> 220
Indexes created Fri Sep 26 20:09:58 GMT 2025