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files.sibyte revision 1.7.48.1
      1       1.1  simonb ###
      2       1.1  simonb ### SBMIPS DEVICES
      3       1.1  simonb ###
      4       1.1  simonb 
      5       1.1  simonb # System Control/Debug
      6       1.7    matt device	sbscd {[offset = -1], [intr[2] = {-1,-1}]}
      7       1.1  simonb attach	sbscd at zbbus
      8       1.1  simonb file	arch/mips/sibyte/dev/sbscd.c		sbscd
      9       1.1  simonb 
     10       1.1  simonb # On-board I/O (slow I/O bridge)
     11       1.7    matt device	sbobio {[offset = -1], [intr[2] = {-1,-1}]}
     12       1.1  simonb attach	sbobio at zbbus
     13       1.1  simonb file	arch/mips/sibyte/dev/sbobio.c		sbobio
     14       1.1  simonb 
     15       1.1  simonb # Generic bus, hang off of sbobio
     16       1.1  simonb device	sbgbus {[chipsel = -1], [offset = 0], [intr[2] = {-1,-1}]}
     17       1.1  simonb attach	sbgbus at sbobio
     18       1.1  simonb file	arch/mips/sibyte/dev/sbgbus.c		sbgbus
     19       1.1  simonb 
     20       1.1  simonb # I/O Bridge Zero attachment to ZBbus
     21       1.1  simonb device	sbbrz: pcibus
     22       1.1  simonb attach	sbbrz at zbbus
     23       1.1  simonb file	arch/mips/sibyte/pci/sbbrz.c		sbbrz
     24       1.1  simonb file	arch/mips/sibyte/pci/sbbrz_pci.c	sbbrz
     25       1.7    matt file	arch/mips/sibyte/pci/sbbrz_bus_io.c	sbbrz
     26       1.7    matt file	arch/mips/sibyte/pci/sbbrz_bus_mem.c	sbbrz
     27       1.1  simonb 
     28       1.1  simonb 
     29       1.1  simonb # sbscd children
     30       1.1  simonb 
     31       1.1  simonb device	sbtimer
     32       1.1  simonb attach	sbtimer at sbscd
     33       1.1  simonb file	arch/mips/sibyte/dev/sbtimer.c		sbtimer
     34       1.1  simonb 
     35       1.3  simonb device	sbwdog: sysmon_wdog
     36       1.1  simonb attach	sbwdog at sbscd
     37       1.1  simonb file	arch/mips/sibyte/dev/sbwdog.c		sbwdog
     38       1.1  simonb 
     39       1.1  simonb # sbobio children
     40       1.1  simonb 
     41       1.1  simonb # SB1250 MAC (XXX: maybe add mii_bitbang?)
     42       1.1  simonb device	sbmac: arp, ether, ifnet, mii, mii_bitbang
     43       1.1  simonb attach	sbmac at sbobio
     44       1.1  simonb file	arch/mips/sibyte/dev/sbmac.c		sbmac
     45       1.1  simonb 
     46       1.1  simonb # SB1250 built-in (asynchronous) serial ports
     47       1.1  simonb device	sbscn: tty
     48       1.1  simonb attach	sbscn at sbobio
     49       1.1  simonb file	arch/mips/sibyte/dev/sbscn.c		sbscn	needs-flag
     50       1.1  simonb 
     51       1.2  simonb # XXX XXX
     52       1.2  simonb # need to think about SMBus more, just hack something together
     53       1.2  simonb # temporariliy so we can use the RTC.
     54       1.2  simonb 
     55       1.2  simonb # SB1250 SMBus
     56       1.2  simonb device	smbus {[chan = -1], [dev = -1]}
     57       1.2  simonb attach	smbus at sbobio
     58       1.2  simonb file	arch/mips/sibyte/dev/sbsmbus.c		smbus
     59       1.2  simonb 
     60       1.2  simonb # XXX XXX
     61       1.4  simonb # XXX also, this should be in sbmips/conf/files.sbmips
     62       1.2  simonb # Bogus RTC attachment
     63       1.4  simonb device	xirtc
     64       1.4  simonb attach	xirtc at smbus
     65       1.4  simonb 
     66       1.5  simonb device	m41t81rtc
     67       1.5  simonb attach	m41t81rtc at smbus
     68       1.4  simonb 
     69  1.7.48.1  martin # XXX move to arch/mips/sibyte?
     70  1.7.48.1  martin file	arch/evbmips/sbmips/rtc.c		xirtc | m41t81rtc
     71       1.7    matt 
     72       1.7    matt file	arch/mips/sibyte/dev/sbbuswatch.c
     73