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files.sibyte revision 1.1.8.2 
      1 ###
      2 ### SBMIPS DEVICES
      3 ###
      4 
      5 # System Control/Debug
      6 device	sbscd {[offset = -1], [intr[2] = {-1,-1}]}
      7 attach	sbscd at zbbus
      8 file	arch/mips/sibyte/dev/sbscd.c		sbscd
      9 
     10 # On-board I/O (slow I/O bridge)
     11 device	sbobio {[offset = -1], [intr[2] = {-1,-1}]}
     12 attach	sbobio at zbbus
     13 file	arch/mips/sibyte/dev/sbobio.c		sbobio
     14 
     15 # Generic bus, hang off of sbobio
     16 device	sbgbus {[chipsel = -1], [offset = 0], [intr[2] = {-1,-1}]}
     17 attach	sbgbus at sbobio
     18 file	arch/mips/sibyte/dev/sbgbus.c		sbgbus
     19 
     20 # I/O Bridge Zero attachment to ZBbus
     21 device	sbbrz: pcibus
     22 attach	sbbrz at zbbus
     23 file	arch/mips/sibyte/pci/sbbrz.c		sbbrz
     24 file	arch/mips/sibyte/pci/sbbrz_pci.c	sbbrz
     25 
     26 # Instantiated SB-1250 PCI Host bridge
     27 device	sbpcihb
     28 attach	sbpcihb at pci
     29 file	arch/mips/sibyte/pci/sbpcihb.c		sbpcihb
     30 
     31 # SB-1250 LDT Host bridge (acts like ppb)
     32 device	sbldthb: pcibus
     33 attach	sbldthb at pci
     34 file	arch/mips/sibyte/pci/sbldthb.c		sbldthb
     35 
     36 # sbscd children
     37 
     38 device	sbtimer
     39 attach	sbtimer at sbscd
     40 file	arch/mips/sibyte/dev/sbtimer.c		sbtimer
     41 
     42 device	sbwdog
     43 attach	sbwdog at sbscd
     44 file	arch/mips/sibyte/dev/sbwdog.c		sbwdog
     45 
     46 # sbobio children
     47 
     48 # SB1250 MAC (XXX: maybe add mii_bitbang?)
     49 device	sbmac: arp, ether, ifnet, mii, mii_bitbang
     50 attach	sbmac at sbobio
     51 file	arch/mips/sibyte/dev/sbmac.c		sbmac
     52 
     53 # SB1250 built-in (asynchronous) serial ports
     54 device	sbscn: tty
     55 attach	sbscn at sbobio
     56 file	arch/mips/sibyte/dev/sbscn.c		sbscn	needs-flag
     57 
     58