cache_r5900.h revision 1.5
1 /* $NetBSD: cache_r5900.h,v 1.5 2005/12/24 20:07:19 perry Exp $ */ 2 3 /*- 4 * Copyright (c) 2001 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by UCHIYAMA Yasushi. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 #define CACHE_R5900_SIZE_I 16384 40 #define CACHE_R5900_SIZE_D 8192 41 42 #define CACHE_R5900_LSIZE_I 64 43 #define CACHE_R5900_LSIZE_D 64 44 45 #define CACHEOP_R5900_IINV_I 0x07 /* INDEX INVALIDATE */ 46 #define CACHEOP_R5900_HINV_I 0x0b /* HIT INVALIDATE */ 47 #define CACHEOP_R5900_IWBINV_D 0x14 48 /* INDEX WRITE BACK INVALIDATE */ 49 #define CACHEOP_R5900_ILTG_D 0x10 /* INDEX LOAD TAG */ 50 #define CACHEOP_R5900_ISTG_D 0x12 /* INDEX STORE TAG */ 51 #define CACHEOP_R5900_IINV_D 0x16 /* INDEX INVALIDATE */ 52 #define CACHEOP_R5900_HINV_D 0x1a /* HIT INVALIDATE */ 53 #define CACHEOP_R5900_HWBINV_D 0x18 /* HIT WRITEBACK INVALIDATE */ 54 #define CACHEOP_R5900_ILDT_D 0x11 /* INDEX LOAD DATA */ 55 #define CACHEOP_R5900_ISDT_D 0x13 /* INDEX STORE DATA */ 56 #define CACHEOP_R5900_HWB_D 0x1c 57 /* HIT WRITEBACK W/O INVALIDATE */ 58 59 #if !defined(_LOCORE) 60 61 #define cache_op_r5900_line_64(va, op) \ 62 do { \ 63 __asm volatile( \ 64 ".set noreorder \n\t" \ 65 "sync.l \n\t" \ 66 "sync.p \n\t" \ 67 "cache %1, 0(%0) \n\t" \ 68 "sync.l \n\t" \ 69 "sync.p \n\t" \ 70 ".set reorder" \ 71 : \ 72 : "r" (va), "i" (op) \ 73 : "memory"); \ 74 } while (/*CONSTCOND*/0) 75 76 #define cache_r5900_op_4lines_64(va, op) \ 77 do { \ 78 __asm volatile( \ 79 ".set noreorder \n\t" \ 80 "sync.l \n\t" \ 81 "sync.p \n\t" \ 82 "cache %1, 0(%0) \n\t" \ 83 "sync.l \n\t" \ 84 "sync.p \n\t" \ 85 "cache %1, 64(%0) \n\t" \ 86 "sync.l \n\t" \ 87 "sync.p \n\t" \ 88 "cache %1, 128(%0) \n\t" \ 89 "sync.l \n\t" \ 90 "sync.p \n\t" \ 91 "cache %1, 192(%0) \n\t" \ 92 "sync.l \n\t" \ 93 "sync.p \n\t" \ 94 ".set reorder" \ 95 : \ 96 : "r" (va), "i" (op) \ 97 : "memory"); \ 98 } while (/*CONSTCOND*/0) 99 100 #define cache_r5900_op_4lines_64_2way(va, op) \ 101 do { \ 102 __asm volatile( \ 103 ".set noreorder \n\t" \ 104 "sync.l \n\t" \ 105 "sync.p \n\t" \ 106 "cache %1, 0(%0) \n\t" \ 107 "sync.l \n\t" \ 108 "sync.p \n\t" \ 109 "cache %1, 1(%0) \n\t" \ 110 "sync.l \n\t" \ 111 "sync.p \n\t" \ 112 "cache %1, 64(%0) \n\t" \ 113 "sync.l \n\t" \ 114 "sync.p \n\t" \ 115 "cache %1, 65(%0) \n\t" \ 116 "sync.l \n\t" \ 117 "sync.p \n\t" \ 118 "cache %1, 128(%0) \n\t" \ 119 "sync.l \n\t" \ 120 "sync.p \n\t" \ 121 "cache %1, 129(%0) \n\t" \ 122 "sync.l \n\t" \ 123 "sync.p \n\t" \ 124 "cache %1, 192(%0) \n\t" \ 125 "sync.l \n\t" \ 126 "sync.p \n\t" \ 127 "cache %1, 193(%0) \n\t" \ 128 "sync.l \n\t" \ 129 "sync.p \n\t" \ 130 ".set reorder" \ 131 : \ 132 : "r" (va), "i" (op) \ 133 : "memory"); \ 134 } while (/*CONSTCOND*/0) 135 136 void r5900_icache_sync_all_64(void); 137 void r5900_icache_sync_range_64(vaddr_t, vsize_t); 138 void r5900_icache_sync_range_index_64(vaddr_t, vsize_t); 139 140 void r5900_pdcache_wbinv_all_64(void); 141 void r5900_pdcache_wbinv_range_64(vaddr_t, vsize_t); 142 void r5900_pdcache_wbinv_range_index_64(vaddr_t, vsize_t); 143 144 void r5900_pdcache_inv_range_64(vaddr_t, vsize_t); 145 void r5900_pdcache_wb_range_64(vaddr_t, vsize_t); 146 147 #endif /* !_LOCORE */ 148
Indexes created Sat Sep 27 14:09:57 GMT 2025