cpuregs.h revision 1.10
1 /* $NetBSD: cpuregs.h,v 1.10 1997/06/16 07:41:08 jonathan Exp $ */ 2 3 /* 4 * Copyright (c) 1992, 1993 5 * The Regents of the University of California. All rights reserved. 6 * 7 * This code is derived from software contributed to Berkeley by 8 * Ralph Campbell and Rick Macklem. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the University of 21 * California, Berkeley and its contributors. 22 * 4. Neither the name of the University nor the names of its contributors 23 * may be used to endorse or promote products derived from this software 24 * without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 27 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 28 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 29 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 30 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 31 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 32 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 33 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 34 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 35 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 36 * SUCH DAMAGE. 37 * 38 * @(#)machConst.h 8.1 (Berkeley) 6/10/93 39 * 40 * machConst.h -- 41 * 42 * Machine dependent constants. 43 * 44 * Copyright (C) 1989 Digital Equipment Corporation. 45 * Permission to use, copy, modify, and distribute this software and 46 * its documentation for any purpose and without fee is hereby granted, 47 * provided that the above copyright notice appears in all copies. 48 * Digital Equipment Corporation makes no representations about the 49 * suitability of this software for any purpose. It is provided "as is" 50 * without express or implied warranty. 51 * 52 * from: Header: /sprite/src/kernel/mach/ds3100.md/RCS/machConst.h, 53 * v 9.2 89/10/21 15:55:22 jhh Exp SPRITE (DECWRL) 54 * from: Header: /sprite/src/kernel/mach/ds3100.md/RCS/machAddrs.h, 55 * v 1.2 89/08/15 18:28:21 rab Exp SPRITE (DECWRL) 56 * from: Header: /sprite/src/kernel/vm/ds3100.md/RCS/vmPmaxConst.h, 57 * v 9.1 89/09/18 17:33:00 shirriff Exp SPRITE (DECWRL) 58 */ 59 60 #ifndef _MIPS_CPUREGS_H_ 61 #define _MIPS_CPUREGS_H_ 62 63 #define MACH_KUSEG_ADDR 0x0 64 #define MACH_CACHED_MEMORY_ADDR 0x80000000 65 #define MACH_UNCACHED_MEMORY_ADDR 0xa0000000 66 #define MACH_KSEG2_ADDR 0xc0000000 67 #define MACH_MAX_MEM_ADDR 0xbe000000 68 #define MACH_RESERVED_ADDR 0xbfc80000 69 70 #define MACH_CACHED_TO_PHYS(x) ((unsigned)(x) & 0x1fffffff) 71 #define MACH_PHYS_TO_CACHED(x) ((unsigned)(x) | MACH_CACHED_MEMORY_ADDR) 72 #define MACH_UNCACHED_TO_PHYS(x) ((unsigned)(x) & 0x1fffffff) 73 #define MACH_PHYS_TO_UNCACHED(x) ((unsigned)(x) | MACH_UNCACHED_MEMORY_ADDR) 74 75 /* Map virtual address to index in r4k virtually-indexed cache */ 76 #define MIPS_R4K_VA_TO_CINDEX(x) \ 77 ((unsigned)(x) & 0xffffff | MACH_CACHED_MEMORY_ADDR) 78 79 /* XXX compatibility with Pica port */ 80 #define MACH_VA_TO_CINDEX(x) MIPS_R4K_VA_TO_CINDEX(x) 81 82 83 /* 84 * The bits in the cause register. 85 * 86 * Bits common to r3000 and r4000: 87 * 88 * MACH_CR_BR_DELAY Exception happened in branch delay slot. 89 * MACH_CR_COP_ERR Coprocessor error. 90 * MACH_CR_IP Interrupt pending bits defined below. 91 * (same meaning as in CAUSE register). 92 * MACH_CR_EXC_CODE The exception type (see exception codes below). 93 * 94 * Differences: 95 * r3k has 4 bits of execption type, r4k has 5 bits. 96 */ 97 #define MACH_CR_BR_DELAY 0x80000000 98 #define MACH_CR_COP_ERR 0x30000000 99 #define MIPS1_CR_EXC_CODE 0x0000003C /* four bits */ 100 #define MIPS3_CR_EXC_CODE 0x0000007C /* five bits */ 101 #define MACH_CR_IP 0x0000FF00 102 #define MACH_CR_EXC_CODE_SHIFT 2 103 104 #ifdef MIPS3 /* XXX not used any more, only to satisfy regression tests */ 105 #define MACH_CR_EXC_CODE MIPS3_CR_EXC_CODE 106 #else 107 #define MACH_CR_EXC_CODE MIPS1_CR_EXC_CODE 108 #endif /* MIPs3 */ 109 110 /* 111 * The bits in the status register. All bits are active when set to 1. 112 * 113 * R3000 status register fields: 114 * MACH_SR_CO_USABILITY Control the usability of the four coprocessors. 115 * MACH_SR_BOOT_EXC_VEC Use alternate exception vectors. 116 * MACH_SR_TLB_SHUTDOWN TLB disabled. 117 * 118 * MIPS_SR_INT_IE Master (current) interrupt enable bit. 119 * 120 * Differences: 121 * r3k has cache control is via frobbing SR register bits, whereas the 122 * r4k cache control is via explicit instructions. 123 * r3k has a 3-entry stack of kernel/user bits, whereas the 124 * r4k has kernel/supervisor/user. 125 */ 126 #define MACH_SR_COP_USABILITY 0xf0000000 127 #define MACH_SR_COP_0_BIT 0x10000000 128 #define MACH_SR_COP_1_BIT 0x20000000 129 130 /* r4k and r3k differences, see below */ 131 132 #define MACH_SR_BOOT_EXC_VEC 0x00400000 133 #define MACH_SR_TLB_SHUTDOWN 0x00200000 134 135 /* r4k and r3k differences, see below */ 136 137 #define MIPS_SR_INT_IE 0x00000001 138 /*#define MACH_SR_MBZ 0x0f8000c0*/ /* Never used, true for r3k */ 139 /*#define MACH_SR_INT_MASK 0x0000ff00*/ 140 141 #define MACH_SR_INT_ENAB MIPS_SR_INT_IE /* backwards compatibility */ 142 #define MACH_SR_INT_ENA_CUR MIPS_SR_INT_IE /* backwards compatibility */ 143 144 145 146 /* 147 * The R2000/R3000-specific status register bit definitions. 148 * all bits are active when set to 1. 149 * 150 * MACH_SR_PARITY_ERR Parity error. 151 * MACH_SR_CACHE_MISS Most recent D-cache load resulted in a miss. 152 * MACH_SR_PARITY_ZERO Zero replaces outgoing parity bits. 153 * MACH_SR_SWAP_CACHES Swap I-cache and D-cache. 154 * MACH_SR_ISOL_CACHES Isolate D-cache from main memory. 155 * Interrupt enable bits defined below. 156 * MACH_SR_KU_OLD Old kernel/user mode bit. 1 => user mode. 157 * MACH_SR_INT_ENA_OLD Old interrupt enable bit. 158 * MACH_SR_KU_PREV Previous kernel/user mode bit. 1 => user mode. 159 * MACH_SR_INT_ENA_PREV Previous interrupt enable bit. 160 * MACH_SR_KU_CUR Current kernel/user mode bit. 1 => user mode. 161 */ 162 163 #define MIPS_3K_PARITY_ERR 0x00100000 164 #define MIPS_3K_CACHE_MISS 0x00080000 165 #define MIPS_3K_PARITY_ZERO 0x00040000 166 #define MIPS_3K_SWAP_CACHES 0x00020000 167 #define MIPS_3K_ISOL_CACHES 0x00010000 168 169 #define MIPS_3K_SR_KU_OLD 0x00000020 /* 2nd stacked KU/IE*/ 170 #define MIPS_3K_SR_INT_ENA_OLD 0x00000010 /* 2nd stacked KU/IE*/ 171 #define MIPS1_SR_KU_PREV 0x00000008 /* 1st stacked KU/IE*/ 172 #define MIPS1_SR_INT_ENA_PREV 0x00000004 /* 1st stacked KU/IE*/ 173 #define MIPS_3K_SR_KU_CUR 0x00000002 /* current KU */ 174 175 /* backwards compatibility */ 176 #define MACH_SR_PARITY_ERR MIPS_3K_PARITY_ERR 177 #define MACH_SR_CACHE_MISS MIPS_3K_CACHE_MISS 178 #define MACH_SR_PARITY_ZERO MIPS_3K_PARITY_ZERO 179 #define MACH_SR_SWAP_CACHES MIPS_3K_SWAP_CACHES 180 #define MACH_SR_ISOL_CACHES MIPS_3K_ISOL_CACHES 181 182 #define MACH_SR_KU_OLD MIPS_3K_SR_KU_OLD 183 #define MACH_SR_INT_ENA_OLD MIPS_3K_SR_INT_ENA_OLD 184 #define MACH_SR_KU_PREV MIPS1_SR_KU_PREV 185 #define MACH_SR_KU_CUR MIPS_3K_SR_KU_CUR 186 #define MACH_SR_INT_ENA_PREV MIPS1_SR_INT_ENA_PREV 187 188 /* 189 * R4000 status register bit definitons, 190 * where different from r2000/r3000. 191 */ 192 #define MIPS_4K_SR_RP 0x08000000 193 #define MIPS_4K_SR_FR_32 0x04000000 194 #define MIPS_4K_SR_RE 0x02000000 195 196 #define MIPS_4K_SR_SOFT_RESET 0x00100000 197 #define MIPS_4K_SR_DIAG_CH 0x00040000 198 #define MIPS_4K_SR_DIAG_CE 0x00020000 199 #define MIPS_4K_SR_DIAG_PE 0x00010000 200 #define MIPS_4K_SR_KX 0x00000080 201 #define MIPS_4K_SR_SX 0x00000040 202 #define MIPS_4K_SR_UX 0x00000020 203 #define MIPS_4K_SR_KSU_MASK 0x00000018 204 #define MIPS3_SR_KSU_USER 0x00000010 205 #define MIPS_4K_SR_KSU_SUPER 0x00000008 206 #define MIPS_4K_SR_KSU_KERNEL 0x00000000 207 #define MIPS_4K_SR_ERL 0x00000004 208 #define MIPS_4K_SR_EXL 0x00000002 209 210 /* backwards compatibility with names used in Pica port */ 211 #define MACH_SR_RP MIPS_4K_SR_RP 212 #define MACH_SR_FR_32 MIPS_4K_SR_FR_32 213 #define MACH_SR_RE MIPS_4K_SR_RE 214 215 #define MACH_SR_SOFT_RESET MIPS_4K_SR_SOFT_RESET 216 #define MACH_SR_DIAG_CH MIPS_4K_SR_DIAG_CH 217 #define MACH_SR_DIAG_CE MIPS_4K_SR_DIAG_CE 218 #define MACH_SR_DIAG_PE MIPS_4K_SR_DIAG_PE 219 #define MACH_SR_KX MIPS_4K_SR_KX 220 #define MACH_SR_SX MIPS_4K_SR_SX 221 #define MACH_SR_UX MIPS_4K_SR_UX 222 223 #define MACH_SR_KSU_MASK MIPS_4K_SR_KSU_MASK 224 #define MACH_SR_KSU_USER MIPS3_SR_KSU_USER 225 #define MACH_SR_KSU_SUPER MIPS_4K_SR_KSU_SUPER 226 #define MACH_SR_KSU_KERNEL MIPS_4K_SR_KSU_KERNEL 227 #define MACH_SR_ERL MIPS_4K_SR_ERL 228 #define MACH_SR_EXL MIPS_4K_SR_EXL 229 230 231 /* 232 * The interrupt masks. 233 * If a bit in the mask is 1 then the interrupt is enabled (or pending). 234 */ 235 #define MIPS_INT_MASK 0xff00 236 #define MACH_INT_MASK_5 0x8000 237 #define MACH_INT_MASK_4 0x4000 238 #define MACH_INT_MASK_3 0x2000 239 #define MACH_INT_MASK_2 0x1000 240 #define MACH_INT_MASK_1 0x0800 241 #define MACH_INT_MASK_0 0x0400 242 #define MIPS_HARD_INT_MASK 0xfc00 243 #define MACH_SOFT_INT_MASK_1 0x0200 244 #define MACH_SOFT_INT_MASK_0 0x0100 245 246 247 /* 248 * nesting interrupt masks. 249 */ 250 #define MACH_INT_MASK_SPL_SOFT0 MACH_SOFT_INT_MASK_0 251 #define MACH_INT_MASK_SPL_SOFT1 (MACH_SOFT_INT_MASK_1|MACH_INT_MASK_SPL_SOFT0) 252 #define MACH_INT_MASK_SPL0 (MACH_INT_MASK_0|MACH_INT_MASK_SPL_SOFT1) 253 #define MACH_INT_MASK_SPL1 (MACH_INT_MASK_1|MACH_INT_MASK_SPL0) 254 #define MACH_INT_MASK_SPL2 (MACH_INT_MASK_2|MACH_INT_MASK_SPL1) 255 #define MACH_INT_MASK_SPL3 (MACH_INT_MASK_3|MACH_INT_MASK_SPL2) 256 #define MACH_INT_MASK_SPL4 (MACH_INT_MASK_4|MACH_INT_MASK_SPL3) 257 #define MACH_INT_MASK_SPL5 (MACH_INT_MASK_5|MACH_INT_MASK_SPL4) 258 259 260 #ifdef MIPS3 261 /* r4000 has on-chip timer at INT_MASK_5 */ 262 #define MACH_INT_MASK (MIPS_INT_MASK & ~MACH_INT_MASK_5) 263 #define MACH_HARD_INT_MASK (MIPS_HARD_INT_MASK & ~MACH_INT_MASK_5) 264 #else 265 #define MACH_INT_MASK MIPS_INT_MASK 266 #define MACH_HARD_INT_MASK MIPS_HARD_INT_MASK 267 #endif 268 269 /* 270 * The bits in the context register. 271 */ 272 #define MIPS_3K_CNTXT_PTE_BASE 0xFFE00000 273 #define MIPS_3K_CNTXT_BAD_VPN 0x001FFFFC 274 275 #define MIPS_4K_CNTXT_PTE_BASE 0xFF800000 276 #define MIPS_4K_CNTXT_BAD_VPN2 0x007FFFF0 277 278 /* 279 * Backwards compatbility -- XXX more thought 280 */ 281 #ifdef MIPS3 282 #define MACH_CNTXT_PTE_BASE MIPS_4K_CNTXT_PTE_BASE 283 #define MACH_CNTXT_BAD_VPN2 MIPS_4K_CNTXT_BAD_VPN2 284 #else 285 #define MACH_CNTXT_PTE_BASE MIPS_3K_CNTXT_PTE_BASE 286 #define MACH_CNTXT_BAD_VPN MIPS_3K_CNTXT_BAD_VPN 287 #endif 288 289 /* 290 * Location of exception vectors. 291 * 292 * Common vectors: reset and UTLB miss. 293 */ 294 #define MACH_RESET_EXC_VEC 0xBFC00000 295 #define MACH_UTLB_MISS_EXC_VEC 0x80000000 296 297 /* 298 * R3000 general exception vector (everything else) 299 */ 300 #define MIPS1_GEN_EXC_VEC 0x80000080 301 302 /* 303 * R4000 MIPS-III exception vectors 304 */ 305 #define MIPS_4K_XTLB_MISS_EXC_VEC 0x80000080 306 #define MIPS_4K_CACHE_ERR_EXC_VEC 0x80000100 307 #define MIPS3_GEN_EXC_VEC 0x80000180 308 309 /* 310 * Coprocessor 0 registers: 311 * 312 * MACH_COP_0_TLB_INDEX TLB index. 313 * MACH_COP_0_TLB_RANDOM TLB random. 314 * MACH_COP_0_TLB_LOW r3k TLB entry low. 315 * MACH_COP_0_TLB_LO0 r4k TLB entry low. 316 * MACH_COP_0_TLB_LO1 r4k TLB entry low, extended. 317 * MACH_COP_0_TLB_CONTEXT TLB context. 318 * MACH_COP_0_BAD_VADDR Bad virtual address. 319 * MACH_COP_0_TLB_HI TLB entry high. 320 * MACH_COP_0_STATUS_REG Status register. 321 * MACH_COP_0_CAUSE_REG Exception cause register. 322 * MACH_COP_0_EXC_PC Exception PC. 323 * MACH_COP_0_PRID Processor revision identifier. 324 */ 325 #define MACH_COP_0_TLB_INDEX $0 326 #define MACH_COP_0_TLB_RANDOM $1 327 /* Name and meaning of TLB bits for $2 differ on r3k and r4k. */ 328 329 #define MACH_COP_0_TLB_CONTEXT $4 330 /* $5 and $6 new with MIPS-III */ 331 #define MACH_COP_0_BAD_VADDR $8 332 #define MACH_COP_0_TLB_HI $10 333 #define MACH_COP_0_STATUS_REG $12 334 #define MACH_COP_0_CAUSE_REG $13 335 #define MACH_COP_0_EXC_PC $14 336 #define MACH_COP_0_PRID $15 337 338 339 /* r3k-specific */ 340 #define MACH_COP_0_TLB_LOW $2 341 342 /* MIPS-III additions */ 343 #define MACH_COP_0_TLB_LO0 $2 344 #define MACH_COP_0_TLB_LO1 $3 345 346 #define MACH_COP_0_TLB_PG_MASK $5 347 #define MACH_COP_0_TLB_WIRED $6 348 349 #define MACH_COP_0_CONFIG $16 350 #define MACH_COP_0_LLADDR $17 351 #define MACH_COP_0_WATCH_LO $18 352 #define MACH_COP_0_WATCH_HI $19 353 #define MACH_COP_0_TLB_XCONTEXT $20 354 #define MACH_COP_0_ECC $26 355 #define MACH_COP_0_CACHE_ERR $27 356 #define MACH_COP_0_TAG_LO $28 357 #define MACH_COP_0_TAG_HI $29 358 #define MACH_COP_0_ERROR_PC $30 359 360 361 362 /* 363 * Values for the code field in a break instruction. 364 */ 365 #define MACH_BREAK_INSTR 0x0000000d 366 #define MACH_BREAK_VAL_MASK 0x03ff0000 367 #define MACH_BREAK_VAL_SHIFT 16 368 #define MACH_BREAK_KDB_VAL 512 369 #define MACH_BREAK_SSTEP_VAL 513 370 #define MACH_BREAK_BRKPT_VAL 514 371 #define MACH_BREAK_SOVER_VAL 515 372 #define MACH_BREAK_KDB (MACH_BREAK_INSTR | \ 373 (MACH_BREAK_KDB_VAL << MACH_BREAK_VAL_SHIFT)) 374 #define MACH_BREAK_SSTEP (MACH_BREAK_INSTR | \ 375 (MACH_BREAK_SSTEP_VAL << MACH_BREAK_VAL_SHIFT)) 376 #define MACH_BREAK_BRKPT (MACH_BREAK_INSTR | \ 377 (MACH_BREAK_BRKPT_VAL << MACH_BREAK_VAL_SHIFT)) 378 #define MACH_BREAK_SOVER (MACH_BREAK_INSTR | \ 379 (MACH_BREAK_SOVER_VAL << MACH_BREAK_VAL_SHIFT)) 380 381 /* 382 * Mininum and maximum cache sizes. 383 */ 384 #define MACH_MIN_CACHE_SIZE (16 * 1024) 385 #define MACH_MAX_CACHE_SIZE (256 * 1024) 386 387 /* 388 * The floating point version and status registers. 389 */ 390 #define MACH_FPC_ID $0 391 #define MACH_FPC_CSR $31 392 393 /* 394 * The floating point coprocessor status register bits. 395 */ 396 #define MACH_FPC_ROUNDING_BITS 0x00000003 397 #define MACH_FPC_ROUND_RN 0x00000000 398 #define MACH_FPC_ROUND_RZ 0x00000001 399 #define MACH_FPC_ROUND_RP 0x00000002 400 #define MACH_FPC_ROUND_RM 0x00000003 401 #define MACH_FPC_STICKY_BITS 0x0000007c 402 #define MACH_FPC_STICKY_INEXACT 0x00000004 403 #define MACH_FPC_STICKY_UNDERFLOW 0x00000008 404 #define MACH_FPC_STICKY_OVERFLOW 0x00000010 405 #define MACH_FPC_STICKY_DIV0 0x00000020 406 #define MACH_FPC_STICKY_INVALID 0x00000040 407 #define MACH_FPC_ENABLE_BITS 0x00000f80 408 #define MACH_FPC_ENABLE_INEXACT 0x00000080 409 #define MACH_FPC_ENABLE_UNDERFLOW 0x00000100 410 #define MACH_FPC_ENABLE_OVERFLOW 0x00000200 411 #define MACH_FPC_ENABLE_DIV0 0x00000400 412 #define MACH_FPC_ENABLE_INVALID 0x00000800 413 #define MACH_FPC_EXCEPTION_BITS 0x0003f000 414 #define MACH_FPC_EXCEPTION_INEXACT 0x00001000 415 #define MACH_FPC_EXCEPTION_UNDERFLOW 0x00002000 416 #define MACH_FPC_EXCEPTION_OVERFLOW 0x00004000 417 #define MACH_FPC_EXCEPTION_DIV0 0x00008000 418 #define MACH_FPC_EXCEPTION_INVALID 0x00010000 419 #define MACH_FPC_EXCEPTION_UNIMPL 0x00020000 420 #define MACH_FPC_COND_BIT 0x00800000 421 #define MACH_FPC_FLUSH_BIT 0x01000000 /* r4k, MBZ on r3k */ 422 #define MIPS_3K_FPC_MBZ_BITS 0xff7c0000 423 #define MIPS_4K_FPC_MBZ_BITS 0xfe7c0000 424 425 426 /* 427 * Constants to determine if have a floating point instruction. 428 */ 429 #define MACH_OPCODE_SHIFT 26 430 #define MACH_OPCODE_C1 0x11 431 432 433 434 /* 435 * The low part of the TLB entry. 436 */ 437 #define VMMACH_MIPS_3K_TLB_PHYS_PAGE_SHIFT 12 438 #define VMMACH_MIPS_3K_TLB_PF_NUM 0xfffff000 439 #define VMMACH_MIPS_3K_TLB_NON_CACHEABLE_BIT 0x00000800 440 #define VMMACH_MIPS_3K_TLB_MOD_BIT 0x00000400 441 #define VMMACH_MIPS_3K_TLB_VALID_BIT 0x00000200 442 #define VMMACH_MIPS_3K_TLB_GLOBAL_BIT 0x00000100 443 444 #define VMMACH_MIPS_4K_TLB_PHYS_PAGE_SHIFT 6 445 #define VMMACH_MIPS_4K_TLB_PF_NUM 0x3fffffc0 446 #define VMMACH_MIPS_4K_TLB_ATTR_MASK 0x00000038 447 #define VMMACH_MIPS_4K_TLB_MOD_BIT 0x00000004 448 #define VMMACH_MIPS_4K_TLB_VALID_BIT 0x00000002 449 #define VMMACH_MIPS_4K_TLB_GLOBAL_BIT 0x00000001 450 451 452 #ifdef MIPS3 453 #define VMMACH_TLB_PHYS_PAGE_SHIFT VMMACH_MIPS_4K_TLB_PHYS_PAGE_SHIFT 454 #define VMMACH_TLB_PF_NUM VMMACH_MIPS_4K_TLB_PF_NUM 455 #define VMMACH_TLB_ATTR_MASK VMMACH_MIPS_4K_TLB_ATTR_MASK 456 #define VMMACH_TLB_MOD_BIT VMMACH_MIPS_4K_TLB_MOD_BIT 457 #define VMMACH_TLB_VALID_BIT VMMACH_MIPS_4K_TLB_VALID_BIT 458 #define VMMACH_TLB_GLOBAL_BIT VMMACH_MIPS_4K_TLB_GLOBAL_BIT 459 #else 460 #define VMMACH_TLB_PHYS_PAGE_SHIFT VMMACH_MIPS_3K_TLB_PHYS_PAGE_SHIFT 461 #define VMMACH_TLB_PF_NUM VMMACH_MIPS_3K_TLB_PF_NUM 462 #define VMMACH_TLB_NON_CACHEABLE_BIT VMMACH_MIPS_3K_TLB_NON_CACHEABLE_BIT 463 #define VMMACH_TLB_MOD_BIT VMMACH_MIPS_3K_TLB_MOD_BIT 464 #define VMMACH_TLB_VALID_BIT VMMACH_MIPS_3K_TLB_VALID_BIT 465 #define VMMACH_TLB_GLOBAL_BIT VMMACH_MIPS_3K_TLB_GLOBAL_BIT 466 #endif 467 468 /* 469 * The high part of the TLB entry. 470 */ 471 #define VMMACH_TLB_VIRT_PAGE_SHIFT 12 472 473 #define VMMACH_TLB_MIPS_3K_VIRT_PAGE_NUM 0xfffff000 474 #define VMMACH_TLB_MIPS_3K_PID 0x00000fc0 475 #define VMMACH_TLB_MIPS_3K_PID_SHIFT 6 476 477 #define VMMACH_TLB_MIPS_4K_VIRT_PAGE_NUM 0xffffe000 478 #define VMMACH_TLB_MIPS_4K_PID 0x000000ff 479 #define VMMACH_TLB_MIPS_4K_PID_SHIFT 0 480 481 /* XXX needs more thought */ 482 /* 483 * backwards XXX needs more thought, should support runtime decisions. 484 */ 485 486 #ifdef MIPS3 487 #define VMMACH_TLB_VIRT_PAGE_NUM VMMACH_TLB_MIPS_4K_VIRT_PAGE_NUM 488 #define VMMACH_TLB_PID VMMACH_TLB_MIPS_4K_PID 489 #define VMMACH_TLB_PID_SHIFT VMMACH_TLB_MIPS_4K_PID_SHIFT 490 #else 491 #define VMMACH_TLB_VIRT_PAGE_NUM VMMACH_TLB_MIPS_3K_VIRT_PAGE_NUM 492 #define VMMACH_TLB_PID VMMACH_TLB_MIPS_3K_PID 493 #define VMMACH_TLB_PID_SHIFT VMMACH_TLB_MIPS_3K_PID_SHIFT 494 #endif 495 496 /* 497 * r3000: shift count to put the index in the right spot. 498 * (zero on r4000?) 499 */ 500 #define VMMACH_TLB_INDEX_SHIFT 8 501 502 503 /* 504 * The number of TLB entries and the first one that write random hits. 505 */ 506 #define VMMACH_MIPS_3K_NUM_TLB_ENTRIES 64 507 #define VMMACH_MIPS_3K_FIRST_RAND_ENTRY 8 508 509 #define VMMACH_MIPS_4K_NUM_TLB_ENTRIES 48 510 #define VMMACH_MIPS_4K_WIRED_ENTRIES 8 511 512 /* compatibility with existing locore -- XXX more thought */ 513 #ifdef MIPS3 514 #define VMMACH_NUM_TLB_ENTRIES VMMACH_MIPS_4K_NUM_TLB_ENTRIES 515 #define VMMACH_WIRED_ENTRIES VMMACH_MIPS_4K_WIRED_ENTRIES 516 #else 517 #define VMMACH_NUM_TLB_ENTRIES VMMACH_MIPS_3K_NUM_TLB_ENTRIES 518 #endif 519 #define VMMACH_FIRST_RAND_ENTRY VMMACH_MIPS_3K_FIRST_RAND_ENTRY 520 521 /* 522 * The number of process id entries. 523 */ 524 #define VMMACH_MIPS_3K_NUM_PIDS 64 525 #define VMMACH_MIPS_4K_NUM_PIDS 256 526 527 #ifdef MIPS3 528 #define VMMACH_NUM_PIDS VMMACH_MIPS_4K_NUM_PIDS 529 #else 530 #define VMMACH_NUM_PIDS VMMACH_MIPS_3K_NUM_PIDS 531 #endif 532 533 /* 534 * TLB probe return codes. 535 */ 536 #define VMMACH_TLB_NOT_FOUND 0 537 #define VMMACH_TLB_FOUND 1 538 #define VMMACH_TLB_FOUND_WITH_PATCH 2 539 #define VMMACH_TLB_PROBE_ERROR 3 540 541 #endif /* _MIPS_CPUREGS_H_ */ 542
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