cpuregs.h revision 1.12
1 /* $NetBSD: cpuregs.h,v 1.12 1997/06/22 03:17:40 jonathan Exp $ */ 2 3 /* 4 * Copyright (c) 1992, 1993 5 * The Regents of the University of California. All rights reserved. 6 * 7 * This code is derived from software contributed to Berkeley by 8 * Ralph Campbell and Rick Macklem. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the University of 21 * California, Berkeley and its contributors. 22 * 4. Neither the name of the University nor the names of its contributors 23 * may be used to endorse or promote products derived from this software 24 * without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 27 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 28 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 29 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 30 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 31 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 32 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 33 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 34 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 35 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 36 * SUCH DAMAGE. 37 * 38 * @(#)machConst.h 8.1 (Berkeley) 6/10/93 39 * 40 * machConst.h -- 41 * 42 * Machine dependent constants. 43 * 44 * Copyright (C) 1989 Digital Equipment Corporation. 45 * Permission to use, copy, modify, and distribute this software and 46 * its documentation for any purpose and without fee is hereby granted, 47 * provided that the above copyright notice appears in all copies. 48 * Digital Equipment Corporation makes no representations about the 49 * suitability of this software for any purpose. It is provided "as is" 50 * without express or implied warranty. 51 * 52 * from: Header: /sprite/src/kernel/mach/ds3100.md/RCS/machConst.h, 53 * v 9.2 89/10/21 15:55:22 jhh Exp SPRITE (DECWRL) 54 * from: Header: /sprite/src/kernel/mach/ds3100.md/RCS/machAddrs.h, 55 * v 1.2 89/08/15 18:28:21 rab Exp SPRITE (DECWRL) 56 * from: Header: /sprite/src/kernel/vm/ds3100.md/RCS/vmPmaxConst.h, 57 * v 9.1 89/09/18 17:33:00 shirriff Exp SPRITE (DECWRL) 58 */ 59 60 #ifndef _MIPS_CPUREGS_H_ 61 #define _MIPS_CPUREGS_H_ 62 63 #define MACH_KUSEG_ADDR 0x0 64 #define MACH_CACHED_MEMORY_ADDR 0x80000000 65 #define MACH_UNCACHED_MEMORY_ADDR 0xa0000000 66 #define MACH_KSEG2_ADDR 0xc0000000 67 #define MACH_MAX_MEM_ADDR 0xbe000000 68 #define MACH_RESERVED_ADDR 0xbfc80000 69 70 #define MACH_CACHED_TO_PHYS(x) ((unsigned)(x) & 0x1fffffff) 71 #define MACH_PHYS_TO_CACHED(x) ((unsigned)(x) | MACH_CACHED_MEMORY_ADDR) 72 #define MACH_UNCACHED_TO_PHYS(x) ((unsigned)(x) & 0x1fffffff) 73 #define MACH_PHYS_TO_UNCACHED(x) ((unsigned)(x) | MACH_UNCACHED_MEMORY_ADDR) 74 75 /* Map virtual address to index in r4k virtually-indexed cache */ 76 #define MIPS_R4K_VA_TO_CINDEX(x) \ 77 ((unsigned)(x) & 0xffffff | MACH_CACHED_MEMORY_ADDR) 78 79 /* XXX compatibility with Pica port */ 80 #define MACH_VA_TO_CINDEX(x) MIPS_R4K_VA_TO_CINDEX(x) 81 82 83 /* 84 * The bits in the cause register. 85 * 86 * Bits common to r3000 and r4000: 87 * 88 * MACH_CR_BR_DELAY Exception happened in branch delay slot. 89 * MACH_CR_COP_ERR Coprocessor error. 90 * MACH_CR_IP Interrupt pending bits defined below. 91 * (same meaning as in CAUSE register). 92 * MACH_CR_EXC_CODE The exception type (see exception codes below). 93 * 94 * Differences: 95 * r3k has 4 bits of execption type, r4k has 5 bits. 96 */ 97 #define MACH_CR_BR_DELAY 0x80000000 98 #define MACH_CR_COP_ERR 0x30000000 99 #define MIPS1_CR_EXC_CODE 0x0000003C /* four bits */ 100 #define MIPS3_CR_EXC_CODE 0x0000007C /* five bits */ 101 #define MACH_CR_IP 0x0000FF00 102 #define MACH_CR_EXC_CODE_SHIFT 2 103 104 /* 105 * The bits in the status register. All bits are active when set to 1. 106 * 107 * R3000 status register fields: 108 * MACH_SR_CO_USABILITY Control the usability of the four coprocessors. 109 * MACH_SR_BOOT_EXC_VEC Use alternate exception vectors. 110 * MACH_SR_TLB_SHUTDOWN TLB disabled. 111 * 112 * MIPS_SR_INT_IE Master (current) interrupt enable bit. 113 * 114 * Differences: 115 * r3k has cache control is via frobbing SR register bits, whereas the 116 * r4k cache control is via explicit instructions. 117 * r3k has a 3-entry stack of kernel/user bits, whereas the 118 * r4k has kernel/supervisor/user. 119 */ 120 #define MACH_SR_COP_USABILITY 0xf0000000 121 #define MACH_SR_COP_0_BIT 0x10000000 122 #define MACH_SR_COP_1_BIT 0x20000000 123 124 /* r4k and r3k differences, see below */ 125 126 #define MACH_SR_BOOT_EXC_VEC 0x00400000 127 #define MACH_SR_TLB_SHUTDOWN 0x00200000 128 129 /* r4k and r3k differences, see below */ 130 131 #define MIPS_SR_INT_IE 0x00000001 132 /*#define MACH_SR_MBZ 0x0f8000c0*/ /* Never used, true for r3k */ 133 /*#define MACH_SR_INT_MASK 0x0000ff00*/ 134 135 #define MACH_SR_INT_ENAB MIPS_SR_INT_IE /* backwards compatibility */ 136 #define MACH_SR_INT_ENA_CUR MIPS_SR_INT_IE /* backwards compatibility */ 137 138 139 140 /* 141 * The R2000/R3000-specific status register bit definitions. 142 * all bits are active when set to 1. 143 * 144 * MACH_SR_PARITY_ERR Parity error. 145 * MACH_SR_CACHE_MISS Most recent D-cache load resulted in a miss. 146 * MACH_SR_PARITY_ZERO Zero replaces outgoing parity bits. 147 * MACH_SR_SWAP_CACHES Swap I-cache and D-cache. 148 * MACH_SR_ISOL_CACHES Isolate D-cache from main memory. 149 * Interrupt enable bits defined below. 150 * MACH_SR_KU_OLD Old kernel/user mode bit. 1 => user mode. 151 * MACH_SR_INT_ENA_OLD Old interrupt enable bit. 152 * MACH_SR_KU_PREV Previous kernel/user mode bit. 1 => user mode. 153 * MACH_SR_INT_ENA_PREV Previous interrupt enable bit. 154 * MACH_SR_KU_CUR Current kernel/user mode bit. 1 => user mode. 155 */ 156 157 #define MIPS1_PARITY_ERR 0x00100000 158 #define MIPS1_CACHE_MISS 0x00080000 159 #define MIPS1_PARITY_ZERO 0x00040000 160 #define MIPS1_SWAP_CACHES 0x00020000 161 #define MIPS1_ISOL_CACHES 0x00010000 162 163 #define MIPS1_SR_KU_OLD 0x00000020 /* 2nd stacked KU/IE*/ 164 #define MIPS1_SR_INT_ENA_OLD 0x00000010 /* 2nd stacked KU/IE*/ 165 #define MIPS1_SR_KU_PREV 0x00000008 /* 1st stacked KU/IE*/ 166 #define MIPS1_SR_INT_ENA_PREV 0x00000004 /* 1st stacked KU/IE*/ 167 #define MIPS1_SR_KU_CUR 0x00000002 /* current KU */ 168 169 /* backwards compatibility */ 170 #define MACH_SR_PARITY_ERR MIPS1_PARITY_ERR 171 #define MACH_SR_CACHE_MISS MIPS1_CACHE_MISS 172 #define MACH_SR_PARITY_ZERO MIPS1_PARITY_ZERO 173 #define MACH_SR_SWAP_CACHES MIPS1_SWAP_CACHES 174 #define MACH_SR_ISOL_CACHES MIPS1_ISOL_CACHES 175 176 #define MACH_SR_KU_OLD MIPS1_SR_KU_OLD 177 #define MACH_SR_INT_ENA_OLD MIPS1_SR_INT_ENA_OLD 178 #define MACH_SR_KU_PREV MIPS1_SR_KU_PREV 179 #define MACH_SR_KU_CUR MIPS1_SR_KU_CUR 180 #define MACH_SR_INT_ENA_PREV MIPS1_SR_INT_ENA_PREV 181 182 /* 183 * R4000 status register bit definitons, 184 * where different from r2000/r3000. 185 */ 186 #define MIPS3_SR_RP 0x08000000 187 #define MIPS3_SR_FR_32 0x04000000 188 #define MIPS3_SR_RE 0x02000000 189 190 #define MIPS3_SR_SOFT_RESET 0x00100000 191 #define MIPS3_SR_DIAG_CH 0x00040000 192 #define MIPS3_SR_DIAG_CE 0x00020000 193 #define MIPS3_SR_DIAG_PE 0x00010000 194 #define MIPS3_SR_KX 0x00000080 195 #define MIPS3_SR_SX 0x00000040 196 #define MIPS3_SR_UX 0x00000020 197 #define MIPS3_SR_KSU_MASK 0x00000018 198 #define MIPS3_SR_KSU_USER 0x00000010 199 #define MIPS3_SR_KSU_SUPER 0x00000008 200 #define MIPS3_SR_KSU_KERNEL 0x00000000 201 #define MIPS3_SR_ERL 0x00000004 202 #define MIPS3_SR_EXL 0x00000002 203 204 /* backwards compatibility with names used in Pica port */ 205 #define MACH_SR_RP MIPS3_SR_RP 206 #define MACH_SR_FR_32 MIPS3_SR_FR_32 207 #define MACH_SR_RE MIPS3_SR_RE 208 209 #define MACH_SR_SOFT_RESET MIPS3_SR_SOFT_RESET 210 #define MACH_SR_DIAG_CH MIPS3_SR_DIAG_CH 211 #define MACH_SR_DIAG_CE MIPS3_SR_DIAG_CE 212 #define MACH_SR_DIAG_PE MIPS3_SR_DIAG_PE 213 #define MACH_SR_KX MIPS3_SR_KX 214 #define MACH_SR_SX MIPS3_SR_SX 215 #define MACH_SR_UX MIPS3_SR_UX 216 217 #define MACH_SR_KSU_MASK MIPS3_SR_KSU_MASK 218 #define MACH_SR_KSU_USER MIPS3_SR_KSU_USER 219 #define MACH_SR_KSU_SUPER MIPS3_SR_KSU_SUPER 220 #define MACH_SR_KSU_KERNEL MIPS3_SR_KSU_KERNEL 221 #define MACH_SR_ERL MIPS3_SR_ERL 222 #define MACH_SR_EXL MIPS3_SR_EXL 223 224 225 /* 226 * The interrupt masks. 227 * If a bit in the mask is 1 then the interrupt is enabled (or pending). 228 */ 229 #define MIPS_INT_MASK 0xff00 230 #define MACH_INT_MASK_5 0x8000 231 #define MACH_INT_MASK_4 0x4000 232 #define MACH_INT_MASK_3 0x2000 233 #define MACH_INT_MASK_2 0x1000 234 #define MACH_INT_MASK_1 0x0800 235 #define MACH_INT_MASK_0 0x0400 236 #define MIPS_HARD_INT_MASK 0xfc00 237 #define MACH_SOFT_INT_MASK_1 0x0200 238 #define MACH_SOFT_INT_MASK_0 0x0100 239 240 241 /* 242 * nesting interrupt masks. 243 */ 244 #define MACH_INT_MASK_SPL_SOFT0 MACH_SOFT_INT_MASK_0 245 #define MACH_INT_MASK_SPL_SOFT1 (MACH_SOFT_INT_MASK_1|MACH_INT_MASK_SPL_SOFT0) 246 #define MACH_INT_MASK_SPL0 (MACH_INT_MASK_0|MACH_INT_MASK_SPL_SOFT1) 247 #define MACH_INT_MASK_SPL1 (MACH_INT_MASK_1|MACH_INT_MASK_SPL0) 248 #define MACH_INT_MASK_SPL2 (MACH_INT_MASK_2|MACH_INT_MASK_SPL1) 249 #define MACH_INT_MASK_SPL3 (MACH_INT_MASK_3|MACH_INT_MASK_SPL2) 250 #define MACH_INT_MASK_SPL4 (MACH_INT_MASK_4|MACH_INT_MASK_SPL3) 251 #define MACH_INT_MASK_SPL5 (MACH_INT_MASK_5|MACH_INT_MASK_SPL4) 252 253 /* 254 * mips3 CPUs have on-chip timer at INT_MASK_5. We don't support it yet. 255 */ 256 #define MIPS3_INT_MASK (MIPS_INT_MASK & ~MACH_INT_MASK_5) 257 #define MIPS3_HARD_INT_MASK (MIPS_HARD_INT_MASK & ~MACH_INT_MASK_5) 258 259 260 /* 261 * The bits in the context register. 262 */ 263 #define MIPS1_CNTXT_PTE_BASE 0xFFE00000 264 #define MIPS1_CNTXT_BAD_VPN 0x001FFFFC 265 266 #define MIPS3_CNTXT_PTE_BASE 0xFF800000 267 #define MIPS3_CNTXT_BAD_VPN2 0x007FFFF0 268 269 /* 270 * Location of exception vectors. 271 * 272 * Common vectors: reset and UTLB miss. 273 */ 274 #define MACH_RESET_EXC_VEC 0xBFC00000 275 #define MACH_UTLB_MISS_EXC_VEC 0x80000000 276 277 /* 278 * R3000 general exception vector (everything else) 279 */ 280 #define MIPS1_GEN_EXC_VEC 0x80000080 281 282 /* 283 * R4000 MIPS-III exception vectors 284 */ 285 #define MIPS3_XTLB_MISS_EXC_VEC 0x80000080 286 #define MIPS3_CACHE_ERR_EXC_VEC 0x80000100 287 #define MIPS3_GEN_EXC_VEC 0x80000180 288 289 /* 290 * Coprocessor 0 registers: 291 * 292 * MACH_COP_0_TLB_INDEX TLB index. 293 * MACH_COP_0_TLB_RANDOM TLB random. 294 * MACH_COP_0_TLB_LOW r3k TLB entry low. 295 * MACH_COP_0_TLB_LO0 r4k TLB entry low. 296 * MACH_COP_0_TLB_LO1 r4k TLB entry low, extended. 297 * MACH_COP_0_TLB_CONTEXT TLB context. 298 * MACH_COP_0_BAD_VADDR Bad virtual address. 299 * MACH_COP_0_TLB_HI TLB entry high. 300 * MACH_COP_0_STATUS_REG Status register. 301 * MACH_COP_0_CAUSE_REG Exception cause register. 302 * MACH_COP_0_EXC_PC Exception PC. 303 * MACH_COP_0_PRID Processor revision identifier. 304 */ 305 #define MACH_COP_0_TLB_INDEX $0 306 #define MACH_COP_0_TLB_RANDOM $1 307 /* Name and meaning of TLB bits for $2 differ on r3k and r4k. */ 308 309 #define MACH_COP_0_TLB_CONTEXT $4 310 /* $5 and $6 new with MIPS-III */ 311 #define MACH_COP_0_BAD_VADDR $8 312 #define MACH_COP_0_TLB_HI $10 313 #define MACH_COP_0_STATUS_REG $12 314 #define MACH_COP_0_CAUSE_REG $13 315 #define MACH_COP_0_EXC_PC $14 316 #define MACH_COP_0_PRID $15 317 318 319 /* r3k-specific */ 320 #define MACH_COP_0_TLB_LOW $2 321 322 /* MIPS-III additions */ 323 #define MACH_COP_0_TLB_LO0 $2 324 #define MACH_COP_0_TLB_LO1 $3 325 326 #define MACH_COP_0_TLB_PG_MASK $5 327 #define MACH_COP_0_TLB_WIRED $6 328 329 #define MACH_COP_0_CONFIG $16 330 #define MACH_COP_0_LLADDR $17 331 #define MACH_COP_0_WATCH_LO $18 332 #define MACH_COP_0_WATCH_HI $19 333 #define MACH_COP_0_TLB_XCONTEXT $20 334 #define MACH_COP_0_ECC $26 335 #define MACH_COP_0_CACHE_ERR $27 336 #define MACH_COP_0_TAG_LO $28 337 #define MACH_COP_0_TAG_HI $29 338 #define MACH_COP_0_ERROR_PC $30 339 340 341 342 /* 343 * Values for the code field in a break instruction. 344 */ 345 #define MACH_BREAK_INSTR 0x0000000d 346 #define MACH_BREAK_VAL_MASK 0x03ff0000 347 #define MACH_BREAK_VAL_SHIFT 16 348 #define MACH_BREAK_KDB_VAL 512 349 #define MACH_BREAK_SSTEP_VAL 513 350 #define MACH_BREAK_BRKPT_VAL 514 351 #define MACH_BREAK_SOVER_VAL 515 352 #define MACH_BREAK_KDB (MACH_BREAK_INSTR | \ 353 (MACH_BREAK_KDB_VAL << MACH_BREAK_VAL_SHIFT)) 354 #define MACH_BREAK_SSTEP (MACH_BREAK_INSTR | \ 355 (MACH_BREAK_SSTEP_VAL << MACH_BREAK_VAL_SHIFT)) 356 #define MACH_BREAK_BRKPT (MACH_BREAK_INSTR | \ 357 (MACH_BREAK_BRKPT_VAL << MACH_BREAK_VAL_SHIFT)) 358 #define MACH_BREAK_SOVER (MACH_BREAK_INSTR | \ 359 (MACH_BREAK_SOVER_VAL << MACH_BREAK_VAL_SHIFT)) 360 361 /* 362 * Mininum and maximum cache sizes. 363 */ 364 #define MACH_MIN_CACHE_SIZE (16 * 1024) 365 #define MACH_MAX_CACHE_SIZE (256 * 1024) 366 367 /* 368 * The floating point version and status registers. 369 */ 370 #define MACH_FPC_ID $0 371 #define MACH_FPC_CSR $31 372 373 /* 374 * The floating point coprocessor status register bits. 375 */ 376 #define MACH_FPC_ROUNDING_BITS 0x00000003 377 #define MACH_FPC_ROUND_RN 0x00000000 378 #define MACH_FPC_ROUND_RZ 0x00000001 379 #define MACH_FPC_ROUND_RP 0x00000002 380 #define MACH_FPC_ROUND_RM 0x00000003 381 #define MACH_FPC_STICKY_BITS 0x0000007c 382 #define MACH_FPC_STICKY_INEXACT 0x00000004 383 #define MACH_FPC_STICKY_UNDERFLOW 0x00000008 384 #define MACH_FPC_STICKY_OVERFLOW 0x00000010 385 #define MACH_FPC_STICKY_DIV0 0x00000020 386 #define MACH_FPC_STICKY_INVALID 0x00000040 387 #define MACH_FPC_ENABLE_BITS 0x00000f80 388 #define MACH_FPC_ENABLE_INEXACT 0x00000080 389 #define MACH_FPC_ENABLE_UNDERFLOW 0x00000100 390 #define MACH_FPC_ENABLE_OVERFLOW 0x00000200 391 #define MACH_FPC_ENABLE_DIV0 0x00000400 392 #define MACH_FPC_ENABLE_INVALID 0x00000800 393 #define MACH_FPC_EXCEPTION_BITS 0x0003f000 394 #define MACH_FPC_EXCEPTION_INEXACT 0x00001000 395 #define MACH_FPC_EXCEPTION_UNDERFLOW 0x00002000 396 #define MACH_FPC_EXCEPTION_OVERFLOW 0x00004000 397 #define MACH_FPC_EXCEPTION_DIV0 0x00008000 398 #define MACH_FPC_EXCEPTION_INVALID 0x00010000 399 #define MACH_FPC_EXCEPTION_UNIMPL 0x00020000 400 #define MACH_FPC_COND_BIT 0x00800000 401 #define MACH_FPC_FLUSH_BIT 0x01000000 /* r4k, MBZ on r3k */ 402 #define MIPS1_FPC_MBZ_BITS 0xff7c0000 403 #define MIPS3_FPC_MBZ_BITS 0xfe7c0000 404 405 406 /* 407 * Constants to determine if have a floating point instruction. 408 */ 409 #define MACH_OPCODE_SHIFT 26 410 #define MACH_OPCODE_C1 0x11 411 412 413 414 /* 415 * The low part of the TLB entry. 416 */ 417 #define MIPS1_TLB_PHYS_PAGE_SHIFT 12 418 #define MIPS1_TLB_PF_NUM 0xfffff000 419 #define MIPS1_TLB_NON_CACHEABLE_BIT 0x00000800 420 #define MIPS1_TLB_MOD_BIT 0x00000400 421 #define MIPS1_TLB_VALID_BIT 0x00000200 422 #define MIPS1_TLB_GLOBAL_BIT 0x00000100 423 424 #define MIPS3_TLB_PHYS_PAGE_SHIFT 6 425 #define MIPS3_TLB_PF_NUM 0x3fffffc0 426 #define MIPS3_TLB_ATTR_MASK 0x00000038 427 #define MIPS3_TLB_MOD_BIT 0x00000004 428 #define MIPS3_TLB_VALID_BIT 0x00000002 429 #define MIPS3_TLB_GLOBAL_BIT 0x00000001 430 431 432 /* 433 * The high part of the TLB entry. 434 */ 435 #define MIPS_TLB_VIRT_PAGE_SHIFT 12 436 437 #define MIPS1_TLB_VIRT_PAGE_NUM 0xfffff000 438 #define MIPS1_TLB_PID 0x00000fc0 439 #define MIPS1_TLB_PID_SHIFT 6 440 441 #define MIPS3_TLB_VIRT_PAGE_NUM 0xffffe000 442 #define MIPS3_TLB_PID 0x000000ff 443 #define MIPS3_TLB_PID_SHIFT 0 444 445 446 /* 447 * r3000: shift count to put the index in the right spot. 448 * (zero on r4000?) 449 */ 450 #define MIPS1_TLB_INDEX_SHIFT 8 451 452 453 /* 454 * The number of TLB entries and the first one that write random hits. 455 */ 456 #define MIPS1_TLB_NUM_TLB_ENTRIES 64 457 #define MIPS1_TLB_FIRST_RAND_ENTRY 8 458 459 #define MIPS3_TLB_NUM_TLB_ENTRIES 48 460 #define MIPS3_TLB_WIRED_ENTRIES 8 461 462 463 /* 464 * The number of process id entries. 465 */ 466 #define MIPS1_TLB_NUM_PIDS 64 467 #define MIPS3_TLB_NUM_PIDS 256 468 469 /* 470 * backwards compatibility with existing locore and compile-time 471 * mips1/mips3 binding. 472 * 473 * XXX INT_MASK and HARD_INT_MASK are here only because we dont 474 * support the mips3 on-chip timer which is tied to INT_5. 475 */ 476 477 #if defined(MIPS3) && !defined(MIPS1) 478 #define MACH_INT_MASK MIPS3_INT_MASK 479 #define MACH_HARD_INT_MASK MIPS3_HARD_INT_MASK 480 #define MIPS_TLB_PID_SHIFT MIPS3_TLB_PID_SHIFT 481 #define MIPS_TLB_NUM_PIDS MIPS3_TLB_NUM_PIDS 482 #endif 483 484 #if !defined(MIPS3) && defined(MIPS1) 485 #define MACH_INT_MASK MIPS_INT_MASK 486 #define MACH_HARD_INT_MASK MIPS_HARD_INT_MASK 487 #define MIPS_TLB_PID_SHIFT MIPS1_TLB_PID_SHIFT 488 #define MIPS_TLB_NUM_PIDS MIPS1_TLB_NUM_PIDS 489 #endif 490 491 492 #if defined(MIPS1) && defined(MIPS3) 493 #define MACH_INT_MASK MIPS_INT_MASK /* XXX */ 494 #define MACH_HARD_INT_MASK MIPS_HARD_INT_MASK /* XXX */ 495 #define MIPS_TLB_PID_SHIFT \ 496 ((CPUISMIPS3)? MIPS3_TLB_PID_SHIFT : MIPS1_TLB_PID_SHIFT) 497 498 #define MIPS_TLB_NUM_PIDS \ 499 ((CPUISMIPS3)? MIPS3_TLB_NUM_PIDS : MIPS1_TLB_NUM_PIDS) 500 501 #endif 502 503 /* 504 * TLB probe return codes. 505 */ 506 #define MIPS_TLB_NOT_FOUND 0 507 #define MIPS_TLB_FOUND 1 508 #define MIPS_TLB_FOUND_WITH_PATCH 2 509 #define MIPS_TLB_PROBE_ERROR 3 510 511 #endif /* _MIPS_CPUREGS_H_ */ 512
Indexes created Tue Oct 28 12:10:06 GMT 2025