cpuregs.h revision 1.15
1 /* $NetBSD: cpuregs.h,v 1.15 1998/09/11 16:46:31 jonathan Exp $ */ 2 3 /* 4 * Copyright (c) 1992, 1993 5 * The Regents of the University of California. All rights reserved. 6 * 7 * This code is derived from software contributed to Berkeley by 8 * Ralph Campbell and Rick Macklem. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the University of 21 * California, Berkeley and its contributors. 22 * 4. Neither the name of the University nor the names of its contributors 23 * may be used to endorse or promote products derived from this software 24 * without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 27 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 28 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 29 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 30 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 31 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 32 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 33 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 34 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 35 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 36 * SUCH DAMAGE. 37 * 38 * @(#)machConst.h 8.1 (Berkeley) 6/10/93 39 * 40 * machConst.h -- 41 * 42 * Machine dependent constants. 43 * 44 * Copyright (C) 1989 Digital Equipment Corporation. 45 * Permission to use, copy, modify, and distribute this software and 46 * its documentation for any purpose and without fee is hereby granted, 47 * provided that the above copyright notice appears in all copies. 48 * Digital Equipment Corporation makes no representations about the 49 * suitability of this software for any purpose. It is provided "as is" 50 * without express or implied warranty. 51 * 52 * from: Header: /sprite/src/kernel/mach/ds3100.md/RCS/machConst.h, 53 * v 9.2 89/10/21 15:55:22 jhh Exp SPRITE (DECWRL) 54 * from: Header: /sprite/src/kernel/mach/ds3100.md/RCS/machAddrs.h, 55 * v 1.2 89/08/15 18:28:21 rab Exp SPRITE (DECWRL) 56 * from: Header: /sprite/src/kernel/vm/ds3100.md/RCS/vmPmaxConst.h, 57 * v 9.1 89/09/18 17:33:00 shirriff Exp SPRITE (DECWRL) 58 */ 59 60 #ifndef _MIPS_CPUREGS_H_ 61 #define _MIPS_CPUREGS_H_ 62 63 /* 64 * Address space. 65 * 32-bit mips CPUS partition their 32-bit address space into four segments: 66 * 67 * kuseg 0x00000000 - 0x7fffffff User virtual mem, mapped 68 * kseg0 0x80000000 - 0x9fffffff Physical memory, cached, unmapped 69 * kseg1 0xa0000000 - 0xbfffffff Physical memory, uncached, unmapped 70 * kseg2 0xc0000000 - 0xffffffff kernel-virtual, mapped 71 * 72 * mips1 physical memory is limited to 512Mbytes, which is 73 * doubly mapped in kseg0 (cached) and kseg1 (uncached.) 74 * Caching of mapped addresses is controlled by bits in the TLB entry. 75 */ 76 77 #define MIPS_KUSEG_START 0x0 78 #define MIPS_KSEG0_START 0x80000000 79 #define MIPS_KSEG1_START 0xa0000000 80 #define MIPS_KSEG2_START 0xc0000000 81 #define MIPS_MAX_MEM_ADDR 0xbe000000 82 #define MIPS_RESERVED_ADDR 0xbfc80000 83 84 #define MIPS_KSEG0_TO_PHYS(x) ((unsigned)(x) & 0x1fffffff) 85 #define MIPS_PHYS_TO_KSEG0(x) ((unsigned)(x) | MIPS_KSEG0_START) 86 #define MIPS_KSEG1_TO_PHYS(x) ((unsigned)(x) & 0x1fffffff) 87 #define MIPS_PHYS_TO_KSEG1(x) ((unsigned)(x) | MIPS_KSEG1_START) 88 89 /* Map virtual address to index in mips3 r4k virtually-indexed cache */ 90 #define MIPS3_VA_TO_CINDEX(x) \ 91 ((unsigned)(x) & 0xffffff | MIPS_KSEG0_START) 92 93 94 /* 95 * The bits in the cause register. 96 * 97 * Bits common to r3000 and r4000: 98 * 99 * MIPS_CR_BR_DELAY Exception happened in branch delay slot. 100 * MIPS_CR_COP_ERR Coprocessor error. 101 * MIPS_CR_IP Interrupt pending bits defined below. 102 * (same meaning as in CAUSE register). 103 * MIPS_CR_EXC_CODE The exception type (see exception codes below). 104 * 105 * Differences: 106 * r3k has 4 bits of execption type, r4k has 5 bits. 107 */ 108 #define MIPS_CR_BR_DELAY 0x80000000 109 #define MIPS_CR_COP_ERR 0x30000000 110 #define MIPS1_CR_EXC_CODE 0x0000003C /* four bits */ 111 #define MIPS3_CR_EXC_CODE 0x0000007C /* five bits */ 112 #define MIPS_CR_IP 0x0000FF00 113 #define MIPS_CR_EXC_CODE_SHIFT 2 114 115 /* 116 * The bits in the status register. All bits are active when set to 1. 117 * 118 * R3000 status register fields: 119 * MIPS_SR_CO_USABILITY Control the usability of the four coprocessors. 120 * MIPS_SR_BOOT_EXC_VEC Use alternate exception vectors. 121 * MIPS_SR_TLB_SHUTDOWN TLB disabled. 122 * 123 * MIPS_SR_INT_IE Master (current) interrupt enable bit. 124 * 125 * Differences: 126 * r3k has cache control is via frobbing SR register bits, whereas the 127 * r4k cache control is via explicit instructions. 128 * r3k has a 3-entry stack of kernel/user bits, whereas the 129 * r4k has kernel/supervisor/user. 130 */ 131 #define MIPS_SR_COP_USABILITY 0xf0000000 132 #define MIPS_SR_COP_0_BIT 0x10000000 133 #define MIPS_SR_COP_1_BIT 0x20000000 134 135 /* r4k and r3k differences, see below */ 136 137 #define MIPS_SR_BOOT_EXC_VEC 0x00400000 138 #define MIPS_SR_TLB_SHUTDOWN 0x00200000 139 140 /* r4k and r3k differences, see below */ 141 142 #define MIPS_SR_INT_IE 0x00000001 143 /*#define MIPS_SR_MBZ 0x0f8000c0*/ /* Never used, true for r3k */ 144 /*#define MIPS_SR_INT_MASK 0x0000ff00*/ 145 146 #define MIPS_SR_INT_ENAB MIPS_SR_INT_IE /* backwards compatibility */ 147 #define MIPS_SR_INT_ENA_CUR MIPS_SR_INT_IE /* backwards compatibility */ 148 149 150 151 /* 152 * The R2000/R3000-specific status register bit definitions. 153 * all bits are active when set to 1. 154 * 155 * MIPS_SR_PARITY_ERR Parity error. 156 * MIPS_SR_CACHE_MISS Most recent D-cache load resulted in a miss. 157 * MIPS_SR_PARITY_ZERO Zero replaces outgoing parity bits. 158 * MIPS_SR_SWAP_CACHES Swap I-cache and D-cache. 159 * MIPS_SR_ISOL_CACHES Isolate D-cache from main memory. 160 * Interrupt enable bits defined below. 161 * MIPS_SR_KU_OLD Old kernel/user mode bit. 1 => user mode. 162 * MIPS_SR_INT_ENA_OLD Old interrupt enable bit. 163 * MIPS_SR_KU_PREV Previous kernel/user mode bit. 1 => user mode. 164 * MIPS_SR_INT_ENA_PREV Previous interrupt enable bit. 165 * MIPS_SR_KU_CUR Current kernel/user mode bit. 1 => user mode. 166 */ 167 168 #define MIPS1_PARITY_ERR 0x00100000 169 #define MIPS1_CACHE_MISS 0x00080000 170 #define MIPS1_PARITY_ZERO 0x00040000 171 #define MIPS1_SWAP_CACHES 0x00020000 172 #define MIPS1_ISOL_CACHES 0x00010000 173 174 #define MIPS1_SR_KU_OLD 0x00000020 /* 2nd stacked KU/IE*/ 175 #define MIPS1_SR_INT_ENA_OLD 0x00000010 /* 2nd stacked KU/IE*/ 176 #define MIPS1_SR_KU_PREV 0x00000008 /* 1st stacked KU/IE*/ 177 #define MIPS1_SR_INT_ENA_PREV 0x00000004 /* 1st stacked KU/IE*/ 178 #define MIPS1_SR_KU_CUR 0x00000002 /* current KU */ 179 180 /* backwards compatibility */ 181 #define MIPS_SR_PARITY_ERR MIPS1_PARITY_ERR 182 #define MIPS_SR_CACHE_MISS MIPS1_CACHE_MISS 183 #define MIPS_SR_PARITY_ZERO MIPS1_PARITY_ZERO 184 #define MIPS_SR_SWAP_CACHES MIPS1_SWAP_CACHES 185 #define MIPS_SR_ISOL_CACHES MIPS1_ISOL_CACHES 186 187 #define MIPS_SR_KU_OLD MIPS1_SR_KU_OLD 188 #define MIPS_SR_INT_ENA_OLD MIPS1_SR_INT_ENA_OLD 189 #define MIPS_SR_KU_PREV MIPS1_SR_KU_PREV 190 #define MIPS_SR_KU_CUR MIPS1_SR_KU_CUR 191 #define MIPS_SR_INT_ENA_PREV MIPS1_SR_INT_ENA_PREV 192 193 /* 194 * R4000 status register bit definitons, 195 * where different from r2000/r3000. 196 */ 197 #define MIPS3_SR_RP 0x08000000 198 #define MIPS3_SR_FR_32 0x04000000 199 #define MIPS3_SR_RE 0x02000000 200 201 #define MIPS3_SR_SOFT_RESET 0x00100000 202 #define MIPS3_SR_DIAG_CH 0x00040000 203 #define MIPS3_SR_DIAG_CE 0x00020000 204 #define MIPS3_SR_DIAG_PE 0x00010000 205 #define MIPS3_SR_KX 0x00000080 206 #define MIPS3_SR_SX 0x00000040 207 #define MIPS3_SR_UX 0x00000020 208 #define MIPS3_SR_KSU_MASK 0x00000018 209 #define MIPS3_SR_KSU_USER 0x00000010 210 #define MIPS3_SR_KSU_SUPER 0x00000008 211 #define MIPS3_SR_KSU_KERNEL 0x00000000 212 #define MIPS3_SR_ERL 0x00000004 213 #define MIPS3_SR_EXL 0x00000002 214 215 #define MIPS_SR_SOFT_RESET MIPS3_SR_SOFT_RESET 216 #define MIPS_SR_DIAG_CH MIPS3_SR_DIAG_CH 217 #define MIPS_SR_DIAG_CE MIPS3_SR_DIAG_CE 218 #define MIPS_SR_DIAG_PE MIPS3_SR_DIAG_PE 219 #define MIPS_SR_KX MIPS3_SR_KX 220 #define MIPS_SR_SX MIPS3_SR_SX 221 #define MIPS_SR_UX MIPS3_SR_UX 222 223 #define MIPS_SR_KSU_MASK MIPS3_SR_KSU_MASK 224 #define MIPS_SR_KSU_USER MIPS3_SR_KSU_USER 225 #define MIPS_SR_KSU_SUPER MIPS3_SR_KSU_SUPER 226 #define MIPS_SR_KSU_KERNEL MIPS3_SR_KSU_KERNEL 227 #define MIPS_SR_ERL MIPS3_SR_ERL 228 #define MIPS_SR_EXL MIPS3_SR_EXL 229 230 231 /* 232 * The interrupt masks. 233 * If a bit in the mask is 1 then the interrupt is enabled (or pending). 234 */ 235 #define MIPS_INT_MASK 0xff00 236 #define MIPS_INT_MASK_5 0x8000 237 #define MIPS_INT_MASK_4 0x4000 238 #define MIPS_INT_MASK_3 0x2000 239 #define MIPS_INT_MASK_2 0x1000 240 #define MIPS_INT_MASK_1 0x0800 241 #define MIPS_INT_MASK_0 0x0400 242 #define MIPS_HARD_INT_MASK 0xfc00 243 #define MIPS_SOFT_INT_MASK_1 0x0200 244 #define MIPS_SOFT_INT_MASK_0 0x0100 245 246 247 /* 248 * nesting interrupt masks. 249 */ 250 #define MIPS_INT_MASK_SPL_SOFT0 MIPS_SOFT_INT_MASK_0 251 #define MIPS_INT_MASK_SPL_SOFT1 (MIPS_SOFT_INT_MASK_1|MIPS_INT_MASK_SPL_SOFT0) 252 #define MIPS_INT_MASK_SPL0 (MIPS_INT_MASK_0|MIPS_INT_MASK_SPL_SOFT1) 253 #define MIPS_INT_MASK_SPL1 (MIPS_INT_MASK_1|MIPS_INT_MASK_SPL0) 254 #define MIPS_INT_MASK_SPL2 (MIPS_INT_MASK_2|MIPS_INT_MASK_SPL1) 255 #define MIPS_INT_MASK_SPL3 (MIPS_INT_MASK_3|MIPS_INT_MASK_SPL2) 256 #define MIPS_INT_MASK_SPL4 (MIPS_INT_MASK_4|MIPS_INT_MASK_SPL3) 257 #define MIPS_INT_MASK_SPL5 (MIPS_INT_MASK_5|MIPS_INT_MASK_SPL4) 258 259 /* 260 * mips3 CPUs have on-chip timer at INT_MASK_5. We don't support it yet. 261 */ 262 #define MIPS3_INT_MASK (MIPS_INT_MASK & ~MIPS_INT_MASK_5) 263 #define MIPS3_HARD_INT_MASK (MIPS_HARD_INT_MASK & ~MIPS_INT_MASK_5) 264 265 266 /* 267 * The bits in the context register. 268 */ 269 #define MIPS1_CNTXT_PTE_BASE 0xFFE00000 270 #define MIPS1_CNTXT_BAD_VPN 0x001FFFFC 271 272 #define MIPS3_CNTXT_PTE_BASE 0xFF800000 273 #define MIPS3_CNTXT_BAD_VPN2 0x007FFFF0 274 275 /* 276 * The bits in the MIPS3 config register. 277 * 278 * bit 0..5: R/W, Bit 6..31: R/O 279 */ 280 281 /* kseg0 coherency algorithm - see MIPS3_TLB_ATTR values */ 282 #define MIPS3_CONFIG_K0_MASK 0x00000007 283 284 /* 285 * R/W Update on Store Conditional 286 * 0: Store Conditional uses coherency algorithm specified by TLB 287 * 1: Store Conditional uses cacheable coherent update on write 288 */ 289 #define MIPS3_CONFIG_CU 0x00000008 290 291 #define MIPS3_CONFIG_DB 0x00000010 /* Primary D-cache line size */ 292 #define MIPS3_CONFIG_IB 0x00000020 /* Primary I-cache line size */ 293 #define MIPS3_CONFIG_CACHE_L1_LSIZE(config, bit) \ 294 (((config) & (bit)) ? 0x10 : 0x20) 295 296 #define MIPS3_CONFIG_DC_MASK 0x000001c0 /* Primary D-cache size */ 297 #define MIPS3_CONFIG_DC_SHIFT 6 298 #define MIPS3_CONFIG_IC_MASK 0x00000e00 /* Primary I-cache size */ 299 #define MIPS3_CONFIG_IC_SHIFT 9 300 #define MIPS3_CONFIG_CACHE_SIZE(config, mask, shift) \ 301 (0x1000 << (((config) & (mask)) >> (shift))) 302 303 /* Block ordering: 0: sequential, 1: sub-block */ 304 #define MIPS3_CONFIG_EB 0x00002000 305 306 /* ECC mode - 0: ECC mode, 1: parity mode */ 307 #define MIPS3_CONFIG_EM 0x00004000 308 309 /* BigEndianMem - 0: kernel and memory are little endian, 1: big endian */ 310 #define MIPS3_CONFIG_BE 0x00008000 311 312 /* Dirty Shared coherency state - 0: enabled, 1: disabled */ 313 #define MIPS3_CONFIG_SM 0x00010000 314 315 /* Secondary Cache - 0: present, 1: not present */ 316 #define MIPS3_CONFIG_SC 0x00020000 317 318 /* System Port width - 0: 64-bit, 1,2,3: reserved */ 319 #define MIPS3_CONFIG_EW_MASK 0x000c0000 320 #define MIPS3_CONFIG_EW_SHIFT 18 321 322 /* Secondary Cache port width - 0: 128-bit data path to S-cache, 1: reserved */ 323 #define MIPS3_CONFIG_SW 0x00100000 324 325 /* Split Secondary Cache Mode - 0: I/D mixed, 1: I/D separated by SCAddr(17) */ 326 #define MIPS3_CONFIG_SS 0x00200000 327 328 /* Secondary Cache line size */ 329 #define MIPS3_CONFIG_SB_MASK 0x00c00000 330 #define MIPS3_CONFIG_SB_SHIFT 22 331 #define MIPS3_CONFIG_CACHE_L2_LSIZE(config) \ 332 (0x10 << (((config) & MIPS3_CONFIG_SB_MASK) >> MIPS3_CONFIG_SB_SHIFT)) 333 334 /* write back data rate */ 335 #define MIPS3_CONFIG_EP_MASK 0x0f000000 336 #define MIPS3_CONFIG_EP_SHIFT 24 337 338 /* System clock ratio - this value is CPU dependent */ 339 #define MIPS3_CONFIG_EC_MASK 0x70000000 340 #define MIPS3_CONFIG_EC_SHIFT 28 341 342 /* Master-Checker Mode - 1: enabled */ 343 #define MIPS3_CONFIG_CM 0x80000000 344 345 /* 346 * Location of exception vectors. 347 * 348 * Common vectors: reset and UTLB miss. 349 */ 350 #define MIPS_RESET_EXC_VEC 0xBFC00000 351 #define MIPS_UTLB_MISS_EXC_VEC 0x80000000 352 353 /* 354 * R3000 general exception vector (everything else) 355 */ 356 #define MIPS1_GEN_EXC_VEC 0x80000080 357 358 /* 359 * R4000 MIPS-III exception vectors 360 */ 361 #define MIPS3_XTLB_MISS_EXC_VEC 0x80000080 362 #define MIPS3_CACHE_ERR_EXC_VEC 0x80000100 363 #define MIPS3_GEN_EXC_VEC 0x80000180 364 365 /* 366 * Coprocessor 0 registers: 367 * 368 * MIPS_COP_0_TLB_INDEX TLB index. 369 * MIPS_COP_0_TLB_RANDOM TLB random. 370 * MIPS_COP_0_TLB_LOW r3k TLB entry low. 371 * MIPS_COP_0_TLB_LO0 r4k TLB entry low. 372 * MIPS_COP_0_TLB_LO1 r4k TLB entry low, extended. 373 * MIPS_COP_0_TLB_CONTEXT TLB context. 374 * MIPS_COP_0_BAD_VADDR Bad virtual address. 375 * MIPS_COP_0_TLB_HI TLB entry high. 376 * MIPS_COP_0_STATUS_REG Status register. 377 * MIPS_COP_0_CAUSE_REG Exception cause register. 378 * MIPS_COP_0_EXC_PC Exception PC. 379 * MIPS_COP_0_PRID Processor revision identifier. 380 */ 381 #define MIPS_COP_0_TLB_INDEX $0 382 #define MIPS_COP_0_TLB_RANDOM $1 383 /* Name and meaning of TLB bits for $2 differ on r3k and r4k. */ 384 385 #define MIPS_COP_0_TLB_CONTEXT $4 386 /* $5 and $6 new with MIPS-III */ 387 #define MIPS_COP_0_BAD_VADDR $8 388 #define MIPS_COP_0_TLB_HI $10 389 #define MIPS_COP_0_STATUS_REG $12 390 #define MIPS_COP_0_CAUSE_REG $13 391 #define MIPS_COP_0_EXC_PC $14 392 #define MIPS_COP_0_PRID $15 393 394 395 /* r3k-specific */ 396 #define MIPS_COP_0_TLB_LOW $2 397 398 /* MIPS-III additions */ 399 #define MIPS_COP_0_TLB_LO0 $2 400 #define MIPS_COP_0_TLB_LO1 $3 401 402 #define MIPS_COP_0_TLB_PG_MASK $5 403 #define MIPS_COP_0_TLB_WIRED $6 404 405 #define MIPS_COP_0_COUNT $9 406 #define MIPS_COP_0_COMPARE $11 407 408 #define MIPS_COP_0_CONFIG $16 409 #define MIPS_COP_0_LLADDR $17 410 #define MIPS_COP_0_WATCH_LO $18 411 #define MIPS_COP_0_WATCH_HI $19 412 #define MIPS_COP_0_TLB_XCONTEXT $20 413 #define MIPS_COP_0_ECC $26 414 #define MIPS_COP_0_CACHE_ERR $27 415 #define MIPS_COP_0_TAG_LO $28 416 #define MIPS_COP_0_TAG_HI $29 417 #define MIPS_COP_0_ERROR_PC $30 418 419 420 421 /* 422 * Values for the code field in a break instruction. 423 */ 424 #define MIPS_BREAK_INSTR 0x0000000d 425 #define MIPS_BREAK_VAL_MASK 0x03ff0000 426 #define MIPS_BREAK_VAL_SHIFT 16 427 #define MIPS_BREAK_KDB_VAL 512 428 #define MIPS_BREAK_SSTEP_VAL 513 429 #define MIPS_BREAK_BRKPT_VAL 514 430 #define MIPS_BREAK_SOVER_VAL 515 431 #define MIPS_BREAK_KDB (MIPS_BREAK_INSTR | \ 432 (MIPS_BREAK_KDB_VAL << MIPS_BREAK_VAL_SHIFT)) 433 #define MIPS_BREAK_SSTEP (MIPS_BREAK_INSTR | \ 434 (MIPS_BREAK_SSTEP_VAL << MIPS_BREAK_VAL_SHIFT)) 435 #define MIPS_BREAK_BRKPT (MIPS_BREAK_INSTR | \ 436 (MIPS_BREAK_BRKPT_VAL << MIPS_BREAK_VAL_SHIFT)) 437 #define MIPS_BREAK_SOVER (MIPS_BREAK_INSTR | \ 438 (MIPS_BREAK_SOVER_VAL << MIPS_BREAK_VAL_SHIFT)) 439 440 /* 441 * Mininum and maximum cache sizes. 442 */ 443 #define MIPS_MIN_CACHE_SIZE (16 * 1024) 444 #define MIPS_MAX_CACHE_SIZE (256 * 1024) 445 446 /* 447 * The floating point version and status registers. 448 */ 449 #define MIPS_FPU_ID $0 450 #define MIPS_FPU_CSR $31 451 452 /* 453 * The floating point coprocessor status register bits. 454 */ 455 #define MIPS_FPU_ROUNDING_BITS 0x00000003 456 #define MIPS_FPU_ROUND_RN 0x00000000 457 #define MIPS_FPU_ROUND_RZ 0x00000001 458 #define MIPS_FPU_ROUND_RP 0x00000002 459 #define MIPS_FPU_ROUND_RM 0x00000003 460 #define MIPS_FPU_STICKY_BITS 0x0000007c 461 #define MIPS_FPU_STICKY_INEXACT 0x00000004 462 #define MIPS_FPU_STICKY_UNDERFLOW 0x00000008 463 #define MIPS_FPU_STICKY_OVERFLOW 0x00000010 464 #define MIPS_FPU_STICKY_DIV0 0x00000020 465 #define MIPS_FPU_STICKY_INVALID 0x00000040 466 #define MIPS_FPU_ENABLE_BITS 0x00000f80 467 #define MIPS_FPU_ENABLE_INEXACT 0x00000080 468 #define MIPS_FPU_ENABLE_UNDERFLOW 0x00000100 469 #define MIPS_FPU_ENABLE_OVERFLOW 0x00000200 470 #define MIPS_FPU_ENABLE_DIV0 0x00000400 471 #define MIPS_FPU_ENABLE_INVALID 0x00000800 472 #define MIPS_FPU_EXCEPTION_BITS 0x0003f000 473 #define MIPS_FPU_EXCEPTION_INEXACT 0x00001000 474 #define MIPS_FPU_EXCEPTION_UNDERFLOW 0x00002000 475 #define MIPS_FPU_EXCEPTION_OVERFLOW 0x00004000 476 #define MIPS_FPU_EXCEPTION_DIV0 0x00008000 477 #define MIPS_FPU_EXCEPTION_INVALID 0x00010000 478 #define MIPS_FPU_EXCEPTION_UNIMPL 0x00020000 479 #define MIPS_FPU_COND_BIT 0x00800000 480 #define MIPS_FPU_FLUSH_BIT 0x01000000 /* r4k, MBZ on r3k */ 481 #define MIPS1_FPC_MBZ_BITS 0xff7c0000 482 #define MIPS3_FPC_MBZ_BITS 0xfe7c0000 483 484 485 /* 486 * Constants to determine if have a floating point instruction. 487 */ 488 #define MIPS_OPCODE_SHIFT 26 489 #define MIPS_OPCODE_C1 0x11 490 491 492 493 /* 494 * The low part of the TLB entry. 495 */ 496 #define MIPS1_TLB_PHYS_PAGE_SHIFT 12 497 #define MIPS1_TLB_PF_NUM 0xfffff000 498 #define MIPS1_TLB_NON_CACHEABLE_BIT 0x00000800 499 #define MIPS1_TLB_MOD_BIT 0x00000400 500 #define MIPS1_TLB_VALID_BIT 0x00000200 501 #define MIPS1_TLB_GLOBAL_BIT 0x00000100 502 503 #define MIPS3_TLB_PHYS_PAGE_SHIFT 6 504 #define MIPS3_TLB_PF_NUM 0x3fffffc0 505 506 #define MIPS3_TLB_MOD_BIT 0x00000004 507 #define MIPS3_TLB_VALID_BIT 0x00000002 508 #define MIPS3_TLB_GLOBAL_BIT 0x00000001 509 510 /* 511 * MIPS3_TLB_ATTR values - coherency algorithm: 512 * 0: cacheable, noncoherent, write-through, no write allocate 513 * 1: cacheable, noncoherent, write-through, write allocate 514 * 2: uncached 515 * 3: cacheable, noncoherent, write-back (noncoherent) 516 * 4: cacheable, coherent, write-back, exclusive (exclusive) 517 * 5: cacheable, coherent, write-back, exclusive on write (sharable) 518 * 6: cacheable, coherent, write-back, update on write (update) 519 * 7: cacheable, ?, ?, ?, ? 520 */ 521 #define MIPS3_TLB_ATTR_WT 0 /* IDT */ 522 #define MIPS3_TLB_ATTR_WT_WRITEALLOCATE 1 /* IDT */ 523 #define MIPS3_TLB_ATTR_UNCACHED 2 /* R4000/R4400, IDT */ 524 #define MIPS3_TLB_ATTR_WB_NONCOHERENT 3 /* R4000/R4400, IDT */ 525 #define MIPS3_TLB_ATTR_WB_EXCLUSIVE 4 /* R4000/R4400 */ 526 #define MIPS3_TLB_ATTR_WB_SHARABLE 5 /* R4000/R4400 */ 527 #define MIPS3_TLB_ATTR_WB_UPDATE 6 /* R4000/R4400 */ 528 529 530 /* 531 * The high part of the TLB entry. 532 */ 533 #define MIPS_TLB_VIRT_PAGE_SHIFT 12 534 535 #define MIPS1_TLB_VIRT_PAGE_NUM 0xfffff000 536 #define MIPS1_TLB_PID 0x00000fc0 537 #define MIPS1_TLB_PID_SHIFT 6 538 539 #define MIPS3_TLB_VIRT_PAGE_NUM 0xffffe000 540 #define MIPS3_TLB_PID 0x000000ff 541 #define MIPS3_TLB_PID_SHIFT 0 542 543 544 /* 545 * r3000: shift count to put the index in the right spot. 546 * (zero on r4000?) 547 */ 548 #define MIPS1_TLB_INDEX_SHIFT 8 549 550 551 /* 552 * The number of TLB entries and the first one that write random hits. 553 */ 554 #define MIPS1_TLB_NUM_TLB_ENTRIES 64 555 #define MIPS1_TLB_FIRST_RAND_ENTRY 8 556 557 #define MIPS3_TLB_NUM_TLB_ENTRIES 48 558 #define MIPS_R4300_TLB_NUM_TLB_ENTRIES 32 559 #define MIPS3_TLB_WIRED_ENTRIES 8 560 561 562 /* 563 * The number of process id entries. 564 */ 565 #define MIPS1_TLB_NUM_PIDS 64 566 #define MIPS3_TLB_NUM_PIDS 256 567 568 /* 569 * backwards compatibility with existing locore and compile-time 570 * mips1/mips3 binding. 571 * 572 * XXX INT_MASK and HARD_INT_MASK are here only because we dont 573 * support the mips3 on-chip timer which is tied to INT_5. 574 */ 575 576 #if defined(MIPS3) && !defined(MIPS1) 577 #define MIPS_TLB_PID_SHIFT MIPS3_TLB_PID_SHIFT 578 #define MIPS_TLB_NUM_PIDS MIPS3_TLB_NUM_PIDS 579 #endif 580 581 #if !defined(MIPS3) && defined(MIPS1) 582 #define MIPS_TLB_PID_SHIFT MIPS1_TLB_PID_SHIFT 583 #define MIPS_TLB_NUM_PIDS MIPS1_TLB_NUM_PIDS 584 #endif 585 586 587 #if defined(MIPS1) && defined(MIPS3) 588 #define MIPS_TLB_PID_SHIFT \ 589 ((CPUISMIPS3)? MIPS3_TLB_PID_SHIFT : MIPS1_TLB_PID_SHIFT) 590 591 #define MIPS_TLB_NUM_PIDS \ 592 ((CPUISMIPS3)? MIPS3_TLB_NUM_PIDS : MIPS1_TLB_NUM_PIDS) 593 594 #endif 595 596 /* 597 * TLB probe return codes. 598 */ 599 #define MIPS_TLB_NOT_FOUND 0 600 #define MIPS_TLB_FOUND 1 601 #define MIPS_TLB_FOUND_WITH_PATCH 2 602 #define MIPS_TLB_PROBE_ERROR 3 603 604 #endif /* _MIPS_CPUREGS_H_ */ 605
Indexes created Thu Oct 30 16:09:53 GMT 2025