cpuregs.h revision 1.44
1 /* $NetBSD: cpuregs.h,v 1.44 2001/08/15 03:01:37 simonb Exp $ */ 2 3 /* 4 * Copyright (c) 1992, 1993 5 * The Regents of the University of California. All rights reserved. 6 * 7 * This code is derived from software contributed to Berkeley by 8 * Ralph Campbell and Rick Macklem. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the University of 21 * California, Berkeley and its contributors. 22 * 4. Neither the name of the University nor the names of its contributors 23 * may be used to endorse or promote products derived from this software 24 * without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 27 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 28 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 29 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 30 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 31 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 32 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 33 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 34 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 35 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 36 * SUCH DAMAGE. 37 * 38 * @(#)machConst.h 8.1 (Berkeley) 6/10/93 39 * 40 * machConst.h -- 41 * 42 * Machine dependent constants. 43 * 44 * Copyright (C) 1989 Digital Equipment Corporation. 45 * Permission to use, copy, modify, and distribute this software and 46 * its documentation for any purpose and without fee is hereby granted, 47 * provided that the above copyright notice appears in all copies. 48 * Digital Equipment Corporation makes no representations about the 49 * suitability of this software for any purpose. It is provided "as is" 50 * without express or implied warranty. 51 * 52 * from: Header: /sprite/src/kernel/mach/ds3100.md/RCS/machConst.h, 53 * v 9.2 89/10/21 15:55:22 jhh Exp SPRITE (DECWRL) 54 * from: Header: /sprite/src/kernel/mach/ds3100.md/RCS/machAddrs.h, 55 * v 1.2 89/08/15 18:28:21 rab Exp SPRITE (DECWRL) 56 * from: Header: /sprite/src/kernel/vm/ds3100.md/RCS/vmPmaxConst.h, 57 * v 9.1 89/09/18 17:33:00 shirriff Exp SPRITE (DECWRL) 58 */ 59 60 #ifndef _MIPS_CPUREGS_H_ 61 #define _MIPS_CPUREGS_H_ 62 63 /* 64 * Address space. 65 * 32-bit mips CPUS partition their 32-bit address space into four segments: 66 * 67 * kuseg 0x00000000 - 0x7fffffff User virtual mem, mapped 68 * kseg0 0x80000000 - 0x9fffffff Physical memory, cached, unmapped 69 * kseg1 0xa0000000 - 0xbfffffff Physical memory, uncached, unmapped 70 * kseg2 0xc0000000 - 0xffffffff kernel-virtual, mapped 71 * 72 * mips1 physical memory is limited to 512Mbytes, which is 73 * doubly mapped in kseg0 (cached) and kseg1 (uncached.) 74 * Caching of mapped addresses is controlled by bits in the TLB entry. 75 */ 76 77 #define MIPS_KUSEG_START 0x0 78 #define MIPS_KSEG0_START 0x80000000 79 #define MIPS_KSEG1_START 0xa0000000 80 #define MIPS_KSEG2_START 0xc0000000 81 #define MIPS_MAX_MEM_ADDR 0xbe000000 82 #define MIPS_RESERVED_ADDR 0xbfc80000 83 84 #define MIPS_PHYS_MASK 0x1fffffff 85 86 #define MIPS_KSEG0_TO_PHYS(x) ((unsigned)(x) & MIPS_PHYS_MASK) 87 #define MIPS_PHYS_TO_KSEG0(x) ((unsigned)(x) | MIPS_KSEG0_START) 88 #define MIPS_KSEG1_TO_PHYS(x) ((unsigned)(x) & MIPS_PHYS_MASK) 89 #define MIPS_PHYS_TO_KSEG1(x) ((unsigned)(x) | MIPS_KSEG1_START) 90 91 /* Map virtual address to index in mips3 r4k virtually-indexed cache */ 92 #define MIPS3_VA_TO_CINDEX(x) \ 93 ((unsigned)(x) & 0xffffff | MIPS_KSEG0_START) 94 95 96 /* 97 * The bits in the cause register. 98 * 99 * Bits common to r3000 and r4000: 100 * 101 * MIPS_CR_BR_DELAY Exception happened in branch delay slot. 102 * MIPS_CR_COP_ERR Coprocessor error. 103 * MIPS_CR_IP Interrupt pending bits defined below. 104 * (same meaning as in CAUSE register). 105 * MIPS_CR_EXC_CODE The exception type (see exception codes below). 106 * 107 * Differences: 108 * r3k has 4 bits of execption type, r4k has 5 bits. 109 */ 110 #define MIPS_CR_BR_DELAY 0x80000000 111 #define MIPS_CR_COP_ERR 0x30000000 112 #define MIPS1_CR_EXC_CODE 0x0000003C /* four bits */ 113 #define MIPS3_CR_EXC_CODE 0x0000007C /* five bits */ 114 #define MIPS_CR_IP 0x0000FF00 115 #define MIPS_CR_EXC_CODE_SHIFT 2 116 117 /* 118 * The bits in the status register. All bits are active when set to 1. 119 * 120 * R3000 status register fields: 121 * MIPS_SR_CO_USABILITY Control the usability of the four coprocessors. 122 * MIPS_SR_BOOT_EXC_VEC Use alternate exception vectors. 123 * MIPS_SR_TLB_SHUTDOWN TLB disabled. 124 * 125 * MIPS_SR_INT_IE Master (current) interrupt enable bit. 126 * 127 * Differences: 128 * r3k has cache control is via frobbing SR register bits, whereas the 129 * r4k cache control is via explicit instructions. 130 * r3k has a 3-entry stack of kernel/user bits, whereas the 131 * r4k has kernel/supervisor/user. 132 */ 133 #define MIPS_SR_COP_USABILITY 0xf0000000 134 #define MIPS_SR_COP_0_BIT 0x10000000 135 #define MIPS_SR_COP_1_BIT 0x20000000 136 137 /* r4k and r3k differences, see below */ 138 139 #define MIPS_SR_BOOT_EXC_VEC 0x00400000 140 #define MIPS_SR_TLB_SHUTDOWN 0x00200000 141 142 /* r4k and r3k differences, see below */ 143 144 #define MIPS_SR_INT_IE 0x00000001 145 /*#define MIPS_SR_MBZ 0x0f8000c0*/ /* Never used, true for r3k */ 146 /*#define MIPS_SR_INT_MASK 0x0000ff00*/ 147 148 149 /* 150 * The R2000/R3000-specific status register bit definitions. 151 * all bits are active when set to 1. 152 * 153 * MIPS_SR_PARITY_ERR Parity error. 154 * MIPS_SR_CACHE_MISS Most recent D-cache load resulted in a miss. 155 * MIPS_SR_PARITY_ZERO Zero replaces outgoing parity bits. 156 * MIPS_SR_SWAP_CACHES Swap I-cache and D-cache. 157 * MIPS_SR_ISOL_CACHES Isolate D-cache from main memory. 158 * Interrupt enable bits defined below. 159 * MIPS_SR_KU_OLD Old kernel/user mode bit. 1 => user mode. 160 * MIPS_SR_INT_ENA_OLD Old interrupt enable bit. 161 * MIPS_SR_KU_PREV Previous kernel/user mode bit. 1 => user mode. 162 * MIPS_SR_INT_ENA_PREV Previous interrupt enable bit. 163 * MIPS_SR_KU_CUR Current kernel/user mode bit. 1 => user mode. 164 */ 165 166 #define MIPS1_PARITY_ERR 0x00100000 167 #define MIPS1_CACHE_MISS 0x00080000 168 #define MIPS1_PARITY_ZERO 0x00040000 169 #define MIPS1_SWAP_CACHES 0x00020000 170 #define MIPS1_ISOL_CACHES 0x00010000 171 172 #define MIPS1_SR_KU_OLD 0x00000020 /* 2nd stacked KU/IE*/ 173 #define MIPS1_SR_INT_ENA_OLD 0x00000010 /* 2nd stacked KU/IE*/ 174 #define MIPS1_SR_KU_PREV 0x00000008 /* 1st stacked KU/IE*/ 175 #define MIPS1_SR_INT_ENA_PREV 0x00000004 /* 1st stacked KU/IE*/ 176 #define MIPS1_SR_KU_CUR 0x00000002 /* current KU */ 177 178 /* backwards compatibility */ 179 #define MIPS_SR_PARITY_ERR MIPS1_PARITY_ERR 180 #define MIPS_SR_CACHE_MISS MIPS1_CACHE_MISS 181 #define MIPS_SR_PARITY_ZERO MIPS1_PARITY_ZERO 182 #define MIPS_SR_SWAP_CACHES MIPS1_SWAP_CACHES 183 #define MIPS_SR_ISOL_CACHES MIPS1_ISOL_CACHES 184 185 #define MIPS_SR_KU_OLD MIPS1_SR_KU_OLD 186 #define MIPS_SR_INT_ENA_OLD MIPS1_SR_INT_ENA_OLD 187 #define MIPS_SR_KU_PREV MIPS1_SR_KU_PREV 188 #define MIPS_SR_KU_CUR MIPS1_SR_KU_CUR 189 #define MIPS_SR_INT_ENA_PREV MIPS1_SR_INT_ENA_PREV 190 191 /* 192 * R4000 status register bit definitons, 193 * where different from r2000/r3000. 194 */ 195 #define MIPS3_SR_XX 0x80000000 196 #define MIPS3_SR_RP 0x08000000 197 #define MIPS3_SR_FR_32 0x04000000 198 #define MIPS3_SR_RE 0x02000000 199 200 #define MIPS3_SR_DIAG_DL 0x01000000 /* QED 52xx */ 201 #define MIPS3_SR_DIAG_IL 0x00800000 /* QED 52xx */ 202 #define MIPS3_SR_DIAG_BEV 0x00400000 203 #define MIPS3_SR_SOFT_RESET 0x00100000 204 #define MIPS3_SR_DIAG_CH 0x00040000 205 #define MIPS3_SR_DIAG_CE 0x00020000 206 #define MIPS3_SR_DIAG_PE 0x00010000 207 #define MIPS3_SR_KX 0x00000080 208 #define MIPS3_SR_SX 0x00000040 209 #define MIPS3_SR_UX 0x00000020 210 #define MIPS3_SR_KSU_MASK 0x00000018 211 #define MIPS3_SR_KSU_USER 0x00000010 212 #define MIPS3_SR_KSU_SUPER 0x00000008 213 #define MIPS3_SR_KSU_KERNEL 0x00000000 214 #define MIPS3_SR_ERL 0x00000004 215 #define MIPS3_SR_EXL 0x00000002 216 217 #define MIPS_SR_SOFT_RESET MIPS3_SR_SOFT_RESET 218 #define MIPS_SR_DIAG_CH MIPS3_SR_DIAG_CH 219 #define MIPS_SR_DIAG_CE MIPS3_SR_DIAG_CE 220 #define MIPS_SR_DIAG_PE MIPS3_SR_DIAG_PE 221 #define MIPS_SR_KX MIPS3_SR_KX 222 #define MIPS_SR_SX MIPS3_SR_SX 223 #define MIPS_SR_UX MIPS3_SR_UX 224 225 #define MIPS_SR_KSU_MASK MIPS3_SR_KSU_MASK 226 #define MIPS_SR_KSU_USER MIPS3_SR_KSU_USER 227 #define MIPS_SR_KSU_SUPER MIPS3_SR_KSU_SUPER 228 #define MIPS_SR_KSU_KERNEL MIPS3_SR_KSU_KERNEL 229 #define MIPS_SR_ERL MIPS3_SR_ERL 230 #define MIPS_SR_EXL MIPS3_SR_EXL 231 232 233 /* 234 * The interrupt masks. 235 * If a bit in the mask is 1 then the interrupt is enabled (or pending). 236 */ 237 #define MIPS_INT_MASK 0xff00 238 #define MIPS_INT_MASK_5 0x8000 239 #define MIPS_INT_MASK_4 0x4000 240 #define MIPS_INT_MASK_3 0x2000 241 #define MIPS_INT_MASK_2 0x1000 242 #define MIPS_INT_MASK_1 0x0800 243 #define MIPS_INT_MASK_0 0x0400 244 #define MIPS_HARD_INT_MASK 0xfc00 245 #define MIPS_SOFT_INT_MASK_1 0x0200 246 #define MIPS_SOFT_INT_MASK_0 0x0100 247 248 /* 249 * mips3 CPUs have on-chip timer at INT_MASK_5. Each platform can 250 * choose to enable this interrupt. 251 */ 252 #if defined(MIPS3_ENABLE_CLOCK_INTR) 253 #define MIPS3_INT_MASK MIPS_INT_MASK 254 #define MIPS3_HARD_INT_MASK MIPS_HARD_INT_MASK 255 #else 256 #define MIPS3_INT_MASK (MIPS_INT_MASK & ~MIPS_INT_MASK_5) 257 #define MIPS3_HARD_INT_MASK (MIPS_HARD_INT_MASK & ~MIPS_INT_MASK_5) 258 #endif 259 260 /* 261 * The bits in the context register. 262 */ 263 #define MIPS1_CNTXT_PTE_BASE 0xFFE00000 264 #define MIPS1_CNTXT_BAD_VPN 0x001FFFFC 265 266 #define MIPS3_CNTXT_PTE_BASE 0xFF800000 267 #define MIPS3_CNTXT_BAD_VPN2 0x007FFFF0 268 269 /* 270 * The bits in the MIPS3 config register. 271 * 272 * bit 0..5: R/W, Bit 6..31: R/O 273 */ 274 275 /* kseg0 coherency algorithm - see MIPS3_TLB_ATTR values */ 276 #define MIPS3_CONFIG_K0_MASK 0x00000007 277 278 /* 279 * R/W Update on Store Conditional 280 * 0: Store Conditional uses coherency algorithm specified by TLB 281 * 1: Store Conditional uses cacheable coherent update on write 282 */ 283 #define MIPS3_CONFIG_CU 0x00000008 284 285 #define MIPS3_CONFIG_DB 0x00000010 /* Primary D-cache line size */ 286 #define MIPS3_CONFIG_IB 0x00000020 /* Primary I-cache line size */ 287 #define MIPS3_CONFIG_CACHE_L1_LSIZE(config, bit) \ 288 (((config) & (bit)) ? 32 : 16) 289 290 #define MIPS3_CONFIG_DC_MASK 0x000001c0 /* Primary D-cache size */ 291 #define MIPS3_CONFIG_DC_SHIFT 6 292 #define MIPS3_CONFIG_IC_MASK 0x00000e00 /* Primary I-cache size */ 293 #define MIPS3_CONFIG_IC_SHIFT 9 294 #define MIPS3_CONFIG_C_DEFBASE 0x1000 /* default base 2^12 */ 295 #ifdef MIPS3_4100 /* VR4100 core */ 296 /* XXXCDC: THIS MIPS3_4100 SPECIAL CASE SHOULD GO AWAY */ 297 #define MIPS3_CONFIG_CS 0x00001000 /* cache size mode indication*/ 298 #define MIPS3_CONFIG_CACHE_SIZE(config, mask, dummy, shift) \ 299 ((((config)&MIPS3_CONFIG_CS)?0x400:0x1000) << (((config) & (mask)) >> (shift))) 300 #else 301 #define MIPS3_CONFIG_CACHE_SIZE(config, mask, base, shift) \ 302 ((base) << (((config) & (mask)) >> (shift))) 303 #endif 304 305 /* Block ordering: 0: sequential, 1: sub-block */ 306 #define MIPS3_CONFIG_EB 0x00002000 307 308 /* ECC mode - 0: ECC mode, 1: parity mode */ 309 #define MIPS3_CONFIG_EM 0x00004000 310 311 /* BigEndianMem - 0: kernel and memory are little endian, 1: big endian */ 312 #define MIPS3_CONFIG_BE 0x00008000 313 314 /* Dirty Shared coherency state - 0: enabled, 1: disabled */ 315 #define MIPS3_CONFIG_SM 0x00010000 316 317 /* Secondary Cache - 0: present, 1: not present */ 318 #define MIPS3_CONFIG_SC 0x00020000 319 320 /* System Port width - 0: 64-bit, 1: 32-bit (QED RM523x), 2,3: reserved */ 321 #define MIPS3_CONFIG_EW_MASK 0x000c0000 322 #define MIPS3_CONFIG_EW_SHIFT 18 323 324 /* Secondary Cache port width - 0: 128-bit data path to S-cache, 1: reserved */ 325 #define MIPS3_CONFIG_SW 0x00100000 326 327 /* Split Secondary Cache Mode - 0: I/D mixed, 1: I/D separated by SCAddr(17) */ 328 #define MIPS3_CONFIG_SS 0x00200000 329 330 /* Secondary Cache line size */ 331 #define MIPS3_CONFIG_SB_MASK 0x00c00000 332 #define MIPS3_CONFIG_SB_SHIFT 22 333 #define MIPS3_CONFIG_CACHE_L2_LSIZE(config) \ 334 (0x10 << (((config) & MIPS3_CONFIG_SB_MASK) >> MIPS3_CONFIG_SB_SHIFT)) 335 336 /* Write back data rate */ 337 #define MIPS3_CONFIG_EP_MASK 0x0f000000 338 #define MIPS3_CONFIG_EP_SHIFT 24 339 340 /* System clock ratio - this value is CPU dependent */ 341 #define MIPS3_CONFIG_EC_MASK 0x70000000 342 #define MIPS3_CONFIG_EC_SHIFT 28 343 344 /* Master-Checker Mode - 1: enabled */ 345 #define MIPS3_CONFIG_CM 0x80000000 346 347 /* 348 * Location of exception vectors. 349 * 350 * Common vectors: reset and UTLB miss. 351 */ 352 #define MIPS_RESET_EXC_VEC 0xBFC00000 353 #define MIPS_UTLB_MISS_EXC_VEC 0x80000000 354 355 /* 356 * R3000 general exception vector (everything else) 357 */ 358 #define MIPS1_GEN_EXC_VEC 0x80000080 359 360 /* 361 * R4000 MIPS-III exception vectors 362 */ 363 #define MIPS3_XTLB_MISS_EXC_VEC 0x80000080 364 #define MIPS3_CACHE_ERR_EXC_VEC 0x80000100 365 #define MIPS3_GEN_EXC_VEC 0x80000180 366 367 /* 368 * Coprocessor 0 registers: 369 * 370 * 0 MIPS_COP_0_TLB_INDEX TLB Index. 371 * 1 MIPS_COP_0_TLB_RANDOM TLB Random. 372 * 2 MIPS_COP_0_TLB_LOW r3k TLB entry low. 373 * 2 MIPS_COP_0_TLB_LO0 r4k TLB entry low. 374 * 3 MIPS_COP_0_TLB_LO1 r4k TLB entry low, extended. 375 * 4 MIPS_COP_0_TLB_CONTEXT TLB Context. 376 * 5 MIPS_COP_0_TLB_PG_MASK TLB Page Mask register. 377 * 6 MIPS_COP_0_TLB_WIRED Wired TLB number. 378 * 8 MIPS_COP_0_BAD_VADDR Bad virtual address. 379 * 9 MIPS_COP_0_COUNT Count register. 380 * 10 MIPS_COP_0_TLB_HI TLB entry high. 381 * 11 MIPS_COP_0_COMPARE Compare (against Count). 382 * 12 MIPS_COP_0_STATUS Status register. 383 * 13 MIPS_COP_0_CAUSE Exception cause register. 384 * 14 MIPS_COP_0_EXC_PC Exception PC. 385 * 15 MIPS_COP_0_PRID Processor revision identifier. 386 * 16 MIPS_COP_0_CONFIG Configuration register. 387 * 16/1 MIPS_COP_0_CONFIG1 Configuration register 1. 388 * 16/2 MIPS_COP_0_CONFIG2 Configuration register 2. 389 * 16/3 MIPS_COP_0_CONFIG3 Configuration register 3. 390 * 17 MIPS_COP_0_LLADDR Load Linked Address. 391 * 18 MIPS_COP_0_WATCH_LO WatchLo register. 392 * 19 MIPS_COP_0_WATCH_HI WatchHi register. 393 * 20 MIPS_COP_0_TLB_XCONTEXT TLB XContext register. 394 * 23 MIPS_COP_0_DEBUG Debug JTAG register. 395 * 24 MIPS_COP_0_DEPC DEPC JTAG register. 396 * 25 MIPS_COP_0_PERFCNT Performance Counter register. 397 * 26 MIPS_COP_0_ECC ECC / Error Control register. 398 * 27 MIPS_COP_0_CACHE_ERR Cache Error register. 399 * 28/0 MIPS_COP_0_TAG_LO Cache TagLo register (instr). 400 * 28/1 MIPS_COP_0_DATA_LO Cache DataLo register (instr). 401 * 28/2 MIPS_COP_0_TAG_LO Cache TagLo register (data). 402 * 28/3 MIPS_COP_0_DATA_LO Cache DataLo register (data). 403 * 29/0 MIPS_COP_0_TAG_HI Cache TagHi register (instr). 404 * 29/1 MIPS_COP_0_DATA_HI Cache DataHi register (instr). 405 * 29/2 MIPS_COP_0_TAG_HI Cache TagHi register (data). 406 * 29/3 MIPS_COP_0_DATA_HI Cache DataHi register (data). 407 * 30 MIPS_COP_0_ERROR_PC Error EPC register. 408 * 31 MIPS_COP_0_DESAVE DESAVE JTAG register. 409 */ 410 #define MIPS_COP_0_TLB_INDEX $0 411 #define MIPS_COP_0_TLB_RANDOM $1 412 /* Name and meaning of TLB bits for $2 differ on r3k and r4k. */ 413 414 #define MIPS_COP_0_TLB_CONTEXT $4 415 /* $5 and $6 new with MIPS-III */ 416 #define MIPS_COP_0_BAD_VADDR $8 417 #define MIPS_COP_0_TLB_HI $10 418 #define MIPS_COP_0_STATUS_REG $12 419 #define MIPS_COP_0_CAUSE_REG $13 420 #define MIPS_COP_0_STATUS $12 421 #define MIPS_COP_0_CAUSE $13 422 #define MIPS_COP_0_EXC_PC $14 423 #define MIPS_COP_0_PRID $15 424 425 426 /* MIPS-I */ 427 #define MIPS_COP_0_TLB_LOW $2 428 429 /* MIPS-III */ 430 #define MIPS_COP_0_TLB_LO0 $2 431 #define MIPS_COP_0_TLB_LO1 $3 432 433 #define MIPS_COP_0_TLB_PG_MASK $5 434 #define MIPS_COP_0_TLB_WIRED $6 435 436 #define MIPS_COP_0_COUNT $9 437 #define MIPS_COP_0_COMPARE $11 438 439 #define MIPS_COP_0_CONFIG $16 440 #define MIPS_COP_0_LLADDR $17 441 #define MIPS_COP_0_WATCH_LO $18 442 #define MIPS_COP_0_WATCH_HI $19 443 #define MIPS_COP_0_TLB_XCONTEXT $20 444 #define MIPS_COP_0_ECC $26 445 #define MIPS_COP_0_CACHE_ERR $27 446 #define MIPS_COP_0_TAG_LO $28 447 #define MIPS_COP_0_TAG_HI $29 448 #define MIPS_COP_0_ERROR_PC $30 449 450 /* MIPS32/64 */ 451 #define MIPS_COP_0_DEBUG $23 452 #define MIPS_COP_0_DEPC $24 453 #define MIPS_COP_0_PERFCNT $25 454 #define MIPS_COP_0_DATA_LO $28 455 #define MIPS_COP_0_DATA_HI $29 456 #define MIPS_COP_0_DESAVE $31 457 458 /* 459 * Values for the code field in a break instruction. 460 */ 461 #define MIPS_BREAK_INSTR 0x0000000d 462 #define MIPS_BREAK_VAL_MASK 0x03ff0000 463 #define MIPS_BREAK_VAL_SHIFT 16 464 #define MIPS_BREAK_KDB_VAL 512 465 #define MIPS_BREAK_SSTEP_VAL 513 466 #define MIPS_BREAK_BRKPT_VAL 514 467 #define MIPS_BREAK_SOVER_VAL 515 468 #define MIPS_BREAK_KDB (MIPS_BREAK_INSTR | \ 469 (MIPS_BREAK_KDB_VAL << MIPS_BREAK_VAL_SHIFT)) 470 #define MIPS_BREAK_SSTEP (MIPS_BREAK_INSTR | \ 471 (MIPS_BREAK_SSTEP_VAL << MIPS_BREAK_VAL_SHIFT)) 472 #define MIPS_BREAK_BRKPT (MIPS_BREAK_INSTR | \ 473 (MIPS_BREAK_BRKPT_VAL << MIPS_BREAK_VAL_SHIFT)) 474 #define MIPS_BREAK_SOVER (MIPS_BREAK_INSTR | \ 475 (MIPS_BREAK_SOVER_VAL << MIPS_BREAK_VAL_SHIFT)) 476 477 /* 478 * Mininum and maximum cache sizes. 479 */ 480 #define MIPS_MIN_CACHE_SIZE (16 * 1024) 481 #define MIPS_MAX_CACHE_SIZE (256 * 1024) 482 483 /* 484 * The floating point version and status registers. 485 */ 486 #define MIPS_FPU_ID $0 487 #define MIPS_FPU_CSR $31 488 489 /* 490 * The floating point coprocessor status register bits. 491 */ 492 #define MIPS_FPU_ROUNDING_BITS 0x00000003 493 #define MIPS_FPU_ROUND_RN 0x00000000 494 #define MIPS_FPU_ROUND_RZ 0x00000001 495 #define MIPS_FPU_ROUND_RP 0x00000002 496 #define MIPS_FPU_ROUND_RM 0x00000003 497 #define MIPS_FPU_STICKY_BITS 0x0000007c 498 #define MIPS_FPU_STICKY_INEXACT 0x00000004 499 #define MIPS_FPU_STICKY_UNDERFLOW 0x00000008 500 #define MIPS_FPU_STICKY_OVERFLOW 0x00000010 501 #define MIPS_FPU_STICKY_DIV0 0x00000020 502 #define MIPS_FPU_STICKY_INVALID 0x00000040 503 #define MIPS_FPU_ENABLE_BITS 0x00000f80 504 #define MIPS_FPU_ENABLE_INEXACT 0x00000080 505 #define MIPS_FPU_ENABLE_UNDERFLOW 0x00000100 506 #define MIPS_FPU_ENABLE_OVERFLOW 0x00000200 507 #define MIPS_FPU_ENABLE_DIV0 0x00000400 508 #define MIPS_FPU_ENABLE_INVALID 0x00000800 509 #define MIPS_FPU_EXCEPTION_BITS 0x0003f000 510 #define MIPS_FPU_EXCEPTION_INEXACT 0x00001000 511 #define MIPS_FPU_EXCEPTION_UNDERFLOW 0x00002000 512 #define MIPS_FPU_EXCEPTION_OVERFLOW 0x00004000 513 #define MIPS_FPU_EXCEPTION_DIV0 0x00008000 514 #define MIPS_FPU_EXCEPTION_INVALID 0x00010000 515 #define MIPS_FPU_EXCEPTION_UNIMPL 0x00020000 516 #define MIPS_FPU_COND_BIT 0x00800000 517 #define MIPS_FPU_FLUSH_BIT 0x01000000 /* r4k, MBZ on r3k */ 518 #define MIPS1_FPC_MBZ_BITS 0xff7c0000 519 #define MIPS3_FPC_MBZ_BITS 0xfe7c0000 520 521 522 /* 523 * Constants to determine if have a floating point instruction. 524 */ 525 #define MIPS_OPCODE_SHIFT 26 526 #define MIPS_OPCODE_C1 0x11 527 #define MIPS_OPCODE_LWC1 0x31 528 #define MIPS_OPCODE_LDC1 0x35 529 #define MIPS_OPCODE_SWC1 0x39 530 #define MIPS_OPCODE_SDC1 0x3d 531 532 533 /* 534 * The low part of the TLB entry. 535 */ 536 #define MIPS1_TLB_PFN 0xfffff000 537 #define MIPS1_TLB_NON_CACHEABLE_BIT 0x00000800 538 #define MIPS1_TLB_DIRTY_BIT 0x00000400 539 #define MIPS1_TLB_VALID_BIT 0x00000200 540 #define MIPS1_TLB_GLOBAL_BIT 0x00000100 541 542 #define MIPS3_TLB_PFN 0x3fffffc0 543 #define MIPS3_TLB_ATTR_MASK 0x00000038 544 #define MIPS3_TLB_ATTR_SHIFT 3 545 #define MIPS3_TLB_DIRTY_BIT 0x00000004 546 #define MIPS3_TLB_VALID_BIT 0x00000002 547 #define MIPS3_TLB_GLOBAL_BIT 0x00000001 548 549 /* XXX XXX XXX */ 550 #define MIPS1_TLB_PHYS_PAGE_SHIFT 12 551 #define MIPS3_TLB_PHYS_PAGE_SHIFT 6 552 #define MIPS1_TLB_PF_NUM MIPS1_TLB_PFN 553 #define MIPS3_TLB_PF_NUM MIPS3_TLB_PFN 554 #define MIPS1_TLB_MOD_BIT MIPS1_TLB_DIRTY_BIT 555 #define MIPS3_TLB_MOD_BIT MIPS3_TLB_DIRTY_BIT 556 /* XXX XXX XXX */ 557 558 /* 559 * MIPS3_TLB_ATTR values - coherency algorithm: 560 * 0: cacheable, noncoherent, write-through, no write allocate 561 * 1: cacheable, noncoherent, write-through, write allocate 562 * 2: uncached 563 * 3: cacheable, noncoherent, write-back (noncoherent) 564 * 4: cacheable, coherent, write-back, exclusive (exclusive) 565 * 5: cacheable, coherent, write-back, exclusive on write (sharable) 566 * 6: cacheable, coherent, write-back, update on write (update) 567 * 7: uncached, accelerated (gather STORE operations) 568 */ 569 #define MIPS3_TLB_ATTR_WT 0 /* IDT */ 570 #define MIPS3_TLB_ATTR_WT_WRITEALLOCATE 1 /* IDT */ 571 #define MIPS3_TLB_ATTR_UNCACHED 2 /* R4000/R4400, IDT */ 572 #define MIPS3_TLB_ATTR_WB_NONCOHERENT 3 /* R4000/R4400, IDT */ 573 #define MIPS3_TLB_ATTR_WB_EXCLUSIVE 4 /* R4000/R4400 */ 574 #define MIPS3_TLB_ATTR_WB_SHARABLE 5 /* R4000/R4400 */ 575 #define MIPS3_TLB_ATTR_WB_UPDATE 6 /* R4000/R4400 */ 576 #define MIPS4_TLB_ATTR_UNCACHED_ACCELERATED 7 /* R10000 */ 577 578 579 /* 580 * The high part of the TLB entry. 581 */ 582 #define MIPS1_TLB_VPN 0xfffff000 583 #define MIPS1_TLB_PID 0x00000fc0 584 #define MIPS1_TLB_PID_SHIFT 6 585 586 #define MIPS3_TLB_VPN2 0xffffe000 587 #define MIPS3_TLB_ASID 0x000000ff 588 589 /* XXX XXX XXX */ 590 #define MIPS1_TLB_VIRT_PAGE_NUM MIPS1_TLB_VPN 591 #define MIPS3_TLB_VIRT_PAGE_NUM MIPS3_TLB_VPN2 592 #define MIPS3_TLB_PID MIPS3_TLB_ASID 593 #define MIPS_TLB_VIRT_PAGE_SHIFT 12 594 /* XXX XXX XXX */ 595 596 /* 597 * r3000: shift count to put the index in the right spot. 598 */ 599 #define MIPS1_TLB_INDEX_SHIFT 8 600 601 /* 602 * The number of TLB entries and the first one that write random hits. 603 */ 604 #define MIPS1_TLB_NUM_TLB_ENTRIES 64 605 #define MIPS1_TLB_FIRST_RAND_ENTRY 8 606 607 #define MIPS3_TLB_NUM_TLB_ENTRIES 48 608 #define MIPS_R4300_TLB_NUM_TLB_ENTRIES 32 609 #define MIPS3_TLB_WIRED_UPAGES 1 610 611 612 /* 613 * The number of process id entries. 614 */ 615 #define MIPS1_TLB_NUM_PIDS 64 616 #define MIPS3_TLB_NUM_ASIDS 256 617 618 /* 619 * Patch codes to hide CPU design differences between MIPS1 and MIPS3. 620 */ 621 622 #if !defined(MIPS3) && defined(MIPS1) 623 #define MIPS_TLB_PID_SHIFT MIPS1_TLB_PID_SHIFT 624 #define MIPS_TLB_NUM_PIDS MIPS1_TLB_NUM_PIDS 625 #endif 626 627 #if defined(MIPS3) && !defined(MIPS1) 628 #define MIPS_TLB_PID_SHIFT 0 629 #define MIPS_TLB_NUM_PIDS MIPS3_TLB_NUM_ASIDS 630 #endif 631 632 633 #if defined(MIPS1) && defined(MIPS3) 634 #define MIPS_TLB_PID_SHIFT \ 635 ((CPUISMIPS3)? 0 : MIPS1_TLB_PID_SHIFT) 636 637 #define MIPS_TLB_NUM_PIDS \ 638 ((CPUISMIPS3)? MIPS3_TLB_NUM_ASIDS : MIPS1_TLB_NUM_PIDS) 639 640 #endif 641 642 /* 643 * CPU processor revision IDs for company ID == 0 (non mips32/64 chips) */ 644 */ 645 #define MIPS_R2000 0x01 /* MIPS R2000 ISA I */ 646 #define MIPS_R3000 0x02 /* MIPS R3000 ISA I */ 647 #define MIPS_R6000 0x03 /* MIPS R6000 ISA II */ 648 #define MIPS_R4000 0x04 /* MIPS R4000/R4400 ISA III */ 649 #define MIPS_R3LSI 0x05 /* LSI Logic R3000 derivative ISA I */ 650 #define MIPS_R6000A 0x06 /* MIPS R6000A ISA II */ 651 #define MIPS_R3IDT 0x07 /* IDT R3041 or RC36100 ISA I */ 652 #define MIPS_R10000 0x09 /* MIPS R10000 ISA IV */ 653 #define MIPS_R4200 0x0a /* NEC VR4200 ISA III */ 654 #define MIPS_R4300 0x0b /* NEC VR4300 ISA III */ 655 #define MIPS_R4100 0x0c /* NEC VR4100 ISA III */ 656 #define MIPS_R12000 0x0e /* MIPS R12000 ISA IV */ 657 #define MIPS_R14000 0x0f /* MIPS R14000 ISA IV */ 658 #define MIPS_R8000 0x10 /* MIPS R8000 Blackbird/TFP ISA IV */ 659 #define MIPS_RC32300 0x18 /* IDT RC32334,332,355 ISA 32 */ 660 #define MIPS_R4600 0x20 /* QED R4600 Orion ISA III */ 661 #define MIPS_R4700 0x21 /* QED R4700 Orion ISA III */ 662 #define MIPS_R3SONY 0x21 /* Sony R3000 based ISA I */ 663 #define MIPS_R4650 0x22 /* QED R4650 ISA III */ 664 #define MIPS_TX3900 0x22 /* Toshiba TX39 family ISA I */ 665 #define MIPS_R5000 0x23 /* MIPS R5000 ISA IV */ 666 #define MIPS_R3NKK 0x23 /* NKK R3000 based ISA I */ 667 #define MIPS_RC32364 0x26 /* IDT RC32364 ISA 32 */ 668 #define MIPS_RM7000 0x27 /* QED RM7000 ISA IV */ 669 #define MIPS_RM5200 0x28 /* QED RM5200s ISA IV */ 670 #define MIPS_TX4900 0x2d /* Toshiba TX49 family ISA III */ 671 #define MIPS_RC64470 0x30 /* IDT RC64474/RC64475 ISA III */ 672 #define MIPS_R5400 0x54 /* NEC VR5400 ISA IV */ 673 674 /* 675 * CPU processor revision IDs for company ID == 1 (MIPS) */ 676 */ 677 #define MIPS_4Kc 0x80 /* MIPS 4Kc ISA 32 */ 678 #define MIPS_5Kc 0x81 /* MIPS 5Kc ISA 64 */ 679 #define MIPS_4KEc 0x84 /* MIPS 4KEc ISA 32 */ 680 #define MIPS_4KSc 0x86 /* MIPS 4KSc ISA 32 */ 681 682 /* 683 * CPU processor revision IDs for company ID == 3 (Alchemy) */ 684 */ 685 #define MIPS_AU1000 0x01 /* Alchemy Au1000 ISA 32 */ 686 687 /* 688 * CPU processor revision IDs for company ID == 4 (SiByte) */ 689 */ 690 #define MIPS_SB1 0x01 /* SiByte SB1 ISA 64 */ 691 692 /* 693 * FPU processor revision ID 694 */ 695 #define MIPS_SOFT 0x00 /* Software emulation ISA I */ 696 #define MIPS_R2360 0x01 /* MIPS R2360 FPC ISA I */ 697 #define MIPS_R2010 0x02 /* MIPS R2010 FPC ISA I */ 698 #define MIPS_R3010 0x03 /* MIPS R3010 FPC ISA I */ 699 #define MIPS_R6010 0x04 /* MIPS R6010 FPC ISA II */ 700 #define MIPS_R4010 0x05 /* MIPS R4010 FPC ISA II */ 701 #define MIPS_R31LSI 0x06 /* LSI Logic derivate ISA I */ 702 #define MIPS_R3TOSH 0x22 /* Toshiba R3000 based FPU ISA I */ 703 704 #ifdef ENABLE_MIPS_TX3900 705 #include <mips/r3900regs.h> 706 #endif 707 708 #endif /* _MIPS_CPUREGS_H_ */ 709
Indexes created Tue Oct 28 12:10:06 GMT 2025