cpuregs.h revision 1.47.4.3
1 /* $NetBSD: cpuregs.h,v 1.47.4.3 2002/04/01 07:40:58 nathanw Exp $ */ 2 3 /* 4 * Copyright (c) 1992, 1993 5 * The Regents of the University of California. All rights reserved. 6 * 7 * This code is derived from software contributed to Berkeley by 8 * Ralph Campbell and Rick Macklem. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the University of 21 * California, Berkeley and its contributors. 22 * 4. Neither the name of the University nor the names of its contributors 23 * may be used to endorse or promote products derived from this software 24 * without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 27 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 28 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 29 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 30 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 31 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 32 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 33 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 34 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 35 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 36 * SUCH DAMAGE. 37 * 38 * @(#)machConst.h 8.1 (Berkeley) 6/10/93 39 * 40 * machConst.h -- 41 * 42 * Machine dependent constants. 43 * 44 * Copyright (C) 1989 Digital Equipment Corporation. 45 * Permission to use, copy, modify, and distribute this software and 46 * its documentation for any purpose and without fee is hereby granted, 47 * provided that the above copyright notice appears in all copies. 48 * Digital Equipment Corporation makes no representations about the 49 * suitability of this software for any purpose. It is provided "as is" 50 * without express or implied warranty. 51 * 52 * from: Header: /sprite/src/kernel/mach/ds3100.md/RCS/machConst.h, 53 * v 9.2 89/10/21 15:55:22 jhh Exp SPRITE (DECWRL) 54 * from: Header: /sprite/src/kernel/mach/ds3100.md/RCS/machAddrs.h, 55 * v 1.2 89/08/15 18:28:21 rab Exp SPRITE (DECWRL) 56 * from: Header: /sprite/src/kernel/vm/ds3100.md/RCS/vmPmaxConst.h, 57 * v 9.1 89/09/18 17:33:00 shirriff Exp SPRITE (DECWRL) 58 */ 59 60 #ifndef _MIPS_CPUREGS_H_ 61 #define _MIPS_CPUREGS_H_ 62 63 #include <sys/cdefs.h> /* For __CONCAT() */ 64 /* 65 * Address space. 66 * 32-bit mips CPUS partition their 32-bit address space into four segments: 67 * 68 * kuseg 0x00000000 - 0x7fffffff User virtual mem, mapped 69 * kseg0 0x80000000 - 0x9fffffff Physical memory, cached, unmapped 70 * kseg1 0xa0000000 - 0xbfffffff Physical memory, uncached, unmapped 71 * kseg2 0xc0000000 - 0xffffffff kernel-virtual, mapped 72 * 73 * mips1 physical memory is limited to 512Mbytes, which is 74 * doubly mapped in kseg0 (cached) and kseg1 (uncached.) 75 * Caching of mapped addresses is controlled by bits in the TLB entry. 76 */ 77 78 #define MIPS_KUSEG_START 0x0 79 #define MIPS_KSEG0_START 0x80000000 80 #define MIPS_KSEG1_START 0xa0000000 81 #define MIPS_KSEG2_START 0xc0000000 82 #define MIPS_MAX_MEM_ADDR 0xbe000000 83 #define MIPS_RESERVED_ADDR 0xbfc80000 84 85 #define MIPS_PHYS_MASK 0x1fffffff 86 87 #define MIPS_KSEG0_TO_PHYS(x) ((unsigned)(x) & MIPS_PHYS_MASK) 88 #define MIPS_PHYS_TO_KSEG0(x) ((unsigned)(x) | MIPS_KSEG0_START) 89 #define MIPS_KSEG1_TO_PHYS(x) ((unsigned)(x) & MIPS_PHYS_MASK) 90 #define MIPS_PHYS_TO_KSEG1(x) ((unsigned)(x) | MIPS_KSEG1_START) 91 92 /* Map virtual address to index in mips3 r4k virtually-indexed cache */ 93 #define MIPS3_VA_TO_CINDEX(x) \ 94 ((unsigned)(x) & 0xffffff | MIPS_KSEG0_START) 95 96 #define MIPS_PHYS_TO_XKPHYS(cca,x) \ 97 ((0x2ULL << 62) | ((unsigned long long)(cca) << 59) | (x)) 98 #define MIPS_XKPHYS_TO_PHYS(x) ((x) & 0x0effffffffffffffULL) 99 100 /* CPU dependent mtc0 hazard hook */ 101 #define COP0_SYNC /* nothing */ 102 103 /* 104 * The bits in the cause register. 105 * 106 * Bits common to r3000 and r4000: 107 * 108 * MIPS_CR_BR_DELAY Exception happened in branch delay slot. 109 * MIPS_CR_COP_ERR Coprocessor error. 110 * MIPS_CR_IP Interrupt pending bits defined below. 111 * (same meaning as in CAUSE register). 112 * MIPS_CR_EXC_CODE The exception type (see exception codes below). 113 * 114 * Differences: 115 * r3k has 4 bits of execption type, r4k has 5 bits. 116 */ 117 #define MIPS_CR_BR_DELAY 0x80000000 118 #define MIPS_CR_COP_ERR 0x30000000 119 #define MIPS1_CR_EXC_CODE 0x0000003C /* four bits */ 120 #define MIPS3_CR_EXC_CODE 0x0000007C /* five bits */ 121 #define MIPS_CR_IP 0x0000FF00 122 #define MIPS_CR_EXC_CODE_SHIFT 2 123 124 /* 125 * The bits in the status register. All bits are active when set to 1. 126 * 127 * R3000 status register fields: 128 * MIPS_SR_CO_USABILITY Control the usability of the four coprocessors. 129 * MIPS_SR_BOOT_EXC_VEC Use alternate exception vectors. 130 * MIPS_SR_TLB_SHUTDOWN TLB disabled. 131 * 132 * MIPS_SR_INT_IE Master (current) interrupt enable bit. 133 * 134 * Differences: 135 * r3k has cache control is via frobbing SR register bits, whereas the 136 * r4k cache control is via explicit instructions. 137 * r3k has a 3-entry stack of kernel/user bits, whereas the 138 * r4k has kernel/supervisor/user. 139 */ 140 #define MIPS_SR_COP_USABILITY 0xf0000000 141 #define MIPS_SR_COP_0_BIT 0x10000000 142 #define MIPS_SR_COP_1_BIT 0x20000000 143 144 /* r4k and r3k differences, see below */ 145 146 #define MIPS_SR_BOOT_EXC_VEC 0x00400000 147 #define MIPS_SR_TLB_SHUTDOWN 0x00200000 148 149 /* r4k and r3k differences, see below */ 150 151 #define MIPS_SR_INT_IE 0x00000001 152 /*#define MIPS_SR_MBZ 0x0f8000c0*/ /* Never used, true for r3k */ 153 /*#define MIPS_SR_INT_MASK 0x0000ff00*/ 154 155 156 /* 157 * The R2000/R3000-specific status register bit definitions. 158 * all bits are active when set to 1. 159 * 160 * MIPS_SR_PARITY_ERR Parity error. 161 * MIPS_SR_CACHE_MISS Most recent D-cache load resulted in a miss. 162 * MIPS_SR_PARITY_ZERO Zero replaces outgoing parity bits. 163 * MIPS_SR_SWAP_CACHES Swap I-cache and D-cache. 164 * MIPS_SR_ISOL_CACHES Isolate D-cache from main memory. 165 * Interrupt enable bits defined below. 166 * MIPS_SR_KU_OLD Old kernel/user mode bit. 1 => user mode. 167 * MIPS_SR_INT_ENA_OLD Old interrupt enable bit. 168 * MIPS_SR_KU_PREV Previous kernel/user mode bit. 1 => user mode. 169 * MIPS_SR_INT_ENA_PREV Previous interrupt enable bit. 170 * MIPS_SR_KU_CUR Current kernel/user mode bit. 1 => user mode. 171 */ 172 173 #define MIPS1_PARITY_ERR 0x00100000 174 #define MIPS1_CACHE_MISS 0x00080000 175 #define MIPS1_PARITY_ZERO 0x00040000 176 #define MIPS1_SWAP_CACHES 0x00020000 177 #define MIPS1_ISOL_CACHES 0x00010000 178 179 #define MIPS1_SR_KU_OLD 0x00000020 /* 2nd stacked KU/IE*/ 180 #define MIPS1_SR_INT_ENA_OLD 0x00000010 /* 2nd stacked KU/IE*/ 181 #define MIPS1_SR_KU_PREV 0x00000008 /* 1st stacked KU/IE*/ 182 #define MIPS1_SR_INT_ENA_PREV 0x00000004 /* 1st stacked KU/IE*/ 183 #define MIPS1_SR_KU_CUR 0x00000002 /* current KU */ 184 185 /* backwards compatibility */ 186 #define MIPS_SR_PARITY_ERR MIPS1_PARITY_ERR 187 #define MIPS_SR_CACHE_MISS MIPS1_CACHE_MISS 188 #define MIPS_SR_PARITY_ZERO MIPS1_PARITY_ZERO 189 #define MIPS_SR_SWAP_CACHES MIPS1_SWAP_CACHES 190 #define MIPS_SR_ISOL_CACHES MIPS1_ISOL_CACHES 191 192 #define MIPS_SR_KU_OLD MIPS1_SR_KU_OLD 193 #define MIPS_SR_INT_ENA_OLD MIPS1_SR_INT_ENA_OLD 194 #define MIPS_SR_KU_PREV MIPS1_SR_KU_PREV 195 #define MIPS_SR_KU_CUR MIPS1_SR_KU_CUR 196 #define MIPS_SR_INT_ENA_PREV MIPS1_SR_INT_ENA_PREV 197 198 /* 199 * R4000 status register bit definitons, 200 * where different from r2000/r3000. 201 */ 202 #define MIPS3_SR_XX 0x80000000 203 #define MIPS3_SR_RP 0x08000000 204 #define MIPS3_SR_FR_32 0x04000000 205 #define MIPS3_SR_RE 0x02000000 206 207 #define MIPS3_SR_DIAG_DL 0x01000000 /* QED 52xx */ 208 #define MIPS3_SR_DIAG_IL 0x00800000 /* QED 52xx */ 209 #define MIPS3_SR_DIAG_BEV 0x00400000 210 #define MIPS3_SR_SOFT_RESET 0x00100000 211 #define MIPS3_SR_EIE 0x00100000 /* TX79/R5900 */ 212 #define MIPS3_SR_DIAG_CH 0x00040000 213 #define MIPS3_SR_DIAG_CE 0x00020000 214 #define MIPS3_SR_DIAG_PE 0x00010000 215 #define MIPS3_SR_KX 0x00000080 216 #define MIPS3_SR_SX 0x00000040 217 #define MIPS3_SR_UX 0x00000020 218 #define MIPS3_SR_KSU_MASK 0x00000018 219 #define MIPS3_SR_KSU_USER 0x00000010 220 #define MIPS3_SR_KSU_SUPER 0x00000008 221 #define MIPS3_SR_KSU_KERNEL 0x00000000 222 #define MIPS3_SR_ERL 0x00000004 223 #define MIPS3_SR_EXL 0x00000002 224 225 #ifdef MIPS3_5900 226 #undef MIPS_SR_INT_IE 227 #define MIPS_SR_INT_IE 0x00010001 /* XXX */ 228 #endif 229 230 #define MIPS_SR_SOFT_RESET MIPS3_SR_SOFT_RESET 231 #define MIPS_SR_DIAG_CH MIPS3_SR_DIAG_CH 232 #define MIPS_SR_DIAG_CE MIPS3_SR_DIAG_CE 233 #define MIPS_SR_DIAG_PE MIPS3_SR_DIAG_PE 234 #define MIPS_SR_KX MIPS3_SR_KX 235 #define MIPS_SR_SX MIPS3_SR_SX 236 #define MIPS_SR_UX MIPS3_SR_UX 237 238 #define MIPS_SR_KSU_MASK MIPS3_SR_KSU_MASK 239 #define MIPS_SR_KSU_USER MIPS3_SR_KSU_USER 240 #define MIPS_SR_KSU_SUPER MIPS3_SR_KSU_SUPER 241 #define MIPS_SR_KSU_KERNEL MIPS3_SR_KSU_KERNEL 242 #define MIPS_SR_ERL MIPS3_SR_ERL 243 #define MIPS_SR_EXL MIPS3_SR_EXL 244 245 246 /* 247 * The interrupt masks. 248 * If a bit in the mask is 1 then the interrupt is enabled (or pending). 249 */ 250 #define MIPS_INT_MASK 0xff00 251 #define MIPS_INT_MASK_5 0x8000 252 #define MIPS_INT_MASK_4 0x4000 253 #define MIPS_INT_MASK_3 0x2000 254 #define MIPS_INT_MASK_2 0x1000 255 #define MIPS_INT_MASK_1 0x0800 256 #define MIPS_INT_MASK_0 0x0400 257 #define MIPS_HARD_INT_MASK 0xfc00 258 #define MIPS_SOFT_INT_MASK_1 0x0200 259 #define MIPS_SOFT_INT_MASK_0 0x0100 260 261 /* 262 * mips3 CPUs have on-chip timer at INT_MASK_5. Each platform can 263 * choose to enable this interrupt. 264 */ 265 #if defined(MIPS3_ENABLE_CLOCK_INTR) 266 #define MIPS3_INT_MASK MIPS_INT_MASK 267 #define MIPS3_HARD_INT_MASK MIPS_HARD_INT_MASK 268 #else 269 #define MIPS3_INT_MASK (MIPS_INT_MASK & ~MIPS_INT_MASK_5) 270 #define MIPS3_HARD_INT_MASK (MIPS_HARD_INT_MASK & ~MIPS_INT_MASK_5) 271 #endif 272 273 /* 274 * The bits in the context register. 275 */ 276 #define MIPS1_CNTXT_PTE_BASE 0xFFE00000 277 #define MIPS1_CNTXT_BAD_VPN 0x001FFFFC 278 279 #define MIPS3_CNTXT_PTE_BASE 0xFF800000 280 #define MIPS3_CNTXT_BAD_VPN2 0x007FFFF0 281 282 /* 283 * The bits in the MIPS3 config register. 284 * 285 * bit 0..5: R/W, Bit 6..31: R/O 286 */ 287 288 /* kseg0 coherency algorithm - see MIPS3_TLB_ATTR values */ 289 #define MIPS3_CONFIG_K0_MASK 0x00000007 290 291 /* 292 * R/W Update on Store Conditional 293 * 0: Store Conditional uses coherency algorithm specified by TLB 294 * 1: Store Conditional uses cacheable coherent update on write 295 */ 296 #define MIPS3_CONFIG_CU 0x00000008 297 298 #define MIPS3_CONFIG_DB 0x00000010 /* Primary D-cache line size */ 299 #define MIPS3_CONFIG_IB 0x00000020 /* Primary I-cache line size */ 300 #define MIPS3_CONFIG_CACHE_L1_LSIZE(config, bit) \ 301 (((config) & (bit)) ? 32 : 16) 302 303 #define MIPS3_CONFIG_DC_MASK 0x000001c0 /* Primary D-cache size */ 304 #define MIPS3_CONFIG_DC_SHIFT 6 305 #define MIPS3_CONFIG_IC_MASK 0x00000e00 /* Primary I-cache size */ 306 #define MIPS3_CONFIG_IC_SHIFT 9 307 #define MIPS3_CONFIG_C_DEFBASE 0x1000 /* default base 2^12 */ 308 #ifdef MIPS3_4100 /* VR4100 core */ 309 /* XXXCDC: THIS MIPS3_4100 SPECIAL CASE SHOULD GO AWAY */ 310 #define MIPS3_CONFIG_CS 0x00001000 /* cache size mode indication*/ 311 #define MIPS3_CONFIG_CACHE_SIZE(config, mask, dummy, shift) \ 312 ((((config)&MIPS3_CONFIG_CS)?0x400:0x1000) << (((config) & (mask)) >> (shift))) 313 #else 314 #define MIPS3_CONFIG_CACHE_SIZE(config, mask, base, shift) \ 315 ((base) << (((config) & (mask)) >> (shift))) 316 #endif 317 318 /* Block ordering: 0: sequential, 1: sub-block */ 319 #define MIPS3_CONFIG_EB 0x00002000 320 321 /* ECC mode - 0: ECC mode, 1: parity mode */ 322 #define MIPS3_CONFIG_EM 0x00004000 323 324 /* BigEndianMem - 0: kernel and memory are little endian, 1: big endian */ 325 #define MIPS3_CONFIG_BE 0x00008000 326 327 /* Dirty Shared coherency state - 0: enabled, 1: disabled */ 328 #define MIPS3_CONFIG_SM 0x00010000 329 330 /* Secondary Cache - 0: present, 1: not present */ 331 #define MIPS3_CONFIG_SC 0x00020000 332 333 /* System Port width - 0: 64-bit, 1: 32-bit (QED RM523x), 2,3: reserved */ 334 #define MIPS3_CONFIG_EW_MASK 0x000c0000 335 #define MIPS3_CONFIG_EW_SHIFT 18 336 337 /* Secondary Cache port width - 0: 128-bit data path to S-cache, 1: reserved */ 338 #define MIPS3_CONFIG_SW 0x00100000 339 340 /* Split Secondary Cache Mode - 0: I/D mixed, 1: I/D separated by SCAddr(17) */ 341 #define MIPS3_CONFIG_SS 0x00200000 342 343 /* Secondary Cache line size */ 344 #define MIPS3_CONFIG_SB_MASK 0x00c00000 345 #define MIPS3_CONFIG_SB_SHIFT 22 346 #define MIPS3_CONFIG_CACHE_L2_LSIZE(config) \ 347 (0x10 << (((config) & MIPS3_CONFIG_SB_MASK) >> MIPS3_CONFIG_SB_SHIFT)) 348 349 /* Write back data rate */ 350 #define MIPS3_CONFIG_EP_MASK 0x0f000000 351 #define MIPS3_CONFIG_EP_SHIFT 24 352 353 /* System clock ratio - this value is CPU dependent */ 354 #define MIPS3_CONFIG_EC_MASK 0x70000000 355 #define MIPS3_CONFIG_EC_SHIFT 28 356 357 /* Master-Checker Mode - 1: enabled */ 358 #define MIPS3_CONFIG_CM 0x80000000 359 360 /* 361 * Location of exception vectors. 362 * 363 * Common vectors: reset and UTLB miss. 364 */ 365 #define MIPS_RESET_EXC_VEC 0xBFC00000 366 #define MIPS_UTLB_MISS_EXC_VEC 0x80000000 367 368 /* 369 * MIPS-1 general exception vector (everything else) 370 */ 371 #define MIPS1_GEN_EXC_VEC 0x80000080 372 373 /* 374 * MIPS-III exception vectors 375 */ 376 #define MIPS3_XTLB_MISS_EXC_VEC 0x80000080 377 #define MIPS3_CACHE_ERR_EXC_VEC 0x80000100 378 #define MIPS3_GEN_EXC_VEC 0x80000180 379 380 /* 381 * TX79 (R5900) exception vectors 382 */ 383 #define MIPS_R5900_COUNTER_EXC_VEC 0x80000080 384 #define MIPS_R5900_DEBUG_EXC_VEC 0x80000100 385 386 /* 387 * MIPS32/MIPS64 (and some MIPS3) dedicated interrupt vector. 388 */ 389 #define MIPS3_INTR_EXC_VEC 0x80000200 390 391 /* 392 * Coprocessor 0 registers: 393 * 394 * v--- width for mips I,III,32,64 395 * (3=32bit, 6=64bit, i=impl dep) 396 * 0 MIPS_COP_0_TLB_INDEX 3333 TLB Index. 397 * 1 MIPS_COP_0_TLB_RANDOM 3333 TLB Random. 398 * 2 MIPS_COP_0_TLB_LOW 3... r3k TLB entry low. 399 * 2 MIPS_COP_0_TLB_LO0 .636 r4k TLB entry low. 400 * 3 MIPS_COP_0_TLB_LO1 .636 r4k TLB entry low, extended. 401 * 4 MIPS_COP_0_TLB_CONTEXT 3636 TLB Context. 402 * 5 MIPS_COP_0_TLB_PG_MASK .333 TLB Page Mask register. 403 * 6 MIPS_COP_0_TLB_WIRED .333 Wired TLB number. 404 * 8 MIPS_COP_0_BAD_VADDR 3636 Bad virtual address. 405 * 9 MIPS_COP_0_COUNT .333 Count register. 406 * 10 MIPS_COP_0_TLB_HI 3636 TLB entry high. 407 * 11 MIPS_COP_0_COMPARE .333 Compare (against Count). 408 * 12 MIPS_COP_0_STATUS 3333 Status register. 409 * 13 MIPS_COP_0_CAUSE 3333 Exception cause register. 410 * 14 MIPS_COP_0_EXC_PC 3636 Exception PC. 411 * 15 MIPS_COP_0_PRID 3333 Processor revision identifier. 412 * 16 MIPS_COP_0_CONFIG 3333 Configuration register. 413 * 16/1 MIPS_COP_0_CONFIG1 ..33 Configuration register 1. 414 * 16/2 MIPS_COP_0_CONFIG2 ..33 Configuration register 2. 415 * 16/3 MIPS_COP_0_CONFIG3 ..33 Configuration register 3. 416 * 17 MIPS_COP_0_LLADDR .336 Load Linked Address. 417 * 18 MIPS_COP_0_WATCH_LO .336 WatchLo register. 418 * 19 MIPS_COP_0_WATCH_HI .333 WatchHi register. 419 * 20 MIPS_COP_0_TLB_XCONTEXT .6.6 TLB XContext register. 420 * 23 MIPS_COP_0_DEBUG .... Debug JTAG register. 421 * 24 MIPS_COP_0_DEPC .... DEPC JTAG register. 422 * 25 MIPS_COP_0_PERFCNT ..36 Performance Counter register. 423 * 26 MIPS_COP_0_ECC .3ii ECC / Error Control register. 424 * 27 MIPS_COP_0_CACHE_ERR .3ii Cache Error register. 425 * 28/0 MIPS_COP_0_TAG_LO .3ii Cache TagLo register (instr). 426 * 28/1 MIPS_COP_0_DATA_LO ..ii Cache DataLo register (instr). 427 * 28/2 MIPS_COP_0_TAG_LO ..ii Cache TagLo register (data). 428 * 28/3 MIPS_COP_0_DATA_LO ..ii Cache DataLo register (data). 429 * 29/0 MIPS_COP_0_TAG_HI .3ii Cache TagHi register (instr). 430 * 29/1 MIPS_COP_0_DATA_HI ..ii Cache DataHi register (instr). 431 * 29/2 MIPS_COP_0_TAG_HI ..ii Cache TagHi register (data). 432 * 29/3 MIPS_COP_0_DATA_HI ..ii Cache DataHi register (data). 433 * 30 MIPS_COP_0_ERROR_PC .636 Error EPC register. 434 * 31 MIPS_COP_0_DESAVE .... DESAVE JTAG register. 435 */ 436 #ifdef _LOCORE 437 #define _(n) __CONCAT($,n) 438 #else 439 #define _(n) n 440 #endif 441 #define MIPS_COP_0_TLB_INDEX _(0) 442 #define MIPS_COP_0_TLB_RANDOM _(1) 443 /* Name and meaning of TLB bits for $2 differ on r3k and r4k. */ 444 445 #define MIPS_COP_0_TLB_CONTEXT _(4) 446 /* $5 and $6 new with MIPS-III */ 447 #define MIPS_COP_0_BAD_VADDR _(8) 448 #define MIPS_COP_0_TLB_HI _(10) 449 #define MIPS_COP_0_STATUS_REG _(12) 450 #define MIPS_COP_0_CAUSE_REG _(13) 451 #define MIPS_COP_0_STATUS _(12) 452 #define MIPS_COP_0_CAUSE _(13) 453 #define MIPS_COP_0_EXC_PC _(14) 454 #define MIPS_COP_0_PRID _(15) 455 456 457 /* MIPS-I */ 458 #define MIPS_COP_0_TLB_LOW _(2) 459 460 /* MIPS-III */ 461 #define MIPS_COP_0_TLB_LO0 _(2) 462 #define MIPS_COP_0_TLB_LO1 _(3) 463 464 #define MIPS_COP_0_TLB_PG_MASK _(5) 465 #define MIPS_COP_0_TLB_WIRED _(6) 466 467 #define MIPS_COP_0_COUNT _(9) 468 #define MIPS_COP_0_COMPARE _(11) 469 470 #define MIPS_COP_0_CONFIG _(16) 471 #define MIPS_COP_0_LLADDR _(17) 472 #define MIPS_COP_0_WATCH_LO _(18) 473 #define MIPS_COP_0_WATCH_HI _(19) 474 #define MIPS_COP_0_TLB_XCONTEXT _(20) 475 #define MIPS_COP_0_ECC _(26) 476 #define MIPS_COP_0_CACHE_ERR _(27) 477 #define MIPS_COP_0_TAG_LO _(28) 478 #define MIPS_COP_0_TAG_HI _(29) 479 #define MIPS_COP_0_ERROR_PC _(30) 480 481 /* MIPS32/64 */ 482 #define MIPS_COP_0_DEBUG _(23) 483 #define MIPS_COP_0_DEPC _(24) 484 #define MIPS_COP_0_PERFCNT _(25) 485 #define MIPS_COP_0_DATA_LO _(28) 486 #define MIPS_COP_0_DATA_HI _(29) 487 #define MIPS_COP_0_DESAVE _(31) 488 489 /* 490 * Values for the code field in a break instruction. 491 */ 492 #define MIPS_BREAK_INSTR 0x0000000d 493 #define MIPS_BREAK_VAL_MASK 0x03ff0000 494 #define MIPS_BREAK_VAL_SHIFT 16 495 #define MIPS_BREAK_KDB_VAL 512 496 #define MIPS_BREAK_SSTEP_VAL 513 497 #define MIPS_BREAK_BRKPT_VAL 514 498 #define MIPS_BREAK_SOVER_VAL 515 499 #define MIPS_BREAK_KDB (MIPS_BREAK_INSTR | \ 500 (MIPS_BREAK_KDB_VAL << MIPS_BREAK_VAL_SHIFT)) 501 #define MIPS_BREAK_SSTEP (MIPS_BREAK_INSTR | \ 502 (MIPS_BREAK_SSTEP_VAL << MIPS_BREAK_VAL_SHIFT)) 503 #define MIPS_BREAK_BRKPT (MIPS_BREAK_INSTR | \ 504 (MIPS_BREAK_BRKPT_VAL << MIPS_BREAK_VAL_SHIFT)) 505 #define MIPS_BREAK_SOVER (MIPS_BREAK_INSTR | \ 506 (MIPS_BREAK_SOVER_VAL << MIPS_BREAK_VAL_SHIFT)) 507 508 /* 509 * Mininum and maximum cache sizes. 510 */ 511 #define MIPS_MIN_CACHE_SIZE (16 * 1024) 512 #define MIPS_MAX_CACHE_SIZE (256 * 1024) 513 #define MIPS3_MAX_PCACHE_SIZE (32 * 1024) /* max. primary cache size */ 514 515 /* 516 * The floating point version and status registers. 517 */ 518 #define MIPS_FPU_ID $0 519 #define MIPS_FPU_CSR $31 520 521 /* 522 * The floating point coprocessor status register bits. 523 */ 524 #define MIPS_FPU_ROUNDING_BITS 0x00000003 525 #define MIPS_FPU_ROUND_RN 0x00000000 526 #define MIPS_FPU_ROUND_RZ 0x00000001 527 #define MIPS_FPU_ROUND_RP 0x00000002 528 #define MIPS_FPU_ROUND_RM 0x00000003 529 #define MIPS_FPU_STICKY_BITS 0x0000007c 530 #define MIPS_FPU_STICKY_INEXACT 0x00000004 531 #define MIPS_FPU_STICKY_UNDERFLOW 0x00000008 532 #define MIPS_FPU_STICKY_OVERFLOW 0x00000010 533 #define MIPS_FPU_STICKY_DIV0 0x00000020 534 #define MIPS_FPU_STICKY_INVALID 0x00000040 535 #define MIPS_FPU_ENABLE_BITS 0x00000f80 536 #define MIPS_FPU_ENABLE_INEXACT 0x00000080 537 #define MIPS_FPU_ENABLE_UNDERFLOW 0x00000100 538 #define MIPS_FPU_ENABLE_OVERFLOW 0x00000200 539 #define MIPS_FPU_ENABLE_DIV0 0x00000400 540 #define MIPS_FPU_ENABLE_INVALID 0x00000800 541 #define MIPS_FPU_EXCEPTION_BITS 0x0003f000 542 #define MIPS_FPU_EXCEPTION_INEXACT 0x00001000 543 #define MIPS_FPU_EXCEPTION_UNDERFLOW 0x00002000 544 #define MIPS_FPU_EXCEPTION_OVERFLOW 0x00004000 545 #define MIPS_FPU_EXCEPTION_DIV0 0x00008000 546 #define MIPS_FPU_EXCEPTION_INVALID 0x00010000 547 #define MIPS_FPU_EXCEPTION_UNIMPL 0x00020000 548 #define MIPS_FPU_COND_BIT 0x00800000 549 #define MIPS_FPU_FLUSH_BIT 0x01000000 /* r4k, MBZ on r3k */ 550 #define MIPS1_FPC_MBZ_BITS 0xff7c0000 551 #define MIPS3_FPC_MBZ_BITS 0xfe7c0000 552 553 554 /* 555 * Constants to determine if have a floating point instruction. 556 */ 557 #define MIPS_OPCODE_SHIFT 26 558 #define MIPS_OPCODE_C1 0x11 559 #define MIPS_OPCODE_LWC1 0x31 560 #define MIPS_OPCODE_LDC1 0x35 561 #define MIPS_OPCODE_SWC1 0x39 562 #define MIPS_OPCODE_SDC1 0x3d 563 564 565 /* 566 * The low part of the TLB entry. 567 */ 568 #define MIPS1_TLB_PFN 0xfffff000 569 #define MIPS1_TLB_NON_CACHEABLE_BIT 0x00000800 570 #define MIPS1_TLB_DIRTY_BIT 0x00000400 571 #define MIPS1_TLB_VALID_BIT 0x00000200 572 #define MIPS1_TLB_GLOBAL_BIT 0x00000100 573 574 #define MIPS3_TLB_PFN 0x3fffffc0 575 #define MIPS3_TLB_ATTR_MASK 0x00000038 576 #define MIPS3_TLB_ATTR_SHIFT 3 577 #define MIPS3_TLB_DIRTY_BIT 0x00000004 578 #define MIPS3_TLB_VALID_BIT 0x00000002 579 #define MIPS3_TLB_GLOBAL_BIT 0x00000001 580 581 #define MIPS1_TLB_PHYS_PAGE_SHIFT 12 582 #define MIPS3_TLB_PHYS_PAGE_SHIFT 6 583 #define MIPS1_TLB_PF_NUM MIPS1_TLB_PFN 584 #define MIPS3_TLB_PF_NUM MIPS3_TLB_PFN 585 #define MIPS1_TLB_MOD_BIT MIPS1_TLB_DIRTY_BIT 586 #define MIPS3_TLB_MOD_BIT MIPS3_TLB_DIRTY_BIT 587 588 /* 589 * MIPS3_TLB_ATTR values - coherency algorithm: 590 * 0: cacheable, noncoherent, write-through, no write allocate 591 * 1: cacheable, noncoherent, write-through, write allocate 592 * 2: uncached 593 * 3: cacheable, noncoherent, write-back (noncoherent) 594 * 4: cacheable, coherent, write-back, exclusive (exclusive) 595 * 5: cacheable, coherent, write-back, exclusive on write (sharable) 596 * 6: cacheable, coherent, write-back, update on write (update) 597 * 7: uncached, accelerated (gather STORE operations) 598 */ 599 #define MIPS3_TLB_ATTR_WT 0 /* IDT */ 600 #define MIPS3_TLB_ATTR_WT_WRITEALLOCATE 1 /* IDT */ 601 #define MIPS3_TLB_ATTR_UNCACHED 2 /* R4000/R4400, IDT */ 602 #define MIPS3_TLB_ATTR_WB_NONCOHERENT 3 /* R4000/R4400, IDT */ 603 #define MIPS3_TLB_ATTR_WB_EXCLUSIVE 4 /* R4000/R4400 */ 604 #define MIPS3_TLB_ATTR_WB_SHARABLE 5 /* R4000/R4400 */ 605 #define MIPS3_TLB_ATTR_WB_UPDATE 6 /* R4000/R4400 */ 606 #define MIPS4_TLB_ATTR_UNCACHED_ACCELERATED 7 /* R10000 */ 607 608 609 /* 610 * The high part of the TLB entry. 611 */ 612 #define MIPS1_TLB_VPN 0xfffff000 613 #define MIPS1_TLB_PID 0x00000fc0 614 #define MIPS1_TLB_PID_SHIFT 6 615 616 #define MIPS3_TLB_VPN2 0xffffe000 617 #define MIPS3_TLB_ASID 0x000000ff 618 619 #define MIPS1_TLB_VIRT_PAGE_NUM MIPS1_TLB_VPN 620 #define MIPS3_TLB_VIRT_PAGE_NUM MIPS3_TLB_VPN2 621 #define MIPS3_TLB_PID MIPS3_TLB_ASID 622 #define MIPS_TLB_VIRT_PAGE_SHIFT 12 623 624 /* 625 * r3000: shift count to put the index in the right spot. 626 */ 627 #define MIPS1_TLB_INDEX_SHIFT 8 628 629 /* 630 * The first TLB that write random hits. 631 */ 632 #define MIPS1_TLB_FIRST_RAND_ENTRY 8 633 #define MIPS3_TLB_WIRED_UPAGES 1 634 635 /* 636 * The number of process id entries. 637 */ 638 #define MIPS1_TLB_NUM_PIDS 64 639 #define MIPS3_TLB_NUM_ASIDS 256 640 641 /* 642 * Patch codes to hide CPU design differences between MIPS1 and MIPS3. 643 */ 644 645 /* XXX simonb: this is before MIPS3_PLUS is defined (and is ugly!) */ 646 647 #if !(defined(MIPS3) || defined(MIPS4) || defined(MIPS32) || defined(MIPS64)) \ 648 && defined(MIPS1) /* XXX simonb must be neater! */ 649 #define MIPS_TLB_PID_SHIFT MIPS1_TLB_PID_SHIFT 650 #define MIPS_TLB_NUM_PIDS MIPS1_TLB_NUM_PIDS 651 #endif 652 653 #if (defined(MIPS3) || defined(MIPS4) || defined(MIPS32) || defined(MIPS64)) \ 654 && !defined(MIPS1) /* XXX simonb must be neater! */ 655 #define MIPS_TLB_PID_SHIFT 0 656 #define MIPS_TLB_NUM_PIDS MIPS3_TLB_NUM_ASIDS 657 #endif 658 659 660 #if !defined(MIPS_TLB_PID_SHIFT) 661 #define MIPS_TLB_PID_SHIFT \ 662 ((MIPS_HAS_R4K_MMU) ? 0 : MIPS1_TLB_PID_SHIFT) 663 664 #define MIPS_TLB_NUM_PIDS \ 665 ((MIPS_HAS_R4K_MMU) ? MIPS3_TLB_NUM_ASIDS : MIPS1_TLB_NUM_PIDS) 666 #endif 667 668 /* 669 * CPU processor revision IDs for company ID == 0 (non mips32/64 chips) 670 */ 671 #define MIPS_R2000 0x01 /* MIPS R2000 ISA I */ 672 #define MIPS_R3000 0x02 /* MIPS R3000 ISA I */ 673 #define MIPS_R6000 0x03 /* MIPS R6000 ISA II */ 674 #define MIPS_R4000 0x04 /* MIPS R4000/R4400 ISA III */ 675 #define MIPS_R3LSI 0x05 /* LSI Logic R3000 derivative ISA I */ 676 #define MIPS_R6000A 0x06 /* MIPS R6000A ISA II */ 677 #define MIPS_R3IDT 0x07 /* IDT R3041 or RC36100 ISA I */ 678 #define MIPS_R10000 0x09 /* MIPS R10000 ISA IV */ 679 #define MIPS_R4200 0x0a /* NEC VR4200 ISA III */ 680 #define MIPS_R4300 0x0b /* NEC VR4300 ISA III */ 681 #define MIPS_R4100 0x0c /* NEC VR4100 ISA III */ 682 #define MIPS_R12000 0x0e /* MIPS R12000 ISA IV */ 683 #define MIPS_R14000 0x0f /* MIPS R14000 ISA IV */ 684 #define MIPS_R8000 0x10 /* MIPS R8000 Blackbird/TFP ISA IV */ 685 #define MIPS_RC32300 0x18 /* IDT RC32334,332,355 ISA 32 */ 686 #define MIPS_R4600 0x20 /* QED R4600 Orion ISA III */ 687 #define MIPS_R4700 0x21 /* QED R4700 Orion ISA III */ 688 #define MIPS_R3SONY 0x21 /* Sony R3000 based ISA I */ 689 #define MIPS_R4650 0x22 /* QED R4650 ISA III */ 690 #define MIPS_TX3900 0x22 /* Toshiba TX39 family ISA I */ 691 #define MIPS_R5000 0x23 /* MIPS R5000 ISA IV */ 692 #define MIPS_R3NKK 0x23 /* NKK R3000 based ISA I */ 693 #define MIPS_RC32364 0x26 /* IDT RC32364 ISA 32 */ 694 #define MIPS_RM7000 0x27 /* QED RM7000 ISA IV */ 695 #define MIPS_RM5200 0x28 /* QED RM5200s ISA IV */ 696 #define MIPS_TX4900 0x2d /* Toshiba TX49 family ISA III */ 697 #define MIPS_R5900 0x2e /* Toshiba R5900 (EECore) ISA --- */ 698 #define MIPS_RC64470 0x30 /* IDT RC64474/RC64475 ISA III */ 699 #define MIPS_R5400 0x54 /* NEC VR5400 ISA IV */ 700 701 /* 702 * CPU revision IDs for some prehistoric processors. 703 */ 704 705 /* For MIPS_R3000 */ 706 #define MIPS_REV_R3000 0x20 707 #define MIPS_REV_R3000A 0x30 708 709 /* For MIPS_TX3900 */ 710 #define MIPS_REV_TX3912 0x10 711 #define MIPS_REV_TX3922 0x30 712 #define MIPS_REV_TX3927 0x40 713 714 /* For MIPS_R4000 */ 715 #define MIPS_REV_R4000_A 0x00 716 #define MIPS_REV_R4000_B 0x30 717 #define MIPS_REV_R4400_A 0x40 718 #define MIPS_REV_R4400_B 0x50 719 #define MIPS_REV_R4400_C 0x60 720 721 /* 722 * CPU processor revision IDs for company ID == 1 (MIPS) 723 */ 724 #define MIPS_4Kc 0x80 /* MIPS 4Kc ISA 32 */ 725 #define MIPS_5Kc 0x81 /* MIPS 5Kc ISA 64 */ 726 #define MIPS_4KEc 0x84 /* MIPS 4KEc ISA 32 */ 727 #define MIPS_4KSc 0x86 /* MIPS 4KSc ISA 32 */ 728 729 /* 730 * CPU processor revision IDs for company ID == 3 (Alchemy) 731 */ 732 #define MIPS_AU1000_R1 0x01 /* Alchemy Au1000 (Rev 1) ISA 32 */ 733 #define MIPS_AU1000_R2 0x02 /* Alchemy Au1000 (Rev 2) ISA 32 */ 734 735 /* 736 * CPU processor revision IDs for company ID == 4 (SiByte) 737 */ 738 #define MIPS_SB1 0x01 /* SiByte SB1 ISA 64 */ 739 740 /* 741 * CPU processor revision IDs for company ID == 5 (SandCraft) 742 */ 743 #define MIPS_SR7100 0x04 /* SandCraft SR7100 ISA 64 */ 744 745 /* 746 * FPU processor revision ID 747 */ 748 #define MIPS_SOFT 0x00 /* Software emulation ISA I */ 749 #define MIPS_R2360 0x01 /* MIPS R2360 FPC ISA I */ 750 #define MIPS_R2010 0x02 /* MIPS R2010 FPC ISA I */ 751 #define MIPS_R3010 0x03 /* MIPS R3010 FPC ISA I */ 752 #define MIPS_R6010 0x04 /* MIPS R6010 FPC ISA II */ 753 #define MIPS_R4010 0x05 /* MIPS R4010 FPC ISA II */ 754 #define MIPS_R31LSI 0x06 /* LSI Logic derivate ISA I */ 755 #define MIPS_R3TOSH 0x22 /* Toshiba R3000 based FPU ISA I */ 756 757 #ifdef ENABLE_MIPS_TX3900 758 #include <mips/r3900regs.h> 759 #endif 760 #ifdef MIPS3_5900 761 #include <mips/r5900regs.h> 762 #endif 763 764 #endif /* _MIPS_CPUREGS_H_ */ 765
Indexes created Tue Oct 28 12:10:06 GMT 2025