cpuregs.h revision 1.48
1 /* $NetBSD: cpuregs.h,v 1.48 2001/12/28 04:06:06 shin Exp $ */ 2 3 /* 4 * Copyright (c) 1992, 1993 5 * The Regents of the University of California. All rights reserved. 6 * 7 * This code is derived from software contributed to Berkeley by 8 * Ralph Campbell and Rick Macklem. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the University of 21 * California, Berkeley and its contributors. 22 * 4. Neither the name of the University nor the names of its contributors 23 * may be used to endorse or promote products derived from this software 24 * without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 27 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 28 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 29 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 30 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 31 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 32 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 33 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 34 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 35 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 36 * SUCH DAMAGE. 37 * 38 * @(#)machConst.h 8.1 (Berkeley) 6/10/93 39 * 40 * machConst.h -- 41 * 42 * Machine dependent constants. 43 * 44 * Copyright (C) 1989 Digital Equipment Corporation. 45 * Permission to use, copy, modify, and distribute this software and 46 * its documentation for any purpose and without fee is hereby granted, 47 * provided that the above copyright notice appears in all copies. 48 * Digital Equipment Corporation makes no representations about the 49 * suitability of this software for any purpose. It is provided "as is" 50 * without express or implied warranty. 51 * 52 * from: Header: /sprite/src/kernel/mach/ds3100.md/RCS/machConst.h, 53 * v 9.2 89/10/21 15:55:22 jhh Exp SPRITE (DECWRL) 54 * from: Header: /sprite/src/kernel/mach/ds3100.md/RCS/machAddrs.h, 55 * v 1.2 89/08/15 18:28:21 rab Exp SPRITE (DECWRL) 56 * from: Header: /sprite/src/kernel/vm/ds3100.md/RCS/vmPmaxConst.h, 57 * v 9.1 89/09/18 17:33:00 shirriff Exp SPRITE (DECWRL) 58 */ 59 60 #ifndef _MIPS_CPUREGS_H_ 61 #define _MIPS_CPUREGS_H_ 62 63 /* 64 * Address space. 65 * 32-bit mips CPUS partition their 32-bit address space into four segments: 66 * 67 * kuseg 0x00000000 - 0x7fffffff User virtual mem, mapped 68 * kseg0 0x80000000 - 0x9fffffff Physical memory, cached, unmapped 69 * kseg1 0xa0000000 - 0xbfffffff Physical memory, uncached, unmapped 70 * kseg2 0xc0000000 - 0xffffffff kernel-virtual, mapped 71 * 72 * mips1 physical memory is limited to 512Mbytes, which is 73 * doubly mapped in kseg0 (cached) and kseg1 (uncached.) 74 * Caching of mapped addresses is controlled by bits in the TLB entry. 75 */ 76 77 #define MIPS_KUSEG_START 0x0 78 #define MIPS_KSEG0_START 0x80000000 79 #define MIPS_KSEG1_START 0xa0000000 80 #define MIPS_KSEG2_START 0xc0000000 81 #define MIPS_MAX_MEM_ADDR 0xbe000000 82 #define MIPS_RESERVED_ADDR 0xbfc80000 83 84 #define MIPS_PHYS_MASK 0x1fffffff 85 86 #define MIPS_KSEG0_TO_PHYS(x) ((unsigned)(x) & MIPS_PHYS_MASK) 87 #define MIPS_PHYS_TO_KSEG0(x) ((unsigned)(x) | MIPS_KSEG0_START) 88 #define MIPS_KSEG1_TO_PHYS(x) ((unsigned)(x) & MIPS_PHYS_MASK) 89 #define MIPS_PHYS_TO_KSEG1(x) ((unsigned)(x) | MIPS_KSEG1_START) 90 91 /* Map virtual address to index in mips3 r4k virtually-indexed cache */ 92 #define MIPS3_VA_TO_CINDEX(x) \ 93 ((unsigned)(x) & 0xffffff | MIPS_KSEG0_START) 94 95 /* CPU dependent mtc0 hazard hook */ 96 #define COP0_SYNC /* nothing */ 97 98 /* 99 * The bits in the cause register. 100 * 101 * Bits common to r3000 and r4000: 102 * 103 * MIPS_CR_BR_DELAY Exception happened in branch delay slot. 104 * MIPS_CR_COP_ERR Coprocessor error. 105 * MIPS_CR_IP Interrupt pending bits defined below. 106 * (same meaning as in CAUSE register). 107 * MIPS_CR_EXC_CODE The exception type (see exception codes below). 108 * 109 * Differences: 110 * r3k has 4 bits of execption type, r4k has 5 bits. 111 */ 112 #define MIPS_CR_BR_DELAY 0x80000000 113 #define MIPS_CR_COP_ERR 0x30000000 114 #define MIPS1_CR_EXC_CODE 0x0000003C /* four bits */ 115 #define MIPS3_CR_EXC_CODE 0x0000007C /* five bits */ 116 #define MIPS_CR_IP 0x0000FF00 117 #define MIPS_CR_EXC_CODE_SHIFT 2 118 119 /* 120 * The bits in the status register. All bits are active when set to 1. 121 * 122 * R3000 status register fields: 123 * MIPS_SR_CO_USABILITY Control the usability of the four coprocessors. 124 * MIPS_SR_BOOT_EXC_VEC Use alternate exception vectors. 125 * MIPS_SR_TLB_SHUTDOWN TLB disabled. 126 * 127 * MIPS_SR_INT_IE Master (current) interrupt enable bit. 128 * 129 * Differences: 130 * r3k has cache control is via frobbing SR register bits, whereas the 131 * r4k cache control is via explicit instructions. 132 * r3k has a 3-entry stack of kernel/user bits, whereas the 133 * r4k has kernel/supervisor/user. 134 */ 135 #define MIPS_SR_COP_USABILITY 0xf0000000 136 #define MIPS_SR_COP_0_BIT 0x10000000 137 #define MIPS_SR_COP_1_BIT 0x20000000 138 139 /* r4k and r3k differences, see below */ 140 141 #define MIPS_SR_BOOT_EXC_VEC 0x00400000 142 #define MIPS_SR_TLB_SHUTDOWN 0x00200000 143 144 /* r4k and r3k differences, see below */ 145 146 #define MIPS_SR_INT_IE 0x00000001 147 /*#define MIPS_SR_MBZ 0x0f8000c0*/ /* Never used, true for r3k */ 148 /*#define MIPS_SR_INT_MASK 0x0000ff00*/ 149 150 151 /* 152 * The R2000/R3000-specific status register bit definitions. 153 * all bits are active when set to 1. 154 * 155 * MIPS_SR_PARITY_ERR Parity error. 156 * MIPS_SR_CACHE_MISS Most recent D-cache load resulted in a miss. 157 * MIPS_SR_PARITY_ZERO Zero replaces outgoing parity bits. 158 * MIPS_SR_SWAP_CACHES Swap I-cache and D-cache. 159 * MIPS_SR_ISOL_CACHES Isolate D-cache from main memory. 160 * Interrupt enable bits defined below. 161 * MIPS_SR_KU_OLD Old kernel/user mode bit. 1 => user mode. 162 * MIPS_SR_INT_ENA_OLD Old interrupt enable bit. 163 * MIPS_SR_KU_PREV Previous kernel/user mode bit. 1 => user mode. 164 * MIPS_SR_INT_ENA_PREV Previous interrupt enable bit. 165 * MIPS_SR_KU_CUR Current kernel/user mode bit. 1 => user mode. 166 */ 167 168 #define MIPS1_PARITY_ERR 0x00100000 169 #define MIPS1_CACHE_MISS 0x00080000 170 #define MIPS1_PARITY_ZERO 0x00040000 171 #define MIPS1_SWAP_CACHES 0x00020000 172 #define MIPS1_ISOL_CACHES 0x00010000 173 174 #define MIPS1_SR_KU_OLD 0x00000020 /* 2nd stacked KU/IE*/ 175 #define MIPS1_SR_INT_ENA_OLD 0x00000010 /* 2nd stacked KU/IE*/ 176 #define MIPS1_SR_KU_PREV 0x00000008 /* 1st stacked KU/IE*/ 177 #define MIPS1_SR_INT_ENA_PREV 0x00000004 /* 1st stacked KU/IE*/ 178 #define MIPS1_SR_KU_CUR 0x00000002 /* current KU */ 179 180 /* backwards compatibility */ 181 #define MIPS_SR_PARITY_ERR MIPS1_PARITY_ERR 182 #define MIPS_SR_CACHE_MISS MIPS1_CACHE_MISS 183 #define MIPS_SR_PARITY_ZERO MIPS1_PARITY_ZERO 184 #define MIPS_SR_SWAP_CACHES MIPS1_SWAP_CACHES 185 #define MIPS_SR_ISOL_CACHES MIPS1_ISOL_CACHES 186 187 #define MIPS_SR_KU_OLD MIPS1_SR_KU_OLD 188 #define MIPS_SR_INT_ENA_OLD MIPS1_SR_INT_ENA_OLD 189 #define MIPS_SR_KU_PREV MIPS1_SR_KU_PREV 190 #define MIPS_SR_KU_CUR MIPS1_SR_KU_CUR 191 #define MIPS_SR_INT_ENA_PREV MIPS1_SR_INT_ENA_PREV 192 193 /* 194 * R4000 status register bit definitons, 195 * where different from r2000/r3000. 196 */ 197 #define MIPS3_SR_XX 0x80000000 198 #define MIPS3_SR_RP 0x08000000 199 #define MIPS3_SR_FR_32 0x04000000 200 #define MIPS3_SR_RE 0x02000000 201 202 #define MIPS3_SR_DIAG_DL 0x01000000 /* QED 52xx */ 203 #define MIPS3_SR_DIAG_IL 0x00800000 /* QED 52xx */ 204 #define MIPS3_SR_DIAG_BEV 0x00400000 205 #define MIPS3_SR_SOFT_RESET 0x00100000 206 #define MIPS3_SR_DIAG_CH 0x00040000 207 #define MIPS3_SR_DIAG_CE 0x00020000 208 #define MIPS3_SR_DIAG_PE 0x00010000 209 #define MIPS3_SR_KX 0x00000080 210 #define MIPS3_SR_SX 0x00000040 211 #define MIPS3_SR_UX 0x00000020 212 #define MIPS3_SR_KSU_MASK 0x00000018 213 #define MIPS3_SR_KSU_USER 0x00000010 214 #define MIPS3_SR_KSU_SUPER 0x00000008 215 #define MIPS3_SR_KSU_KERNEL 0x00000000 216 #define MIPS3_SR_ERL 0x00000004 217 #define MIPS3_SR_EXL 0x00000002 218 219 #define MIPS_SR_SOFT_RESET MIPS3_SR_SOFT_RESET 220 #define MIPS_SR_DIAG_CH MIPS3_SR_DIAG_CH 221 #define MIPS_SR_DIAG_CE MIPS3_SR_DIAG_CE 222 #define MIPS_SR_DIAG_PE MIPS3_SR_DIAG_PE 223 #define MIPS_SR_KX MIPS3_SR_KX 224 #define MIPS_SR_SX MIPS3_SR_SX 225 #define MIPS_SR_UX MIPS3_SR_UX 226 227 #define MIPS_SR_KSU_MASK MIPS3_SR_KSU_MASK 228 #define MIPS_SR_KSU_USER MIPS3_SR_KSU_USER 229 #define MIPS_SR_KSU_SUPER MIPS3_SR_KSU_SUPER 230 #define MIPS_SR_KSU_KERNEL MIPS3_SR_KSU_KERNEL 231 #define MIPS_SR_ERL MIPS3_SR_ERL 232 #define MIPS_SR_EXL MIPS3_SR_EXL 233 234 235 /* 236 * The interrupt masks. 237 * If a bit in the mask is 1 then the interrupt is enabled (or pending). 238 */ 239 #define MIPS_INT_MASK 0xff00 240 #define MIPS_INT_MASK_5 0x8000 241 #define MIPS_INT_MASK_4 0x4000 242 #define MIPS_INT_MASK_3 0x2000 243 #define MIPS_INT_MASK_2 0x1000 244 #define MIPS_INT_MASK_1 0x0800 245 #define MIPS_INT_MASK_0 0x0400 246 #define MIPS_HARD_INT_MASK 0xfc00 247 #define MIPS_SOFT_INT_MASK_1 0x0200 248 #define MIPS_SOFT_INT_MASK_0 0x0100 249 250 /* 251 * mips3 CPUs have on-chip timer at INT_MASK_5. Each platform can 252 * choose to enable this interrupt. 253 */ 254 #if defined(MIPS3_ENABLE_CLOCK_INTR) 255 #define MIPS3_INT_MASK MIPS_INT_MASK 256 #define MIPS3_HARD_INT_MASK MIPS_HARD_INT_MASK 257 #else 258 #define MIPS3_INT_MASK (MIPS_INT_MASK & ~MIPS_INT_MASK_5) 259 #define MIPS3_HARD_INT_MASK (MIPS_HARD_INT_MASK & ~MIPS_INT_MASK_5) 260 #endif 261 262 /* 263 * The bits in the context register. 264 */ 265 #define MIPS1_CNTXT_PTE_BASE 0xFFE00000 266 #define MIPS1_CNTXT_BAD_VPN 0x001FFFFC 267 268 #define MIPS3_CNTXT_PTE_BASE 0xFF800000 269 #define MIPS3_CNTXT_BAD_VPN2 0x007FFFF0 270 271 /* 272 * The bits in the MIPS3 config register. 273 * 274 * bit 0..5: R/W, Bit 6..31: R/O 275 */ 276 277 /* kseg0 coherency algorithm - see MIPS3_TLB_ATTR values */ 278 #define MIPS3_CONFIG_K0_MASK 0x00000007 279 280 /* 281 * R/W Update on Store Conditional 282 * 0: Store Conditional uses coherency algorithm specified by TLB 283 * 1: Store Conditional uses cacheable coherent update on write 284 */ 285 #define MIPS3_CONFIG_CU 0x00000008 286 287 #define MIPS3_CONFIG_DB 0x00000010 /* Primary D-cache line size */ 288 #define MIPS3_CONFIG_IB 0x00000020 /* Primary I-cache line size */ 289 #define MIPS3_CONFIG_CACHE_L1_LSIZE(config, bit) \ 290 (((config) & (bit)) ? 32 : 16) 291 292 #define MIPS3_CONFIG_DC_MASK 0x000001c0 /* Primary D-cache size */ 293 #define MIPS3_CONFIG_DC_SHIFT 6 294 #define MIPS3_CONFIG_IC_MASK 0x00000e00 /* Primary I-cache size */ 295 #define MIPS3_CONFIG_IC_SHIFT 9 296 #define MIPS3_CONFIG_C_DEFBASE 0x1000 /* default base 2^12 */ 297 #ifdef MIPS3_4100 /* VR4100 core */ 298 /* XXXCDC: THIS MIPS3_4100 SPECIAL CASE SHOULD GO AWAY */ 299 #define MIPS3_CONFIG_CS 0x00001000 /* cache size mode indication*/ 300 #define MIPS3_CONFIG_CACHE_SIZE(config, mask, dummy, shift) \ 301 ((((config)&MIPS3_CONFIG_CS)?0x400:0x1000) << (((config) & (mask)) >> (shift))) 302 #else 303 #define MIPS3_CONFIG_CACHE_SIZE(config, mask, base, shift) \ 304 ((base) << (((config) & (mask)) >> (shift))) 305 #endif 306 307 /* Block ordering: 0: sequential, 1: sub-block */ 308 #define MIPS3_CONFIG_EB 0x00002000 309 310 /* ECC mode - 0: ECC mode, 1: parity mode */ 311 #define MIPS3_CONFIG_EM 0x00004000 312 313 /* BigEndianMem - 0: kernel and memory are little endian, 1: big endian */ 314 #define MIPS3_CONFIG_BE 0x00008000 315 316 /* Dirty Shared coherency state - 0: enabled, 1: disabled */ 317 #define MIPS3_CONFIG_SM 0x00010000 318 319 /* Secondary Cache - 0: present, 1: not present */ 320 #define MIPS3_CONFIG_SC 0x00020000 321 322 /* System Port width - 0: 64-bit, 1: 32-bit (QED RM523x), 2,3: reserved */ 323 #define MIPS3_CONFIG_EW_MASK 0x000c0000 324 #define MIPS3_CONFIG_EW_SHIFT 18 325 326 /* Secondary Cache port width - 0: 128-bit data path to S-cache, 1: reserved */ 327 #define MIPS3_CONFIG_SW 0x00100000 328 329 /* Split Secondary Cache Mode - 0: I/D mixed, 1: I/D separated by SCAddr(17) */ 330 #define MIPS3_CONFIG_SS 0x00200000 331 332 /* Secondary Cache line size */ 333 #define MIPS3_CONFIG_SB_MASK 0x00c00000 334 #define MIPS3_CONFIG_SB_SHIFT 22 335 #define MIPS3_CONFIG_CACHE_L2_LSIZE(config) \ 336 (0x10 << (((config) & MIPS3_CONFIG_SB_MASK) >> MIPS3_CONFIG_SB_SHIFT)) 337 338 /* Write back data rate */ 339 #define MIPS3_CONFIG_EP_MASK 0x0f000000 340 #define MIPS3_CONFIG_EP_SHIFT 24 341 342 /* System clock ratio - this value is CPU dependent */ 343 #define MIPS3_CONFIG_EC_MASK 0x70000000 344 #define MIPS3_CONFIG_EC_SHIFT 28 345 346 /* Master-Checker Mode - 1: enabled */ 347 #define MIPS3_CONFIG_CM 0x80000000 348 349 /* 350 * Location of exception vectors. 351 * 352 * Common vectors: reset and UTLB miss. 353 */ 354 #define MIPS_RESET_EXC_VEC 0xBFC00000 355 #define MIPS_UTLB_MISS_EXC_VEC 0x80000000 356 357 /* 358 * R3000 general exception vector (everything else) 359 */ 360 #define MIPS1_GEN_EXC_VEC 0x80000080 361 362 /* 363 * R4000 MIPS-III exception vectors 364 */ 365 #define MIPS3_XTLB_MISS_EXC_VEC 0x80000080 366 #define MIPS3_CACHE_ERR_EXC_VEC 0x80000100 367 #define MIPS3_GEN_EXC_VEC 0x80000180 368 369 /* 370 * Coprocessor 0 registers: 371 * 372 * v--- width for mips I,III,32,64 373 * (3=32bit, 6=64bit, i=impl dep) 374 * 0 MIPS_COP_0_TLB_INDEX 3333 TLB Index. 375 * 1 MIPS_COP_0_TLB_RANDOM 3333 TLB Random. 376 * 2 MIPS_COP_0_TLB_LOW 3... r3k TLB entry low. 377 * 2 MIPS_COP_0_TLB_LO0 .636 r4k TLB entry low. 378 * 3 MIPS_COP_0_TLB_LO1 .636 r4k TLB entry low, extended. 379 * 4 MIPS_COP_0_TLB_CONTEXT 3636 TLB Context. 380 * 5 MIPS_COP_0_TLB_PG_MASK .333 TLB Page Mask register. 381 * 6 MIPS_COP_0_TLB_WIRED .333 Wired TLB number. 382 * 8 MIPS_COP_0_BAD_VADDR 3636 Bad virtual address. 383 * 9 MIPS_COP_0_COUNT .333 Count register. 384 * 10 MIPS_COP_0_TLB_HI 3636 TLB entry high. 385 * 11 MIPS_COP_0_COMPARE .333 Compare (against Count). 386 * 12 MIPS_COP_0_STATUS 3333 Status register. 387 * 13 MIPS_COP_0_CAUSE 3333 Exception cause register. 388 * 14 MIPS_COP_0_EXC_PC 3636 Exception PC. 389 * 15 MIPS_COP_0_PRID 3333 Processor revision identifier. 390 * 16 MIPS_COP_0_CONFIG 3333 Configuration register. 391 * 16/1 MIPS_COP_0_CONFIG1 ..33 Configuration register 1. 392 * 16/2 MIPS_COP_0_CONFIG2 ..33 Configuration register 2. 393 * 16/3 MIPS_COP_0_CONFIG3 ..33 Configuration register 3. 394 * 17 MIPS_COP_0_LLADDR .336 Load Linked Address. 395 * 18 MIPS_COP_0_WATCH_LO .336 WatchLo register. 396 * 19 MIPS_COP_0_WATCH_HI .333 WatchHi register. 397 * 20 MIPS_COP_0_TLB_XCONTEXT .6.6 TLB XContext register. 398 * 23 MIPS_COP_0_DEBUG .... Debug JTAG register. 399 * 24 MIPS_COP_0_DEPC .... DEPC JTAG register. 400 * 25 MIPS_COP_0_PERFCNT ..36 Performance Counter register. 401 * 26 MIPS_COP_0_ECC .3ii ECC / Error Control register. 402 * 27 MIPS_COP_0_CACHE_ERR .3ii Cache Error register. 403 * 28/0 MIPS_COP_0_TAG_LO .3ii Cache TagLo register (instr). 404 * 28/1 MIPS_COP_0_DATA_LO ..ii Cache DataLo register (instr). 405 * 28/2 MIPS_COP_0_TAG_LO ..ii Cache TagLo register (data). 406 * 28/3 MIPS_COP_0_DATA_LO ..ii Cache DataLo register (data). 407 * 29/0 MIPS_COP_0_TAG_HI .3ii Cache TagHi register (instr). 408 * 29/1 MIPS_COP_0_DATA_HI ..ii Cache DataHi register (instr). 409 * 29/2 MIPS_COP_0_TAG_HI ..ii Cache TagHi register (data). 410 * 29/3 MIPS_COP_0_DATA_HI ..ii Cache DataHi register (data). 411 * 30 MIPS_COP_0_ERROR_PC .636 Error EPC register. 412 * 31 MIPS_COP_0_DESAVE .... DESAVE JTAG register. 413 */ 414 #define MIPS_COP_0_TLB_INDEX $0 415 #define MIPS_COP_0_TLB_RANDOM $1 416 /* Name and meaning of TLB bits for $2 differ on r3k and r4k. */ 417 418 #define MIPS_COP_0_TLB_CONTEXT $4 419 /* $5 and $6 new with MIPS-III */ 420 #define MIPS_COP_0_BAD_VADDR $8 421 #define MIPS_COP_0_TLB_HI $10 422 #define MIPS_COP_0_STATUS_REG $12 423 #define MIPS_COP_0_CAUSE_REG $13 424 #define MIPS_COP_0_STATUS $12 425 #define MIPS_COP_0_CAUSE $13 426 #define MIPS_COP_0_EXC_PC $14 427 #define MIPS_COP_0_PRID $15 428 429 430 /* MIPS-I */ 431 #define MIPS_COP_0_TLB_LOW $2 432 433 /* MIPS-III */ 434 #define MIPS_COP_0_TLB_LO0 $2 435 #define MIPS_COP_0_TLB_LO1 $3 436 437 #define MIPS_COP_0_TLB_PG_MASK $5 438 #define MIPS_COP_0_TLB_WIRED $6 439 440 #define MIPS_COP_0_COUNT $9 441 #define MIPS_COP_0_COMPARE $11 442 443 #define MIPS_COP_0_CONFIG $16 444 #define MIPS_COP_0_LLADDR $17 445 #define MIPS_COP_0_WATCH_LO $18 446 #define MIPS_COP_0_WATCH_HI $19 447 #define MIPS_COP_0_TLB_XCONTEXT $20 448 #define MIPS_COP_0_ECC $26 449 #define MIPS_COP_0_CACHE_ERR $27 450 #define MIPS_COP_0_TAG_LO $28 451 #define MIPS_COP_0_TAG_HI $29 452 #define MIPS_COP_0_ERROR_PC $30 453 454 /* MIPS32/64 */ 455 #define MIPS_COP_0_DEBUG $23 456 #define MIPS_COP_0_DEPC $24 457 #define MIPS_COP_0_PERFCNT $25 458 #define MIPS_COP_0_DATA_LO $28 459 #define MIPS_COP_0_DATA_HI $29 460 #define MIPS_COP_0_DESAVE $31 461 462 /* 463 * Values for the code field in a break instruction. 464 */ 465 #define MIPS_BREAK_INSTR 0x0000000d 466 #define MIPS_BREAK_VAL_MASK 0x03ff0000 467 #define MIPS_BREAK_VAL_SHIFT 16 468 #define MIPS_BREAK_KDB_VAL 512 469 #define MIPS_BREAK_SSTEP_VAL 513 470 #define MIPS_BREAK_BRKPT_VAL 514 471 #define MIPS_BREAK_SOVER_VAL 515 472 #define MIPS_BREAK_KDB (MIPS_BREAK_INSTR | \ 473 (MIPS_BREAK_KDB_VAL << MIPS_BREAK_VAL_SHIFT)) 474 #define MIPS_BREAK_SSTEP (MIPS_BREAK_INSTR | \ 475 (MIPS_BREAK_SSTEP_VAL << MIPS_BREAK_VAL_SHIFT)) 476 #define MIPS_BREAK_BRKPT (MIPS_BREAK_INSTR | \ 477 (MIPS_BREAK_BRKPT_VAL << MIPS_BREAK_VAL_SHIFT)) 478 #define MIPS_BREAK_SOVER (MIPS_BREAK_INSTR | \ 479 (MIPS_BREAK_SOVER_VAL << MIPS_BREAK_VAL_SHIFT)) 480 481 /* 482 * Mininum and maximum cache sizes. 483 */ 484 #define MIPS_MIN_CACHE_SIZE (16 * 1024) 485 #define MIPS_MAX_CACHE_SIZE (256 * 1024) 486 #define MIPS3_MAX_PCACHE_SIZE (32 * 1024) /* max. primary cache size */ 487 488 /* 489 * The floating point version and status registers. 490 */ 491 #define MIPS_FPU_ID $0 492 #define MIPS_FPU_CSR $31 493 494 /* 495 * The floating point coprocessor status register bits. 496 */ 497 #define MIPS_FPU_ROUNDING_BITS 0x00000003 498 #define MIPS_FPU_ROUND_RN 0x00000000 499 #define MIPS_FPU_ROUND_RZ 0x00000001 500 #define MIPS_FPU_ROUND_RP 0x00000002 501 #define MIPS_FPU_ROUND_RM 0x00000003 502 #define MIPS_FPU_STICKY_BITS 0x0000007c 503 #define MIPS_FPU_STICKY_INEXACT 0x00000004 504 #define MIPS_FPU_STICKY_UNDERFLOW 0x00000008 505 #define MIPS_FPU_STICKY_OVERFLOW 0x00000010 506 #define MIPS_FPU_STICKY_DIV0 0x00000020 507 #define MIPS_FPU_STICKY_INVALID 0x00000040 508 #define MIPS_FPU_ENABLE_BITS 0x00000f80 509 #define MIPS_FPU_ENABLE_INEXACT 0x00000080 510 #define MIPS_FPU_ENABLE_UNDERFLOW 0x00000100 511 #define MIPS_FPU_ENABLE_OVERFLOW 0x00000200 512 #define MIPS_FPU_ENABLE_DIV0 0x00000400 513 #define MIPS_FPU_ENABLE_INVALID 0x00000800 514 #define MIPS_FPU_EXCEPTION_BITS 0x0003f000 515 #define MIPS_FPU_EXCEPTION_INEXACT 0x00001000 516 #define MIPS_FPU_EXCEPTION_UNDERFLOW 0x00002000 517 #define MIPS_FPU_EXCEPTION_OVERFLOW 0x00004000 518 #define MIPS_FPU_EXCEPTION_DIV0 0x00008000 519 #define MIPS_FPU_EXCEPTION_INVALID 0x00010000 520 #define MIPS_FPU_EXCEPTION_UNIMPL 0x00020000 521 #define MIPS_FPU_COND_BIT 0x00800000 522 #define MIPS_FPU_FLUSH_BIT 0x01000000 /* r4k, MBZ on r3k */ 523 #define MIPS1_FPC_MBZ_BITS 0xff7c0000 524 #define MIPS3_FPC_MBZ_BITS 0xfe7c0000 525 526 527 /* 528 * Constants to determine if have a floating point instruction. 529 */ 530 #define MIPS_OPCODE_SHIFT 26 531 #define MIPS_OPCODE_C1 0x11 532 #define MIPS_OPCODE_LWC1 0x31 533 #define MIPS_OPCODE_LDC1 0x35 534 #define MIPS_OPCODE_SWC1 0x39 535 #define MIPS_OPCODE_SDC1 0x3d 536 537 538 /* 539 * The low part of the TLB entry. 540 */ 541 #define MIPS1_TLB_PFN 0xfffff000 542 #define MIPS1_TLB_NON_CACHEABLE_BIT 0x00000800 543 #define MIPS1_TLB_DIRTY_BIT 0x00000400 544 #define MIPS1_TLB_VALID_BIT 0x00000200 545 #define MIPS1_TLB_GLOBAL_BIT 0x00000100 546 547 #define MIPS3_TLB_PFN 0x3fffffc0 548 #define MIPS3_TLB_ATTR_MASK 0x00000038 549 #define MIPS3_TLB_ATTR_SHIFT 3 550 #define MIPS3_TLB_DIRTY_BIT 0x00000004 551 #define MIPS3_TLB_VALID_BIT 0x00000002 552 #define MIPS3_TLB_GLOBAL_BIT 0x00000001 553 554 /* XXX XXX XXX */ 555 #define MIPS1_TLB_PHYS_PAGE_SHIFT 12 556 #define MIPS3_TLB_PHYS_PAGE_SHIFT 6 557 #define MIPS1_TLB_PF_NUM MIPS1_TLB_PFN 558 #define MIPS3_TLB_PF_NUM MIPS3_TLB_PFN 559 #define MIPS1_TLB_MOD_BIT MIPS1_TLB_DIRTY_BIT 560 #define MIPS3_TLB_MOD_BIT MIPS3_TLB_DIRTY_BIT 561 /* XXX XXX XXX */ 562 563 /* 564 * MIPS3_TLB_ATTR values - coherency algorithm: 565 * 0: cacheable, noncoherent, write-through, no write allocate 566 * 1: cacheable, noncoherent, write-through, write allocate 567 * 2: uncached 568 * 3: cacheable, noncoherent, write-back (noncoherent) 569 * 4: cacheable, coherent, write-back, exclusive (exclusive) 570 * 5: cacheable, coherent, write-back, exclusive on write (sharable) 571 * 6: cacheable, coherent, write-back, update on write (update) 572 * 7: uncached, accelerated (gather STORE operations) 573 */ 574 #define MIPS3_TLB_ATTR_WT 0 /* IDT */ 575 #define MIPS3_TLB_ATTR_WT_WRITEALLOCATE 1 /* IDT */ 576 #define MIPS3_TLB_ATTR_UNCACHED 2 /* R4000/R4400, IDT */ 577 #define MIPS3_TLB_ATTR_WB_NONCOHERENT 3 /* R4000/R4400, IDT */ 578 #define MIPS3_TLB_ATTR_WB_EXCLUSIVE 4 /* R4000/R4400 */ 579 #define MIPS3_TLB_ATTR_WB_SHARABLE 5 /* R4000/R4400 */ 580 #define MIPS3_TLB_ATTR_WB_UPDATE 6 /* R4000/R4400 */ 581 #define MIPS4_TLB_ATTR_UNCACHED_ACCELERATED 7 /* R10000 */ 582 583 584 /* 585 * The high part of the TLB entry. 586 */ 587 #define MIPS1_TLB_VPN 0xfffff000 588 #define MIPS1_TLB_PID 0x00000fc0 589 #define MIPS1_TLB_PID_SHIFT 6 590 591 #define MIPS3_TLB_VPN2 0xffffe000 592 #define MIPS3_TLB_ASID 0x000000ff 593 594 /* XXX XXX XXX */ 595 #define MIPS1_TLB_VIRT_PAGE_NUM MIPS1_TLB_VPN 596 #define MIPS3_TLB_VIRT_PAGE_NUM MIPS3_TLB_VPN2 597 #define MIPS3_TLB_PID MIPS3_TLB_ASID 598 #define MIPS_TLB_VIRT_PAGE_SHIFT 12 599 /* XXX XXX XXX */ 600 601 /* 602 * r3000: shift count to put the index in the right spot. 603 */ 604 #define MIPS1_TLB_INDEX_SHIFT 8 605 606 /* 607 * The number of TLB entries and the first one that write random hits. 608 */ 609 #define MIPS1_TLB_NUM_TLB_ENTRIES 64 610 #define MIPS1_TLB_FIRST_RAND_ENTRY 8 611 612 #define MIPS3_TLB_NUM_TLB_ENTRIES 48 613 #define MIPS_R4300_TLB_NUM_TLB_ENTRIES 32 614 #define MIPS3_TLB_WIRED_UPAGES 1 615 616 617 /* 618 * The number of process id entries. 619 */ 620 #define MIPS1_TLB_NUM_PIDS 64 621 #define MIPS3_TLB_NUM_ASIDS 256 622 623 /* 624 * Patch codes to hide CPU design differences between MIPS1 and MIPS3. 625 */ 626 627 #if !defined(MIPS3) && defined(MIPS1) 628 #define MIPS_TLB_PID_SHIFT MIPS1_TLB_PID_SHIFT 629 #define MIPS_TLB_NUM_PIDS MIPS1_TLB_NUM_PIDS 630 #endif 631 632 #if defined(MIPS3) && !defined(MIPS1) 633 #define MIPS_TLB_PID_SHIFT 0 634 #define MIPS_TLB_NUM_PIDS MIPS3_TLB_NUM_ASIDS 635 #endif 636 637 638 #if defined(MIPS1) && defined(MIPS3) 639 #define MIPS_TLB_PID_SHIFT \ 640 ((CPUISMIPS3)? 0 : MIPS1_TLB_PID_SHIFT) 641 642 #define MIPS_TLB_NUM_PIDS \ 643 ((CPUISMIPS3)? MIPS3_TLB_NUM_ASIDS : MIPS1_TLB_NUM_PIDS) 644 645 #endif 646 647 /* 648 * CPU processor revision IDs for company ID == 0 (non mips32/64 chips) 649 */ 650 #define MIPS_R2000 0x01 /* MIPS R2000 ISA I */ 651 #define MIPS_R3000 0x02 /* MIPS R3000 ISA I */ 652 #define MIPS_R6000 0x03 /* MIPS R6000 ISA II */ 653 #define MIPS_R4000 0x04 /* MIPS R4000/R4400 ISA III */ 654 #define MIPS_R3LSI 0x05 /* LSI Logic R3000 derivative ISA I */ 655 #define MIPS_R6000A 0x06 /* MIPS R6000A ISA II */ 656 #define MIPS_R3IDT 0x07 /* IDT R3041 or RC36100 ISA I */ 657 #define MIPS_R10000 0x09 /* MIPS R10000 ISA IV */ 658 #define MIPS_R4200 0x0a /* NEC VR4200 ISA III */ 659 #define MIPS_R4300 0x0b /* NEC VR4300 ISA III */ 660 #define MIPS_R4100 0x0c /* NEC VR4100 ISA III */ 661 #define MIPS_R12000 0x0e /* MIPS R12000 ISA IV */ 662 #define MIPS_R14000 0x0f /* MIPS R14000 ISA IV */ 663 #define MIPS_R8000 0x10 /* MIPS R8000 Blackbird/TFP ISA IV */ 664 #define MIPS_RC32300 0x18 /* IDT RC32334,332,355 ISA 32 */ 665 #define MIPS_R4600 0x20 /* QED R4600 Orion ISA III */ 666 #define MIPS_R4700 0x21 /* QED R4700 Orion ISA III */ 667 #define MIPS_R3SONY 0x21 /* Sony R3000 based ISA I */ 668 #define MIPS_R4650 0x22 /* QED R4650 ISA III */ 669 #define MIPS_TX3900 0x22 /* Toshiba TX39 family ISA I */ 670 #define MIPS_R5000 0x23 /* MIPS R5000 ISA IV */ 671 #define MIPS_R3NKK 0x23 /* NKK R3000 based ISA I */ 672 #define MIPS_RC32364 0x26 /* IDT RC32364 ISA 32 */ 673 #define MIPS_RM7000 0x27 /* QED RM7000 ISA IV */ 674 #define MIPS_RM5200 0x28 /* QED RM5200s ISA IV */ 675 #define MIPS_TX4900 0x2d /* Toshiba TX49 family ISA III */ 676 #define MIPS_R5900 0x2e /* Toshiba R5900 (EECore) ISA --- */ 677 #define MIPS_RC64470 0x30 /* IDT RC64474/RC64475 ISA III */ 678 #define MIPS_R5400 0x54 /* NEC VR5400 ISA IV */ 679 680 /* 681 * CPU processor revision IDs for company ID == 1 (MIPS) 682 */ 683 #define MIPS_4Kc 0x80 /* MIPS 4Kc ISA 32 */ 684 #define MIPS_5Kc 0x81 /* MIPS 5Kc ISA 64 */ 685 #define MIPS_4KEc 0x84 /* MIPS 4KEc ISA 32 */ 686 #define MIPS_4KSc 0x86 /* MIPS 4KSc ISA 32 */ 687 688 /* 689 * CPU processor revision IDs for company ID == 3 (Alchemy) 690 */ 691 #define MIPS_AU1000 0x01 /* Alchemy Au1000 ISA 32 */ 692 693 /* 694 * CPU processor revision IDs for company ID == 4 (SiByte) 695 */ 696 #define MIPS_SB1 0x01 /* SiByte SB1 ISA 64 */ 697 698 /* 699 * FPU processor revision ID 700 */ 701 #define MIPS_SOFT 0x00 /* Software emulation ISA I */ 702 #define MIPS_R2360 0x01 /* MIPS R2360 FPC ISA I */ 703 #define MIPS_R2010 0x02 /* MIPS R2010 FPC ISA I */ 704 #define MIPS_R3010 0x03 /* MIPS R3010 FPC ISA I */ 705 #define MIPS_R6010 0x04 /* MIPS R6010 FPC ISA II */ 706 #define MIPS_R4010 0x05 /* MIPS R4010 FPC ISA II */ 707 #define MIPS_R31LSI 0x06 /* LSI Logic derivate ISA I */ 708 #define MIPS_R3TOSH 0x22 /* Toshiba R3000 based FPU ISA I */ 709 710 #ifdef ENABLE_MIPS_TX3900 711 #include <mips/r3900regs.h> 712 #endif 713 #ifdef MIPS3_5900 714 #include <mips/r5900/cpuregs.h> 715 #endif 716 717 #endif /* _MIPS_CPUREGS_H_ */ 718
Indexes created Thu Oct 30 16:09:53 GMT 2025