cpuregs.h revision 1.74.28.16
1 /* $NetBSD: cpuregs.h,v 1.74.28.16 2010/03/21 18:18:51 cliff Exp $ */ 2 3 /* 4 * Copyright (c) 1992, 1993 5 * The Regents of the University of California. All rights reserved. 6 * 7 * This code is derived from software contributed to Berkeley by 8 * Ralph Campbell and Rick Macklem. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. Neither the name of the University nor the names of its contributors 19 * may be used to endorse or promote products derived from this software 20 * without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 27 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 28 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 29 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 30 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 31 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 32 * SUCH DAMAGE. 33 * 34 * @(#)machConst.h 8.1 (Berkeley) 6/10/93 35 * 36 * machConst.h -- 37 * 38 * Machine dependent constants. 39 * 40 * Copyright (C) 1989 Digital Equipment Corporation. 41 * Permission to use, copy, modify, and distribute this software and 42 * its documentation for any purpose and without fee is hereby granted, 43 * provided that the above copyright notice appears in all copies. 44 * Digital Equipment Corporation makes no representations about the 45 * suitability of this software for any purpose. It is provided "as is" 46 * without express or implied warranty. 47 * 48 * from: Header: /sprite/src/kernel/mach/ds3100.md/RCS/machConst.h, 49 * v 9.2 89/10/21 15:55:22 jhh Exp SPRITE (DECWRL) 50 * from: Header: /sprite/src/kernel/mach/ds3100.md/RCS/machAddrs.h, 51 * v 1.2 89/08/15 18:28:21 rab Exp SPRITE (DECWRL) 52 * from: Header: /sprite/src/kernel/vm/ds3100.md/RCS/vmPmaxConst.h, 53 * v 9.1 89/09/18 17:33:00 shirriff Exp SPRITE (DECWRL) 54 */ 55 56 #ifndef _MIPS_CPUREGS_H_ 57 #define _MIPS_CPUREGS_H_ 58 59 #include <sys/cdefs.h> /* For __CONCAT() */ 60 61 #if defined(_KERNEL_OPT) 62 #include "opt_cputype.h" 63 #endif 64 65 /* 66 * Address space. 67 * 32-bit mips CPUS partition their 32-bit address space into four segments: 68 * 69 * kuseg 0x00000000 - 0x7fffffff User virtual mem, mapped 70 * kseg0 0x80000000 - 0x9fffffff Physical memory, cached, unmapped 71 * kseg1 0xa0000000 - 0xbfffffff Physical memory, uncached, unmapped 72 * kseg2 0xc0000000 - 0xffffffff kernel-virtual, mapped 73 * 74 * mips1 physical memory is limited to 512Mbytes, which is 75 * doubly mapped in kseg0 (cached) and kseg1 (uncached.) 76 * Caching of mapped addresses is controlled by bits in the TLB entry. 77 */ 78 79 #ifdef _LP64 80 #define MIPS_XUSEG_START (0L << 62) 81 #define MIPS_XUSEG_P(x) (((uint64_t)(x) >> 62) == 0) 82 #define MIPS_USEG_P(x) ((uintptr_t)(x) < 0x80000000L) 83 #define MIPS_XSSEG_START (1L << 62) 84 #define MIPS_XSSEG_P(x) (((uint64_t)(x) >> 62) == 1) 85 #endif 86 87 /* 88 * MIPS addresses are signed and we defining as negative so that 89 * in LP64 kern they get sign-extended correctly. 90 */ 91 #ifndef _LOCORE 92 #define MIPS_KSEG0_START (-0x7fffffffL-1) /* 0x80000000 */ 93 #define MIPS_KSEG1_START -0x60000000L /* 0xa0000000 */ 94 #define MIPS_KSEG2_START -0x40000000L /* 0xc0000000 */ 95 #define MIPS_MAX_MEM_ADDR -0x42000000L /* 0xbe000000 */ 96 #define MIPS_RESERVED_ADDR -0x40380000L /* 0xbfc80000 */ 97 #endif 98 99 #define MIPS_PHYS_MASK 0x1fffffff 100 101 #define MIPS_KSEG0_TO_PHYS(x) ((uintptr_t)(x) & MIPS_PHYS_MASK) 102 #define MIPS_PHYS_TO_KSEG0(x) ((uintptr_t)(x) | (intptr_t)MIPS_KSEG0_START) 103 #define MIPS_KSEG1_TO_PHYS(x) ((uintptr_t)(x) & MIPS_PHYS_MASK) 104 #define MIPS_PHYS_TO_KSEG1(x) ((uintptr_t)(x) | (intptr_t)MIPS_KSEG1_START) 105 106 #define MIPS_KSEG0_P(x) (((intptr_t)(x) & ~MIPS_PHYS_MASK) == MIPS_KSEG0_START) 107 #define MIPS_KSEG1_P(x) (((intptr_t)(x) & ~MIPS_PHYS_MASK) == MIPS_KSEG1_START) 108 #define MIPS_KSEG2_P(x) ((uintptr_t)MIPS_KSEG2_START <= (uintptr_t)(x)) 109 110 /* Map virtual address to index in mips3 r4k virtually-indexed cache */ 111 #define MIPS3_VA_TO_CINDEX(x) \ 112 (((intptr_t)(x) & 0xffffff) | MIPS_KSEG0_START) 113 114 #ifndef _LOCORE 115 #define MIPS_XSEG_MASK (0x3fffffffffffffffLL) 116 #define MIPS_XKSEG_START (0x3ULL << 62) 117 #define MIPS_XKSEG_P(x) (((uint64_t)(x) >> 62) == 3) 118 119 #define MIPS_XKPHYS_START (0x2ULL << 62) 120 #define MIPS_PHYS_TO_XKPHYS_UNCACHED(x) \ 121 (MIPS_XKPHYS_START | ((uint64_t)(CCA_UNCACHED) << 59) | (x)) 122 #define MIPS_PHYS_TO_XKPHYS_CACHED(x) \ 123 (mips_options.mips3_xkphys_cached | (x)) 124 #define MIPS_PHYS_TO_XKPHYS(cca,x) \ 125 (MIPS_XKPHYS_START | ((uint64_t)(cca) << 59) | (x)) 126 #define MIPS_XKPHYS_TO_PHYS(x) ((uint64_t)(x) & 0x07ffffffffffffffLL) 127 #define MIPS_XKPHYS_TO_CCA(x) (((uint64_t)(x) >> 59) & 7) 128 #define MIPS_XKPHYS_P(x) (((uint64_t)(x) >> 62) == 2) 129 #endif /* _LOCORE */ 130 131 #define CCA_UNCACHED 2 132 #define CCA_CACHEABLE 3 /* cacheable non-coherent */ 133 134 /* CPU dependent mtc0 hazard hook */ 135 #define COP0_SYNC /* nothing */ 136 #define COP0_HAZARD_FPUENABLE nop; nop; nop; nop; 137 138 /* 139 * The bits in the cause register. 140 * 141 * Bits common to r3000 and r4000: 142 * 143 * MIPS_CR_BR_DELAY Exception happened in branch delay slot. 144 * MIPS_CR_COP_ERR Coprocessor error. 145 * MIPS_CR_IP Interrupt pending bits defined below. 146 * (same meaning as in CAUSE register). 147 * MIPS_CR_EXC_CODE The exception type (see exception codes below). 148 * 149 * Differences: 150 * r3k has 4 bits of execption type, r4k has 5 bits. 151 */ 152 #define MIPS_CR_BR_DELAY 0x80000000 153 #define MIPS_CR_COP_ERR 0x30000000 154 #define MIPS1_CR_EXC_CODE 0x0000003C /* four bits */ 155 #define MIPS3_CR_EXC_CODE 0x0000007C /* five bits */ 156 #define MIPS_CR_IP 0x0000FF00 157 #define MIPS_CR_EXC_CODE_SHIFT 2 158 159 /* 160 * The bits in the status register. All bits are active when set to 1. 161 * 162 * R3000 status register fields: 163 * MIPS_SR_COP_USABILITY Control the usability of the four coprocessors. 164 * MIPS_SR_TS TLB shutdown. 165 * 166 * MIPS_SR_INT_IE Master (current) interrupt enable bit. 167 * 168 * Differences: 169 * r3k has cache control is via frobbing SR register bits, whereas the 170 * r4k cache control is via explicit instructions. 171 * r3k has a 3-entry stack of kernel/user bits, whereas the 172 * r4k has kernel/supervisor/user. 173 */ 174 #define MIPS_SR_COP_USABILITY 0xf0000000 175 #define MIPS_SR_COP_0_BIT 0x10000000 176 #define MIPS_SR_COP_1_BIT 0x20000000 177 #define MIPS_SR_COP_2_BIT 0x40000000 178 179 /* r4k and r3k differences, see below */ 180 181 #define MIPS_SR_MX 0x01000000 /* MIPS64 */ 182 #define MIPS_SR_PX 0x00800000 /* MIPS64 */ 183 #define MIPS_SR_BEV 0x00400000 /* Use boot exception vector */ 184 #define MIPS_SR_TS 0x00200000 185 186 /* r4k and r3k differences, see below */ 187 188 #define MIPS_SR_INT_IE 0x00000001 189 /*#define MIPS_SR_MBZ 0x0f8000c0*/ /* Never used, true for r3k */ 190 /*#define MIPS_SR_INT_MASK 0x0000ff00*/ 191 192 193 /* 194 * The R2000/R3000-specific status register bit definitions. 195 * all bits are active when set to 1. 196 * 197 * MIPS_SR_PARITY_ERR Parity error. 198 * MIPS_SR_CACHE_MISS Most recent D-cache load resulted in a miss. 199 * MIPS_SR_PARITY_ZERO Zero replaces outgoing parity bits. 200 * MIPS_SR_SWAP_CACHES Swap I-cache and D-cache. 201 * MIPS_SR_ISOL_CACHES Isolate D-cache from main memory. 202 * Interrupt enable bits defined below. 203 * MIPS_SR_KU_OLD Old kernel/user mode bit. 1 => user mode. 204 * MIPS_SR_INT_ENA_OLD Old interrupt enable bit. 205 * MIPS_SR_KU_PREV Previous kernel/user mode bit. 1 => user mode. 206 * MIPS_SR_INT_ENA_PREV Previous interrupt enable bit. 207 * MIPS_SR_KU_CUR Current kernel/user mode bit. 1 => user mode. 208 */ 209 210 #define MIPS1_PARITY_ERR 0x00100000 211 #define MIPS1_CACHE_MISS 0x00080000 212 #define MIPS1_PARITY_ZERO 0x00040000 213 #define MIPS1_SWAP_CACHES 0x00020000 214 #define MIPS1_ISOL_CACHES 0x00010000 215 216 #define MIPS1_SR_KU_OLD 0x00000020 /* 2nd stacked KU/IE*/ 217 #define MIPS1_SR_INT_ENA_OLD 0x00000010 /* 2nd stacked KU/IE*/ 218 #define MIPS1_SR_KU_PREV 0x00000008 /* 1st stacked KU/IE*/ 219 #define MIPS1_SR_INT_ENA_PREV 0x00000004 /* 1st stacked KU/IE*/ 220 #define MIPS1_SR_KU_CUR 0x00000002 /* current KU */ 221 222 /* backwards compatibility */ 223 #define MIPS_SR_PARITY_ERR MIPS1_PARITY_ERR 224 #define MIPS_SR_CACHE_MISS MIPS1_CACHE_MISS 225 #define MIPS_SR_PARITY_ZERO MIPS1_PARITY_ZERO 226 #define MIPS_SR_SWAP_CACHES MIPS1_SWAP_CACHES 227 #define MIPS_SR_ISOL_CACHES MIPS1_ISOL_CACHES 228 229 #define MIPS_SR_KU_OLD MIPS1_SR_KU_OLD 230 #define MIPS_SR_INT_ENA_OLD MIPS1_SR_INT_ENA_OLD 231 #define MIPS_SR_KU_PREV MIPS1_SR_KU_PREV 232 #define MIPS_SR_KU_CUR MIPS1_SR_KU_CUR 233 #define MIPS_SR_INT_ENA_PREV MIPS1_SR_INT_ENA_PREV 234 235 /* 236 * R4000 status register bit definitons, 237 * where different from r2000/r3000. 238 */ 239 #define MIPS3_SR_XX 0x80000000 240 #define MIPS3_SR_RP 0x08000000 241 #define MIPS3_SR_FR 0x04000000 242 #define MIPS3_SR_RE 0x02000000 243 244 #define MIPS3_SR_DIAG_DL 0x01000000 /* QED 52xx */ 245 #define MIPS3_SR_DIAG_IL 0x00800000 /* QED 52xx */ 246 #define MIPS3_SR_PX 0x00800000 /* MIPS64 */ 247 #define MIPS3_SR_SR 0x00100000 248 #define MIPS3_SR_NMI 0x00080000 /* MIPS32/64 */ 249 #define MIPS3_SR_DIAG_CH 0x00040000 250 #define MIPS3_SR_DIAG_CE 0x00020000 251 #define MIPS3_SR_DIAG_PE 0x00010000 252 #define MIPS3_SR_EIE 0x00010000 /* TX79/R5900 */ 253 #define MIPS3_SR_KX 0x00000080 254 #define MIPS3_SR_SX 0x00000040 255 #define MIPS3_SR_UX 0x00000020 256 #define MIPS3_SR_KSU_MASK 0x00000018 257 #define MIPS3_SR_KSU_USER 0x00000010 258 #define MIPS3_SR_KSU_SUPER 0x00000008 259 #define MIPS3_SR_KSU_KERNEL 0x00000000 260 #define MIPS3_SR_ERL 0x00000004 261 #define MIPS3_SR_EXL 0x00000002 262 263 #ifdef MIPS3_5900 264 #undef MIPS_SR_INT_IE 265 #define MIPS_SR_INT_IE 0x00010001 /* XXX */ 266 #endif 267 268 #define MIPS_SR_SOFT_RESET MIPS3_SR_SOFT_RESET 269 #define MIPS_SR_DIAG_CH MIPS3_SR_DIAG_CH 270 #define MIPS_SR_DIAG_CE MIPS3_SR_DIAG_CE 271 #define MIPS_SR_DIAG_PE MIPS3_SR_DIAG_PE 272 #define MIPS_SR_KX MIPS3_SR_KX 273 #define MIPS_SR_SX MIPS3_SR_SX 274 #define MIPS_SR_UX MIPS3_SR_UX 275 276 #define MIPS_SR_KSU_MASK MIPS3_SR_KSU_MASK 277 #define MIPS_SR_KSU_USER MIPS3_SR_KSU_USER 278 #define MIPS_SR_KSU_SUPER MIPS3_SR_KSU_SUPER 279 #define MIPS_SR_KSU_KERNEL MIPS3_SR_KSU_KERNEL 280 #define MIPS_SR_ERL MIPS3_SR_ERL 281 #define MIPS_SR_EXL MIPS3_SR_EXL 282 283 284 /* 285 * The interrupt masks. 286 * If a bit in the mask is 1 then the interrupt is enabled (or pending). 287 */ 288 #define MIPS_INT_MASK 0xff00 289 #define MIPS_INT_MASK_5 0x8000 290 #define MIPS_INT_MASK_4 0x4000 291 #define MIPS_INT_MASK_3 0x2000 292 #define MIPS_INT_MASK_2 0x1000 293 #define MIPS_INT_MASK_1 0x0800 294 #define MIPS_INT_MASK_0 0x0400 295 #define MIPS_HARD_INT_MASK 0xfc00 296 #define MIPS_SOFT_INT_MASK_1 0x0200 297 #define MIPS_SOFT_INT_MASK_0 0x0100 298 #define MIPS_SOFT_INT_MASK 0x0300 299 #define MIPS_INT_MASK_SHIFT 8 300 301 /* 302 * mips3 CPUs have on-chip timer at INT_MASK_5. Each platform can 303 * choose to enable this interrupt. 304 */ 305 #if defined(MIPS3_ENABLE_CLOCK_INTR) 306 #define MIPS3_INT_MASK MIPS_INT_MASK 307 #define MIPS3_HARD_INT_MASK MIPS_HARD_INT_MASK 308 #else 309 #define MIPS3_INT_MASK (MIPS_INT_MASK & ~MIPS_INT_MASK_5) 310 #define MIPS3_HARD_INT_MASK (MIPS_HARD_INT_MASK & ~MIPS_INT_MASK_5) 311 #endif 312 313 /* 314 * The bits in the context register. 315 */ 316 #define MIPS1_CNTXT_PTE_BASE 0xFFE00000 317 #define MIPS1_CNTXT_BAD_VPN 0x001FFFFC 318 319 #define MIPS3_CNTXT_PTE_BASE 0xFF800000 320 #define MIPS3_CNTXT_BAD_VPN2 0x007FFFF0 321 322 /* 323 * The bits in the MIPS3 config register. 324 * 325 * bit 0..5: R/W, Bit 6..31: R/O 326 */ 327 328 /* kseg0 coherency algorithm - see MIPS3_TLB_ATTR values */ 329 #define MIPS3_CONFIG_K0_MASK 0x00000007 330 331 /* 332 * R/W Update on Store Conditional 333 * 0: Store Conditional uses coherency algorithm specified by TLB 334 * 1: Store Conditional uses cacheable coherent update on write 335 */ 336 #define MIPS3_CONFIG_CU 0x00000008 337 338 #define MIPS3_CONFIG_DB 0x00000010 /* Primary D-cache line size */ 339 #define MIPS3_CONFIG_IB 0x00000020 /* Primary I-cache line size */ 340 #define MIPS3_CONFIG_CACHE_L1_LSIZE(config, bit) \ 341 (((config) & (bit)) ? 32 : 16) 342 343 #define MIPS3_CONFIG_DC_MASK 0x000001c0 /* Primary D-cache size */ 344 #define MIPS3_CONFIG_DC_SHIFT 6 345 #define MIPS3_CONFIG_IC_MASK 0x00000e00 /* Primary I-cache size */ 346 #define MIPS3_CONFIG_IC_SHIFT 9 347 #define MIPS3_CONFIG_C_DEFBASE 0x1000 /* default base 2^12 */ 348 349 /* Cache size mode indication: available only on Vr41xx CPUs */ 350 #define MIPS3_CONFIG_CS 0x00001000 351 #define MIPS3_CONFIG_C_4100BASE 0x0400 /* base is 2^10 if CS=1 */ 352 #define MIPS3_CONFIG_CACHE_SIZE(config, mask, base, shift) \ 353 ((base) << (((config) & (mask)) >> (shift))) 354 355 /* External cache enable: Controls L2 for R5000/Rm527x and L3 for Rm7000 */ 356 #define MIPS3_CONFIG_SE 0x00001000 357 358 /* Block ordering: 0: sequential, 1: sub-block */ 359 #define MIPS3_CONFIG_EB 0x00002000 360 361 /* ECC mode - 0: ECC mode, 1: parity mode */ 362 #define MIPS3_CONFIG_EM 0x00004000 363 364 /* BigEndianMem - 0: kernel and memory are little endian, 1: big endian */ 365 #define MIPS3_CONFIG_BE 0x00008000 366 367 /* Dirty Shared coherency state - 0: enabled, 1: disabled */ 368 #define MIPS3_CONFIG_SM 0x00010000 369 370 /* Secondary Cache - 0: present, 1: not present */ 371 #define MIPS3_CONFIG_SC 0x00020000 372 373 /* System Port width - 0: 64-bit, 1: 32-bit (QED RM523x), 2,3: reserved */ 374 #define MIPS3_CONFIG_EW_MASK 0x000c0000 375 #define MIPS3_CONFIG_EW_SHIFT 18 376 377 /* Secondary Cache port width - 0: 128-bit data path to S-cache, 1: reserved */ 378 #define MIPS3_CONFIG_SW 0x00100000 379 380 /* Split Secondary Cache Mode - 0: I/D mixed, 1: I/D separated by SCAddr(17) */ 381 #define MIPS3_CONFIG_SS 0x00200000 382 383 /* Secondary Cache line size */ 384 #define MIPS3_CONFIG_SB_MASK 0x00c00000 385 #define MIPS3_CONFIG_SB_SHIFT 22 386 #define MIPS3_CONFIG_CACHE_L2_LSIZE(config) \ 387 (0x10 << (((config) & MIPS3_CONFIG_SB_MASK) >> MIPS3_CONFIG_SB_SHIFT)) 388 389 /* Write back data rate */ 390 #define MIPS3_CONFIG_EP_MASK 0x0f000000 391 #define MIPS3_CONFIG_EP_SHIFT 24 392 393 /* System clock ratio - this value is CPU dependent */ 394 #define MIPS3_CONFIG_EC_MASK 0x70000000 395 #define MIPS3_CONFIG_EC_SHIFT 28 396 397 /* Master-Checker Mode - 1: enabled */ 398 #define MIPS3_CONFIG_CM 0x80000000 399 400 /* 401 * The bits in the MIPS4 config register. 402 */ 403 404 /* kseg0 coherency algorithm - see MIPS3_TLB_ATTR values */ 405 #define MIPS4_CONFIG_K0_MASK MIPS3_CONFIG_K0_MASK 406 #define MIPS4_CONFIG_DN_MASK 0x00000018 /* Device number */ 407 #define MIPS4_CONFIG_CT 0x00000020 /* CohPrcReqTar */ 408 #define MIPS4_CONFIG_PE 0x00000040 /* PreElmReq */ 409 #define MIPS4_CONFIG_PM_MASK 0x00000180 /* PreReqMax */ 410 #define MIPS4_CONFIG_EC_MASK 0x00001e00 /* SysClkDiv */ 411 #define MIPS4_CONFIG_SB 0x00002000 /* SCBlkSize */ 412 #define MIPS4_CONFIG_SK 0x00004000 /* SCColEn */ 413 #define MIPS4_CONFIG_BE 0x00008000 /* MemEnd */ 414 #define MIPS4_CONFIG_SS_MASK 0x00070000 /* SCSize */ 415 #define MIPS4_CONFIG_SC_MASK 0x00380000 /* SCClkDiv */ 416 #define MIPS4_CONFIG_RESERVED 0x03c00000 /* Reserved wired 0 */ 417 #define MIPS4_CONFIG_DC_MASK 0x1c000000 /* Primary D-Cache size */ 418 #define MIPS4_CONFIG_IC_MASK 0xe0000000 /* Primary I-Cache size */ 419 420 #define MIPS4_CONFIG_DC_SHIFT 26 421 #define MIPS4_CONFIG_IC_SHIFT 29 422 423 #define MIPS4_CONFIG_CACHE_SIZE(config, mask, base, shift) \ 424 ((base) << (((config) & (mask)) >> (shift))) 425 426 #define MIPS4_CONFIG_CACHE_L2_LSIZE(config) \ 427 (((config) & MIPS4_CONFIG_SB) ? 128 : 64) 428 429 /* 430 * Location of exception vectors. 431 * 432 * Common vectors: reset and UTLB miss. 433 */ 434 #define MIPS_RESET_EXC_VEC MIPS_PHYS_TO_KSEG1(0x1FC00000) 435 #define MIPS_UTLB_MISS_EXC_VEC MIPS_PHYS_TO_KSEG0(0) 436 437 /* 438 * MIPS-1 general exception vector (everything else) 439 */ 440 #define MIPS1_GEN_EXC_VEC MIPS_PHYS_TO_KSEG0(0x0080) 441 442 /* 443 * MIPS-III exception vectors 444 */ 445 #define MIPS3_XTLB_MISS_EXC_VEC MIPS_PHYS_TO_KSEG0(0x0080) 446 #define MIPS3_CACHE_ERR_EXC_VEC MIPS_PHYS_TO_KSEG0(0x0100) 447 #define MIPS3_GEN_EXC_VEC MIPS_PHYS_TO_KSEG0(0x0180) 448 449 /* 450 * TX79 (R5900) exception vectors 451 */ 452 #define MIPS_R5900_COUNTER_EXC_VEC MIPS_PHYS_TO_KSEG0(0x0080) 453 #define MIPS_R5900_DEBUG_EXC_VEC MIPS_PHYS_TO_KSEG0(0x0100) 454 455 /* 456 * MIPS32/MIPS64 (and some MIPS3) dedicated interrupt vector. 457 */ 458 #define MIPS3_INTR_EXC_VEC MIPS_PHYS_TO_KSEG0(0x0200) 459 460 /* 461 * Coprocessor 0 registers: 462 * 463 * v--- width for mips I,III,32,64 464 * (3=32bit, 6=64bit, i=impl dep) 465 * 0 MIPS_COP_0_TLB_INDEX 3333 TLB Index. 466 * 1 MIPS_COP_0_TLB_RANDOM 3333 TLB Random. 467 * 2 MIPS_COP_0_TLB_LOW 3... r3k TLB entry low. 468 * 2 MIPS_COP_0_TLB_LO0 .636 r4k TLB entry low. 469 * 3 MIPS_COP_0_TLB_LO1 .636 r4k TLB entry low, extended. 470 * 4 MIPS_COP_0_TLB_CONTEXT 3636 TLB Context. 471 * 5 MIPS_COP_0_TLB_PG_MASK .333 TLB Page Mask register. 472 * 6 MIPS_COP_0_TLB_WIRED .333 Wired TLB number. 473 * 8 MIPS_COP_0_BAD_VADDR 3636 Bad virtual address. 474 * 9 MIPS_COP_0_COUNT .333 Count register. 475 * 10 MIPS_COP_0_TLB_HI 3636 TLB entry high. 476 * 11 MIPS_COP_0_COMPARE .333 Compare (against Count). 477 * 12 MIPS_COP_0_STATUS 3333 Status register. 478 * 13 MIPS_COP_0_CAUSE 3333 Exception cause register. 479 * 14 MIPS_COP_0_EXC_PC 3636 Exception PC. 480 * 15 MIPS_COP_0_PRID 3333 Processor revision identifier. 481 * 15/1 MIPS_COP_0_EBASE ..33 Exception Base 482 * 16 MIPS_COP_0_CONFIG 3333 Configuration register. 483 * 16/1 MIPS_COP_0_CONFIG1 ..33 Configuration register 1. 484 * 16/2 MIPS_COP_0_CONFIG2 ..33 Configuration register 2. 485 * 16/3 MIPS_COP_0_CONFIG3 ..33 Configuration register 3. 486 * 17 MIPS_COP_0_LLADDR .336 Load Linked Address. 487 * 18 MIPS_COP_0_WATCH_LO .336 WatchLo register. 488 * 19 MIPS_COP_0_WATCH_HI .333 WatchHi register. 489 * 20 MIPS_COP_0_TLB_XCONTEXT .6.6 TLB XContext register. 490 * 22 MIPS_COP_0_OSSCRATCH ...6 [RMI] OS Scratch register. (select 0..7) 491 * 23 MIPS_COP_0_DEBUG .... Debug JTAG register. 492 * 24 MIPS_COP_0_DEPC .... DEPC JTAG register. 493 * 25 MIPS_COP_0_PERFCNT ..36 Performance Counter register. 494 * 26 MIPS_COP_0_ECC .3ii ECC / Error Control register. 495 * 27 MIPS_COP_0_CACHE_ERR .3ii Cache Error register. 496 * 28/0 MIPS_COP_0_TAG_LO .3ii Cache TagLo register (instr). 497 * 28/1 MIPS_COP_0_DATA_LO ..ii Cache DataLo register (instr). 498 * 28/2 MIPS_COP_0_TAG_LO ..ii Cache TagLo register (data). 499 * 28/3 MIPS_COP_0_DATA_LO ..ii Cache DataLo register (data). 500 * 29/0 MIPS_COP_0_TAG_HI .3ii Cache TagHi register (instr). 501 * 29/1 MIPS_COP_0_DATA_HI ..ii Cache DataHi register (instr). 502 * 29/2 MIPS_COP_0_TAG_HI ..ii Cache TagHi register (data). 503 * 29/3 MIPS_COP_0_DATA_HI ..ii Cache DataHi register (data). 504 * 30 MIPS_COP_0_ERROR_PC .636 Error EPC register. 505 * 31 MIPS_COP_0_DESAVE .... DESAVE JTAG register. 506 */ 507 #ifdef _LOCORE 508 #define _(n) __CONCAT($,n) 509 #else 510 #define _(n) n 511 #endif 512 #define MIPS_COP_0_TLB_INDEX _(0) 513 #define MIPS_COP_0_TLB_RANDOM _(1) 514 /* Name and meaning of TLB bits for $2 differ on r3k and r4k. */ 515 516 #define MIPS_COP_0_TLB_CONTEXT _(4) 517 /* $5 and $6 new with MIPS-III */ 518 #define MIPS_COP_0_BAD_VADDR _(8) 519 #define MIPS_COP_0_TLB_HI _(10) 520 #define MIPS_COP_0_STATUS _(12) 521 #define MIPS_COP_0_CAUSE _(13) 522 #define MIPS_COP_0_EXC_PC _(14) 523 #define MIPS_COP_0_PRID _(15) 524 525 526 /* MIPS-I */ 527 #define MIPS_COP_0_TLB_LOW _(2) 528 529 /* MIPS-III */ 530 #define MIPS_COP_0_TLB_LO0 _(2) 531 #define MIPS_COP_0_TLB_LO1 _(3) 532 533 #define MIPS_COP_0_TLB_PG_MASK _(5) 534 #define MIPS_COP_0_TLB_WIRED _(6) 535 536 #define MIPS_COP_0_COUNT _(9) 537 #define MIPS_COP_0_COMPARE _(11) 538 539 #define MIPS_COP_0_CONFIG _(16) 540 #define MIPS_COP_0_LLADDR _(17) 541 #define MIPS_COP_0_WATCH_LO _(18) 542 #define MIPS_COP_0_WATCH_HI _(19) 543 #define MIPS_COP_0_TLB_XCONTEXT _(20) 544 #define MIPS_COP_0_ECC _(26) 545 #define MIPS_COP_0_CACHE_ERR _(27) 546 #define MIPS_COP_0_TAG_LO _(28) 547 #define MIPS_COP_0_TAG_HI _(29) 548 #define MIPS_COP_0_ERROR_PC _(30) 549 550 /* MIPS32/64 */ 551 #define MIPS_COP_0_OSSCRATCH _(22) 552 #define MIPS_COP_0_DEBUG _(23) 553 #define MIPS_COP_0_DEPC _(24) 554 #define MIPS_COP_0_PERFCNT _(25) 555 #define MIPS_COP_0_DATA_LO _(28) 556 #define MIPS_COP_0_DATA_HI _(29) 557 #define MIPS_COP_0_DESAVE _(31) 558 559 /* 560 * Values for the code field in a break instruction. 561 */ 562 #define MIPS_BREAK_INSTR 0x0000000d 563 #define MIPS_BREAK_VAL_MASK 0x03ff0000 564 #define MIPS_BREAK_VAL_SHIFT 16 565 #define MIPS_BREAK_KDB_VAL 512 566 #define MIPS_BREAK_SSTEP_VAL 513 567 #define MIPS_BREAK_BRKPT_VAL 514 568 #define MIPS_BREAK_SOVER_VAL 515 569 #define MIPS_BREAK_KDB (MIPS_BREAK_INSTR | \ 570 (MIPS_BREAK_KDB_VAL << MIPS_BREAK_VAL_SHIFT)) 571 #define MIPS_BREAK_SSTEP (MIPS_BREAK_INSTR | \ 572 (MIPS_BREAK_SSTEP_VAL << MIPS_BREAK_VAL_SHIFT)) 573 #define MIPS_BREAK_BRKPT (MIPS_BREAK_INSTR | \ 574 (MIPS_BREAK_BRKPT_VAL << MIPS_BREAK_VAL_SHIFT)) 575 #define MIPS_BREAK_SOVER (MIPS_BREAK_INSTR | \ 576 (MIPS_BREAK_SOVER_VAL << MIPS_BREAK_VAL_SHIFT)) 577 578 /* 579 * Mininum and maximum cache sizes. 580 */ 581 #define MIPS_MIN_CACHE_SIZE (16 * 1024) 582 #define MIPS_MAX_CACHE_SIZE (256 * 1024) 583 #define MIPS3_MAX_PCACHE_SIZE (32 * 1024) /* max. primary cache size */ 584 585 /* 586 * The floating point version and status registers. 587 */ 588 #define MIPS_FPU_ID $0 589 #define MIPS_FPU_CSR $31 590 591 /* 592 * The floating point coprocessor status register bits. 593 */ 594 #define MIPS_FPU_ROUNDING_BITS 0x00000003 595 #define MIPS_FPU_ROUND_RN 0x00000000 596 #define MIPS_FPU_ROUND_RZ 0x00000001 597 #define MIPS_FPU_ROUND_RP 0x00000002 598 #define MIPS_FPU_ROUND_RM 0x00000003 599 #define MIPS_FPU_STICKY_BITS 0x0000007c 600 #define MIPS_FPU_STICKY_INEXACT 0x00000004 601 #define MIPS_FPU_STICKY_UNDERFLOW 0x00000008 602 #define MIPS_FPU_STICKY_OVERFLOW 0x00000010 603 #define MIPS_FPU_STICKY_DIV0 0x00000020 604 #define MIPS_FPU_STICKY_INVALID 0x00000040 605 #define MIPS_FPU_ENABLE_BITS 0x00000f80 606 #define MIPS_FPU_ENABLE_INEXACT 0x00000080 607 #define MIPS_FPU_ENABLE_UNDERFLOW 0x00000100 608 #define MIPS_FPU_ENABLE_OVERFLOW 0x00000200 609 #define MIPS_FPU_ENABLE_DIV0 0x00000400 610 #define MIPS_FPU_ENABLE_INVALID 0x00000800 611 #define MIPS_FPU_EXCEPTION_BITS 0x0003f000 612 #define MIPS_FPU_EXCEPTION_INEXACT 0x00001000 613 #define MIPS_FPU_EXCEPTION_UNDERFLOW 0x00002000 614 #define MIPS_FPU_EXCEPTION_OVERFLOW 0x00004000 615 #define MIPS_FPU_EXCEPTION_DIV0 0x00008000 616 #define MIPS_FPU_EXCEPTION_INVALID 0x00010000 617 #define MIPS_FPU_EXCEPTION_UNIMPL 0x00020000 618 #define MIPS_FPU_COND_BIT 0x00800000 619 #define MIPS_FPU_FLUSH_BIT 0x01000000 /* r4k, MBZ on r3k */ 620 #define MIPS1_FPC_MBZ_BITS 0xff7c0000 621 #define MIPS3_FPC_MBZ_BITS 0xfe7c0000 622 623 624 /* 625 * Constants to determine if have a floating point instruction. 626 */ 627 #define MIPS_OPCODE_SHIFT 26 628 #define MIPS_OPCODE_C1 0x11 629 630 631 /* 632 * The low part of the TLB entry. 633 */ 634 #define MIPS1_TLB_PFN 0xfffff000 635 #define MIPS1_TLB_NON_CACHEABLE_BIT 0x00000800 636 #define MIPS1_TLB_DIRTY_BIT 0x00000400 637 #define MIPS1_TLB_VALID_BIT 0x00000200 638 #define MIPS1_TLB_GLOBAL_BIT 0x00000100 639 640 #define MIPS3_TLB_PFN 0x3fffffc0 641 #define MIPS3_TLB_ATTR_MASK 0x00000038 642 #define MIPS3_TLB_ATTR_SHIFT 3 643 #define MIPS3_TLB_DIRTY_BIT 0x00000004 644 #define MIPS3_TLB_VALID_BIT 0x00000002 645 #define MIPS3_TLB_GLOBAL_BIT 0x00000001 646 647 #define MIPS1_TLB_PHYS_PAGE_SHIFT 12 648 #define MIPS3_TLB_PHYS_PAGE_SHIFT 6 649 #define MIPS1_TLB_PF_NUM MIPS1_TLB_PFN 650 #define MIPS3_TLB_PF_NUM MIPS3_TLB_PFN 651 #define MIPS1_TLB_MOD_BIT MIPS1_TLB_DIRTY_BIT 652 #define MIPS3_TLB_MOD_BIT MIPS3_TLB_DIRTY_BIT 653 654 /* 655 * MIPS3_TLB_ATTR (CCA) values - coherency algorithm: 656 * 0: cacheable, noncoherent, write-through, no write allocate 657 * 1: cacheable, noncoherent, write-through, write allocate 658 * 2: uncached 659 * 3: cacheable, noncoherent, write-back (noncoherent) 660 * 4: cacheable, coherent, write-back, exclusive (exclusive) 661 * 5: cacheable, coherent, write-back, exclusive on write (sharable) 662 * 6: cacheable, coherent, write-back, update on write (update) 663 * 7: uncached, accelerated (gather STORE operations) 664 */ 665 #define MIPS3_TLB_ATTR_WT 0 /* IDT */ 666 #define MIPS3_TLB_ATTR_WT_WRITEALLOCATE 1 /* IDT */ 667 #define MIPS3_TLB_ATTR_UNCACHED 2 /* R4000/R4400, IDT */ 668 #define MIPS3_TLB_ATTR_WB_NONCOHERENT 3 /* R4000/R4400, IDT */ 669 #define MIPS3_TLB_ATTR_WB_EXCLUSIVE 4 /* R4000/R4400 */ 670 #define MIPS3_TLB_ATTR_WB_SHARABLE 5 /* R4000/R4400 */ 671 #define MIPS3_TLB_ATTR_WB_UPDATE 6 /* R4000/R4400 */ 672 #define MIPS4_TLB_ATTR_UNCACHED_ACCELERATED 7 /* R10000 */ 673 674 675 /* 676 * The high part of the TLB entry. 677 */ 678 #define MIPS1_TLB_VPN 0xfffff000 679 #define MIPS1_TLB_PID 0x00000fc0 680 #define MIPS1_TLB_PID_SHIFT 6 681 682 #define MIPS3_TLB_VPN2 0xffffe000 683 #define MIPS3_TLB_ASID 0x000000ff 684 685 #define MIPS1_TLB_VIRT_PAGE_NUM MIPS1_TLB_VPN 686 #define MIPS3_TLB_VIRT_PAGE_NUM MIPS3_TLB_VPN2 687 #define MIPS3_TLB_PID MIPS3_TLB_ASID 688 #define MIPS_TLB_VIRT_PAGE_SHIFT 12 689 690 /* 691 * r3000: shift count to put the index in the right spot. 692 */ 693 #define MIPS1_TLB_INDEX_SHIFT 8 694 695 /* 696 * The first TLB that write random hits. 697 */ 698 #define MIPS1_TLB_FIRST_RAND_ENTRY 8 699 #define MIPS3_TLB_WIRED_UPAGES 1 700 701 /* 702 * The number of process id entries. 703 */ 704 #define MIPS1_TLB_NUM_PIDS 64 705 #define MIPS3_TLB_NUM_ASIDS 256 706 707 /* 708 * Patch codes to hide CPU design differences between MIPS1 and MIPS3. 709 */ 710 711 /* XXX simonb: this is before MIPS3_PLUS is defined (and is ugly!) */ 712 713 #if !(defined(MIPS3) || defined(MIPS4) || defined(MIPS32) || defined(MIPS64)) \ 714 && defined(MIPS1) /* XXX simonb must be neater! */ 715 #define MIPS_TLB_PID_SHIFT MIPS1_TLB_PID_SHIFT 716 #define MIPS_TLB_NUM_PIDS MIPS1_TLB_NUM_PIDS 717 #endif 718 719 #if (defined(MIPS3) || defined(MIPS4) || defined(MIPS32) || defined(MIPS64)) \ 720 && !defined(MIPS1) /* XXX simonb must be neater! */ 721 #define MIPS_TLB_PID_SHIFT 0 722 #define MIPS_TLB_NUM_PIDS MIPS3_TLB_NUM_ASIDS 723 #endif 724 725 726 #if !defined(MIPS_TLB_PID_SHIFT) 727 #define MIPS_TLB_PID_SHIFT \ 728 ((MIPS_HAS_R4K_MMU) ? 0 : MIPS1_TLB_PID_SHIFT) 729 730 #define MIPS_TLB_NUM_PIDS \ 731 ((MIPS_HAS_R4K_MMU) ? MIPS3_TLB_NUM_ASIDS : MIPS1_TLB_NUM_PIDS) 732 #endif 733 734 /* 735 * Hints for the prefetch instruction 736 */ 737 738 /* 739 * Prefetched data is expected to be read (not modified) 740 */ 741 #define PREF_LOAD 0 742 #define PREF_LOAD_STREAMED 4 /* but not reused extensively; it */ 743 /* "streams" through cache. */ 744 #define PREF_LOAD_RETAINED 6 /* and reused extensively; it should */ 745 /* be "retained" in the cache. */ 746 747 /* 748 * Prefetched data is expected to be stored or modified 749 */ 750 #define PREF_STORE 1 751 #define PREF_STORE_STREAMED 5 /* but not reused extensively; it */ 752 /* "streams" through cache. */ 753 #define PREF_STORE_RETAINED 7 /* and reused extensively; it should */ 754 /* be "retained" in the cache. */ 755 756 /* 757 * data is no longer expected to be used. For a WB cache, schedule a 758 * writeback of any dirty data and afterwards free the cache lines. 759 */ 760 #define PREF_WB_INV 25 761 #define PREF_NUDGE PREF_WB_INV 762 763 /* 764 * Prepare for writing an entire cache line without the overhead 765 * involved in filling the line from memory. 766 */ 767 #define PREF_PREPAREFORSTORE 30 768 769 /* 770 * CPU processor revision IDs for company ID == 0 (non mips32/64 chips) 771 */ 772 #define MIPS_R2000 0x01 /* MIPS R2000 ISA I */ 773 #define MIPS_R3000 0x02 /* MIPS R3000 ISA I */ 774 #define MIPS_R6000 0x03 /* MIPS R6000 ISA II */ 775 #define MIPS_R4000 0x04 /* MIPS R4000/R4400 ISA III */ 776 #define MIPS_R3LSI 0x05 /* LSI Logic R3000 derivative ISA I */ 777 #define MIPS_R6000A 0x06 /* MIPS R6000A ISA II */ 778 #define MIPS_R3IDT 0x07 /* IDT R3041 or RC36100 ISA I */ 779 #define MIPS_R10000 0x09 /* MIPS R10000 ISA IV */ 780 #define MIPS_R4200 0x0a /* NEC VR4200 ISA III */ 781 #define MIPS_R4300 0x0b /* NEC VR4300 ISA III */ 782 #define MIPS_R4100 0x0c /* NEC VR4100 ISA III */ 783 #define MIPS_R12000 0x0e /* MIPS R12000 ISA IV */ 784 #define MIPS_R14000 0x0f /* MIPS R14000 ISA IV */ 785 #define MIPS_R8000 0x10 /* MIPS R8000 Blackbird/TFP ISA IV */ 786 #define MIPS_RC32300 0x18 /* IDT RC32334,332,355 ISA 32 */ 787 #define MIPS_R4600 0x20 /* QED R4600 Orion ISA III */ 788 #define MIPS_R4700 0x21 /* QED R4700 Orion ISA III */ 789 #define MIPS_R3SONY 0x21 /* Sony R3000 based ISA I */ 790 #define MIPS_R4650 0x22 /* QED R4650 ISA III */ 791 #define MIPS_TX3900 0x22 /* Toshiba TX39 family ISA I */ 792 #define MIPS_R5000 0x23 /* MIPS R5000 ISA IV */ 793 #define MIPS_R3NKK 0x23 /* NKK R3000 based ISA I */ 794 #define MIPS_RC32364 0x26 /* IDT RC32364 ISA 32 */ 795 #define MIPS_RM7000 0x27 /* QED RM7000 ISA IV */ 796 #define MIPS_RM5200 0x28 /* QED RM5200s ISA IV */ 797 #define MIPS_TX4900 0x2d /* Toshiba TX49 family ISA III */ 798 #define MIPS_R5900 0x2e /* Toshiba R5900 (EECore) ISA --- */ 799 #define MIPS_RC64470 0x30 /* IDT RC64474/RC64475 ISA III */ 800 #define MIPS_TX7900 0x38 /* Toshiba TX79 ISA III+*/ 801 #define MIPS_R5400 0x54 /* NEC VR5400 ISA IV */ 802 #define MIPS_R5500 0x55 /* NEC VR5500 ISA IV */ 803 804 /* 805 * CPU revision IDs for some prehistoric processors. 806 */ 807 808 /* For MIPS_R3000 */ 809 #define MIPS_REV_R2000A 0x16 /* R2000A uses R3000 proc revision */ 810 #define MIPS_REV_R3000 0x20 811 #define MIPS_REV_R3000A 0x30 812 813 /* For MIPS_TX3900 */ 814 #define MIPS_REV_TX3912 0x10 815 #define MIPS_REV_TX3922 0x30 816 #define MIPS_REV_TX3927 0x40 817 818 /* For MIPS_R4000 */ 819 #define MIPS_REV_R4000_A 0x00 820 #define MIPS_REV_R4000_B 0x22 821 #define MIPS_REV_R4000_C 0x30 822 #define MIPS_REV_R4400_A 0x40 823 #define MIPS_REV_R4400_B 0x50 824 #define MIPS_REV_R4400_C 0x60 825 826 /* For MIPS_TX4900 */ 827 #define MIPS_REV_TX4927 0x22 828 829 /* 830 * CPU processor revision IDs for company ID == 1 (MIPS) 831 */ 832 #define MIPS_4Kc 0x80 /* MIPS 4Kc ISA 32 */ 833 #define MIPS_5Kc 0x81 /* MIPS 5Kc ISA 64 */ 834 #define MIPS_20Kc 0x82 /* MIPS 20Kc ISA 64 */ 835 #define MIPS_4Kmp 0x83 /* MIPS 4Km/4Kp ISA 32 */ 836 #define MIPS_4KEc 0x84 /* MIPS 4KEc ISA 32 */ 837 #define MIPS_4KEmp 0x85 /* MIPS 4KEm/4KEp ISA 32 */ 838 #define MIPS_4KSc 0x86 /* MIPS 4KSc ISA 32 */ 839 #define MIPS_M4K 0x87 /* MIPS M4K ISA 32 Rel 2 */ 840 #define MIPS_25Kf 0x88 /* MIPS 25Kf ISA 64 */ 841 #define MIPS_5KE 0x89 /* MIPS 5KE ISA 64 Rel 2 */ 842 #define MIPS_4KEc_R2 0x90 /* MIPS 4KEc_R2 ISA 32 Rel 2 */ 843 #define MIPS_4KEmp_R2 0x91 /* MIPS 4KEm/4KEp_R2 ISA 32 Rel 2 */ 844 #define MIPS_4KSd 0x92 /* MIPS 4KSd ISA 32 Rel 2 */ 845 #define MIPS_24K 0x93 /* MIPS 24Kc/24Kf ISA 32 Rel 2 */ 846 #define MIPS_34K 0x95 /* MIPS 34K ISA 32 R2 MT */ 847 #define MIPS_24KE 0x96 /* MIPS 24KEc ISA 32 Rel 2 */ 848 #define MIPS_74K 0x97 /* MIPS 74Kc/74Kf ISA 32 Rel 2 */ 849 850 /* 851 * Alchemy (company ID 3) use the processor ID field to donote the CPU core 852 * revision and the company options field do donate the SOC chip type. 853 */ 854 /* CPU processor revision IDs */ 855 #define MIPS_AU_REV1 0x01 /* Alchemy Au1000 (Rev 1) ISA 32 */ 856 #define MIPS_AU_REV2 0x02 /* Alchemy Au1000 (Rev 2) ISA 32 */ 857 /* CPU company options IDs */ 858 #define MIPS_AU1000 0x00 859 #define MIPS_AU1500 0x01 860 #define MIPS_AU1100 0x02 861 #define MIPS_AU1550 0x03 862 863 /* 864 * CPU processor revision IDs for company ID == 4 (SiByte) 865 */ 866 #define MIPS_SB1 0x01 /* SiByte SB1 ISA 64 */ 867 868 /* 869 * CPU processor revision IDs for company ID == 5 (SandCraft) 870 */ 871 #define MIPS_SR7100 0x04 /* SandCraft SR7100 ISA 64 */ 872 873 /* 874 * CPU processor revision IDs for company ID == 12 (RMI) 875 */ 876 #define MIPS_XLR732 0x00 /* RMI XLR732-C ISA 64 */ 877 #define MIPS_XLR716 0x02 /* RMI XLR716-C ISA 64 */ 878 #define MIPS_XLR532 0x08 /* RMI XLR532-C ISA 64 */ 879 #define MIPS_XLR516 0x0a /* RMI XLR516-C ISA 64 */ 880 #define MIPS_XLR508 0x0b /* RMI XLR508-C ISA 64 */ 881 #define MIPS_XLR308 0x0f /* RMI XLR308-C ISA 64 */ 882 #define MIPS_XLS616 0x40 /* RMI XLS616 ISA 64 */ 883 #define MIPS_XLS416 0x44 /* RMI XLS416 ISA 64 */ 884 #define MIPS_XLS608 0x4A /* RMI XLS608 ISA 64 */ 885 #define MIPS_XLS408 0x4E /* RMI XLS406 ISA 64 */ 886 #define MIPS_XLS404 0x4F /* RMI XLS404 ISA 64 */ 887 #define MIPS_XLS408LITE 0x88 /* RMI XLS408-Lite ISA 64 */ 888 #define MIPS_XLS404LITE 0x8C /* RMI XLS404-Lite ISA 64 */ 889 #define MIPS_XLS208 0x8E /* RMI XLS208 ISA 64 */ 890 #define MIPS_XLS204 0x8F /* RMI XLS204 ISA 64 */ 891 #define MIPS_XLS108 0xCE /* RMI XLS108 ISA 64 */ 892 #define MIPS_XLS104 0xCF /* RMI XLS104 ISA 64 */ 893 894 /* 895 * FPU processor revision ID 896 */ 897 #define MIPS_SOFT 0x00 /* Software emulation ISA I */ 898 #define MIPS_R2360 0x01 /* MIPS R2360 FPC ISA I */ 899 #define MIPS_R2010 0x02 /* MIPS R2010 FPC ISA I */ 900 #define MIPS_R3010 0x03 /* MIPS R3010 FPC ISA I */ 901 #define MIPS_R6010 0x04 /* MIPS R6010 FPC ISA II */ 902 #define MIPS_R4010 0x05 /* MIPS R4010 FPC ISA II */ 903 #define MIPS_R31LSI 0x06 /* LSI Logic derivate ISA I */ 904 #define MIPS_R3TOSH 0x22 /* Toshiba R3000 based FPU ISA I */ 905 906 #ifdef ENABLE_MIPS_TX3900 907 #include <mips/r3900regs.h> 908 #endif 909 #ifdef MIPS3_5900 910 #include <mips/r5900regs.h> 911 #endif 912 #ifdef MIPS64_SB1 913 #include <mips/sb1regs.h> 914 #endif 915 #if defined(MIPS64_XLP) || defined(MIPS64_XLR) || defined(MIPS64_XLS) 916 #include <mips/rmi/rmixlreg.h> 917 #endif 918 919 #endif /* _MIPS_CPUREGS_H_ */ 920
Indexes created Tue Oct 28 12:10:06 GMT 2025