cpuregs.h revision 1.74.28.2
1 /* $NetBSD: cpuregs.h,v 1.74.28.2 2009/08/21 17:26:23 matt Exp $ */ 2 3 /* 4 * Copyright (c) 1992, 1993 5 * The Regents of the University of California. All rights reserved. 6 * 7 * This code is derived from software contributed to Berkeley by 8 * Ralph Campbell and Rick Macklem. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. Neither the name of the University nor the names of its contributors 19 * may be used to endorse or promote products derived from this software 20 * without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 27 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 28 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 29 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 30 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 31 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 32 * SUCH DAMAGE. 33 * 34 * @(#)machConst.h 8.1 (Berkeley) 6/10/93 35 * 36 * machConst.h -- 37 * 38 * Machine dependent constants. 39 * 40 * Copyright (C) 1989 Digital Equipment Corporation. 41 * Permission to use, copy, modify, and distribute this software and 42 * its documentation for any purpose and without fee is hereby granted, 43 * provided that the above copyright notice appears in all copies. 44 * Digital Equipment Corporation makes no representations about the 45 * suitability of this software for any purpose. It is provided "as is" 46 * without express or implied warranty. 47 * 48 * from: Header: /sprite/src/kernel/mach/ds3100.md/RCS/machConst.h, 49 * v 9.2 89/10/21 15:55:22 jhh Exp SPRITE (DECWRL) 50 * from: Header: /sprite/src/kernel/mach/ds3100.md/RCS/machAddrs.h, 51 * v 1.2 89/08/15 18:28:21 rab Exp SPRITE (DECWRL) 52 * from: Header: /sprite/src/kernel/vm/ds3100.md/RCS/vmPmaxConst.h, 53 * v 9.1 89/09/18 17:33:00 shirriff Exp SPRITE (DECWRL) 54 */ 55 56 #ifndef _MIPS_CPUREGS_H_ 57 #define _MIPS_CPUREGS_H_ 58 59 #include <sys/cdefs.h> /* For __CONCAT() */ 60 61 #if defined(_KERNEL_OPT) 62 #include "opt_cputype.h" 63 #endif 64 65 /* 66 * Address space. 67 * 32-bit mips CPUS partition their 32-bit address space into four segments: 68 * 69 * kuseg 0x00000000 - 0x7fffffff User virtual mem, mapped 70 * kseg0 0x80000000 - 0x9fffffff Physical memory, cached, unmapped 71 * kseg1 0xa0000000 - 0xbfffffff Physical memory, uncached, unmapped 72 * kseg2 0xc0000000 - 0xffffffff kernel-virtual, mapped 73 * 74 * mips1 physical memory is limited to 512Mbytes, which is 75 * doubly mapped in kseg0 (cached) and kseg1 (uncached.) 76 * Caching of mapped addresses is controlled by bits in the TLB entry. 77 */ 78 79 #define MIPS_KUSEG_START 0x0L 80 81 /* 82 * MIPS addresses are signed and we defining as negative so that 83 * in LP64 kern they get sign-extended correctly. 84 */ 85 #define MIPS_KSEG0_START (-0x7fffffff-1) /* 0x80000000 */ 86 #define MIPS_KSEG1_START -0x60000000 /* 0xa0000000 */ 87 #define MIPS_KSEG2_START -0x40000000 /* 0xc0000000 */ 88 #define MIPS_MAX_MEM_ADDR -0x42000000 /* 0xbe000000 */ 89 #define MIPS_RESERVED_ADDR -0x40380000 /* 0xbfc80000 */ 90 91 #define MIPS_PHYS_MASK 0x1fffffff 92 93 #define MIPS_KSEG0_TO_PHYS(x) ((uintptr_t)(x) & MIPS_PHYS_MASK) 94 #define MIPS_PHYS_TO_KSEG0(x) ((uintptr_t)(x) | (intptr_t)MIPS_KSEG0_START) 95 #define MIPS_KSEG1_TO_PHYS(x) ((uintptr_t)(x) & MIPS_PHYS_MASK) 96 #define MIPS_PHYS_TO_KSEG1(x) ((uintptr_t)(x) | (intptr_t)MIPS_KSEG1_START) 97 98 /* Map virtual address to index in mips3 r4k virtually-indexed cache */ 99 #define MIPS3_VA_TO_CINDEX(x) \ 100 (((intptr_t)(x) & 0xffffff) | MIPS_KSEG0_START) 101 #define MIPS_XSEG_MASK (0x3fffffffffffffffLL) 102 #define MIPS_XKSEG_START (0x3ULL << 62) 103 #define MIPS_XKSEG_P(x) (((uint64_t)(x) >> 62) == 3) 104 105 #define MIPS_XKPHYS_START (0x2ULL << 62) 106 #define MIPS_PHYS_TO_XKPHYS(cca,x) \ 107 (MIPS_XKPHYS_START | ((uint64_t)(cca) << 59) | (x)) 108 #define MIPS_XKPHYS_TO_PHYS(x) ((x) & 0x0effffffffffffffLL) 109 #define MIPS_XKPHYS_P(x) (((uint64_t)(x) >> 62) == 2) 110 111 /* CPU dependent mtc0 hazard hook */ 112 #define COP0_SYNC /* nothing */ 113 #define COP0_HAZARD_FPUENABLE nop; nop; nop; nop; 114 115 /* 116 * The bits in the cause register. 117 * 118 * Bits common to r3000 and r4000: 119 * 120 * MIPS_CR_BR_DELAY Exception happened in branch delay slot. 121 * MIPS_CR_COP_ERR Coprocessor error. 122 * MIPS_CR_IP Interrupt pending bits defined below. 123 * (same meaning as in CAUSE register). 124 * MIPS_CR_EXC_CODE The exception type (see exception codes below). 125 * 126 * Differences: 127 * r3k has 4 bits of execption type, r4k has 5 bits. 128 */ 129 #define MIPS_CR_BR_DELAY 0x80000000 130 #define MIPS_CR_COP_ERR 0x30000000 131 #define MIPS1_CR_EXC_CODE 0x0000003C /* four bits */ 132 #define MIPS3_CR_EXC_CODE 0x0000007C /* five bits */ 133 #define MIPS_CR_IP 0x0000FF00 134 #define MIPS_CR_EXC_CODE_SHIFT 2 135 136 /* 137 * The bits in the status register. All bits are active when set to 1. 138 * 139 * R3000 status register fields: 140 * MIPS_SR_COP_USABILITY Control the usability of the four coprocessors. 141 * MIPS_SR_TS TLB shutdown. 142 * 143 * MIPS_SR_INT_IE Master (current) interrupt enable bit. 144 * 145 * Differences: 146 * r3k has cache control is via frobbing SR register bits, whereas the 147 * r4k cache control is via explicit instructions. 148 * r3k has a 3-entry stack of kernel/user bits, whereas the 149 * r4k has kernel/supervisor/user. 150 */ 151 #define MIPS_SR_COP_USABILITY 0xf0000000 152 #define MIPS_SR_COP_0_BIT 0x10000000 153 #define MIPS_SR_COP_1_BIT 0x20000000 154 155 /* r4k and r3k differences, see below */ 156 157 #define MIPS_SR_MX 0x01000000 /* MIPS64 */ 158 #define MIPS_SR_PX 0x00800000 /* MIPS64 */ 159 #define MIPS_SR_BEV 0x00400000 /* Use boot exception vector */ 160 #define MIPS_SR_TS 0x00200000 161 162 /* r4k and r3k differences, see below */ 163 164 #define MIPS_SR_INT_IE 0x00000001 165 /*#define MIPS_SR_MBZ 0x0f8000c0*/ /* Never used, true for r3k */ 166 /*#define MIPS_SR_INT_MASK 0x0000ff00*/ 167 168 169 /* 170 * The R2000/R3000-specific status register bit definitions. 171 * all bits are active when set to 1. 172 * 173 * MIPS_SR_PARITY_ERR Parity error. 174 * MIPS_SR_CACHE_MISS Most recent D-cache load resulted in a miss. 175 * MIPS_SR_PARITY_ZERO Zero replaces outgoing parity bits. 176 * MIPS_SR_SWAP_CACHES Swap I-cache and D-cache. 177 * MIPS_SR_ISOL_CACHES Isolate D-cache from main memory. 178 * Interrupt enable bits defined below. 179 * MIPS_SR_KU_OLD Old kernel/user mode bit. 1 => user mode. 180 * MIPS_SR_INT_ENA_OLD Old interrupt enable bit. 181 * MIPS_SR_KU_PREV Previous kernel/user mode bit. 1 => user mode. 182 * MIPS_SR_INT_ENA_PREV Previous interrupt enable bit. 183 * MIPS_SR_KU_CUR Current kernel/user mode bit. 1 => user mode. 184 */ 185 186 #define MIPS1_PARITY_ERR 0x00100000 187 #define MIPS1_CACHE_MISS 0x00080000 188 #define MIPS1_PARITY_ZERO 0x00040000 189 #define MIPS1_SWAP_CACHES 0x00020000 190 #define MIPS1_ISOL_CACHES 0x00010000 191 192 #define MIPS1_SR_KU_OLD 0x00000020 /* 2nd stacked KU/IE*/ 193 #define MIPS1_SR_INT_ENA_OLD 0x00000010 /* 2nd stacked KU/IE*/ 194 #define MIPS1_SR_KU_PREV 0x00000008 /* 1st stacked KU/IE*/ 195 #define MIPS1_SR_INT_ENA_PREV 0x00000004 /* 1st stacked KU/IE*/ 196 #define MIPS1_SR_KU_CUR 0x00000002 /* current KU */ 197 198 /* backwards compatibility */ 199 #define MIPS_SR_PARITY_ERR MIPS1_PARITY_ERR 200 #define MIPS_SR_CACHE_MISS MIPS1_CACHE_MISS 201 #define MIPS_SR_PARITY_ZERO MIPS1_PARITY_ZERO 202 #define MIPS_SR_SWAP_CACHES MIPS1_SWAP_CACHES 203 #define MIPS_SR_ISOL_CACHES MIPS1_ISOL_CACHES 204 205 #define MIPS_SR_KU_OLD MIPS1_SR_KU_OLD 206 #define MIPS_SR_INT_ENA_OLD MIPS1_SR_INT_ENA_OLD 207 #define MIPS_SR_KU_PREV MIPS1_SR_KU_PREV 208 #define MIPS_SR_KU_CUR MIPS1_SR_KU_CUR 209 #define MIPS_SR_INT_ENA_PREV MIPS1_SR_INT_ENA_PREV 210 211 /* 212 * R4000 status register bit definitons, 213 * where different from r2000/r3000. 214 */ 215 #define MIPS3_SR_XX 0x80000000 216 #define MIPS3_SR_RP 0x08000000 217 #define MIPS3_SR_FR 0x04000000 218 #define MIPS3_SR_RE 0x02000000 219 220 #define MIPS3_SR_DIAG_DL 0x01000000 /* QED 52xx */ 221 #define MIPS3_SR_DIAG_IL 0x00800000 /* QED 52xx */ 222 #define MIPS3_SR_SR 0x00100000 223 #define MIPS3_SR_NMI 0x00080000 /* MIPS32/64 */ 224 #define MIPS3_SR_DIAG_CH 0x00040000 225 #define MIPS3_SR_DIAG_CE 0x00020000 226 #define MIPS3_SR_DIAG_PE 0x00010000 227 #define MIPS3_SR_EIE 0x00010000 /* TX79/R5900 */ 228 #define MIPS3_SR_KX 0x00000080 229 #define MIPS3_SR_SX 0x00000040 230 #define MIPS3_SR_UX 0x00000020 231 #define MIPS3_SR_KSU_MASK 0x00000018 232 #define MIPS3_SR_KSU_USER 0x00000010 233 #define MIPS3_SR_KSU_SUPER 0x00000008 234 #define MIPS3_SR_KSU_KERNEL 0x00000000 235 #define MIPS3_SR_ERL 0x00000004 236 #define MIPS3_SR_EXL 0x00000002 237 238 #ifdef MIPS3_5900 239 #undef MIPS_SR_INT_IE 240 #define MIPS_SR_INT_IE 0x00010001 /* XXX */ 241 #endif 242 243 #define MIPS_SR_SOFT_RESET MIPS3_SR_SOFT_RESET 244 #define MIPS_SR_DIAG_CH MIPS3_SR_DIAG_CH 245 #define MIPS_SR_DIAG_CE MIPS3_SR_DIAG_CE 246 #define MIPS_SR_DIAG_PE MIPS3_SR_DIAG_PE 247 #define MIPS_SR_KX MIPS3_SR_KX 248 #define MIPS_SR_SX MIPS3_SR_SX 249 #define MIPS_SR_UX MIPS3_SR_UX 250 251 #define MIPS_SR_KSU_MASK MIPS3_SR_KSU_MASK 252 #define MIPS_SR_KSU_USER MIPS3_SR_KSU_USER 253 #define MIPS_SR_KSU_SUPER MIPS3_SR_KSU_SUPER 254 #define MIPS_SR_KSU_KERNEL MIPS3_SR_KSU_KERNEL 255 #define MIPS_SR_ERL MIPS3_SR_ERL 256 #define MIPS_SR_EXL MIPS3_SR_EXL 257 258 259 /* 260 * The interrupt masks. 261 * If a bit in the mask is 1 then the interrupt is enabled (or pending). 262 */ 263 #define MIPS_INT_MASK 0xff00 264 #define MIPS_INT_MASK_5 0x8000 265 #define MIPS_INT_MASK_4 0x4000 266 #define MIPS_INT_MASK_3 0x2000 267 #define MIPS_INT_MASK_2 0x1000 268 #define MIPS_INT_MASK_1 0x0800 269 #define MIPS_INT_MASK_0 0x0400 270 #define MIPS_HARD_INT_MASK 0xfc00 271 #define MIPS_SOFT_INT_MASK_1 0x0200 272 #define MIPS_SOFT_INT_MASK_0 0x0100 273 274 /* 275 * mips3 CPUs have on-chip timer at INT_MASK_5. Each platform can 276 * choose to enable this interrupt. 277 */ 278 #if defined(MIPS3_ENABLE_CLOCK_INTR) 279 #define MIPS3_INT_MASK MIPS_INT_MASK 280 #define MIPS3_HARD_INT_MASK MIPS_HARD_INT_MASK 281 #else 282 #define MIPS3_INT_MASK (MIPS_INT_MASK & ~MIPS_INT_MASK_5) 283 #define MIPS3_HARD_INT_MASK (MIPS_HARD_INT_MASK & ~MIPS_INT_MASK_5) 284 #endif 285 286 /* 287 * The bits in the context register. 288 */ 289 #define MIPS1_CNTXT_PTE_BASE 0xFFE00000 290 #define MIPS1_CNTXT_BAD_VPN 0x001FFFFC 291 292 #define MIPS3_CNTXT_PTE_BASE 0xFF800000 293 #define MIPS3_CNTXT_BAD_VPN2 0x007FFFF0 294 295 /* 296 * The bits in the MIPS3 config register. 297 * 298 * bit 0..5: R/W, Bit 6..31: R/O 299 */ 300 301 /* kseg0 coherency algorithm - see MIPS3_TLB_ATTR values */ 302 #define MIPS3_CONFIG_K0_MASK 0x00000007 303 304 /* 305 * R/W Update on Store Conditional 306 * 0: Store Conditional uses coherency algorithm specified by TLB 307 * 1: Store Conditional uses cacheable coherent update on write 308 */ 309 #define MIPS3_CONFIG_CU 0x00000008 310 311 #define MIPS3_CONFIG_DB 0x00000010 /* Primary D-cache line size */ 312 #define MIPS3_CONFIG_IB 0x00000020 /* Primary I-cache line size */ 313 #define MIPS3_CONFIG_CACHE_L1_LSIZE(config, bit) \ 314 (((config) & (bit)) ? 32 : 16) 315 316 #define MIPS3_CONFIG_DC_MASK 0x000001c0 /* Primary D-cache size */ 317 #define MIPS3_CONFIG_DC_SHIFT 6 318 #define MIPS3_CONFIG_IC_MASK 0x00000e00 /* Primary I-cache size */ 319 #define MIPS3_CONFIG_IC_SHIFT 9 320 #define MIPS3_CONFIG_C_DEFBASE 0x1000 /* default base 2^12 */ 321 322 /* Cache size mode indication: available only on Vr41xx CPUs */ 323 #define MIPS3_CONFIG_CS 0x00001000 324 #define MIPS3_CONFIG_C_4100BASE 0x0400 /* base is 2^10 if CS=1 */ 325 #define MIPS3_CONFIG_CACHE_SIZE(config, mask, base, shift) \ 326 ((base) << (((config) & (mask)) >> (shift))) 327 328 /* External cache enable: Controls L2 for R5000/Rm527x and L3 for Rm7000 */ 329 #define MIPS3_CONFIG_SE 0x00001000 330 331 /* Block ordering: 0: sequential, 1: sub-block */ 332 #define MIPS3_CONFIG_EB 0x00002000 333 334 /* ECC mode - 0: ECC mode, 1: parity mode */ 335 #define MIPS3_CONFIG_EM 0x00004000 336 337 /* BigEndianMem - 0: kernel and memory are little endian, 1: big endian */ 338 #define MIPS3_CONFIG_BE 0x00008000 339 340 /* Dirty Shared coherency state - 0: enabled, 1: disabled */ 341 #define MIPS3_CONFIG_SM 0x00010000 342 343 /* Secondary Cache - 0: present, 1: not present */ 344 #define MIPS3_CONFIG_SC 0x00020000 345 346 /* System Port width - 0: 64-bit, 1: 32-bit (QED RM523x), 2,3: reserved */ 347 #define MIPS3_CONFIG_EW_MASK 0x000c0000 348 #define MIPS3_CONFIG_EW_SHIFT 18 349 350 /* Secondary Cache port width - 0: 128-bit data path to S-cache, 1: reserved */ 351 #define MIPS3_CONFIG_SW 0x00100000 352 353 /* Split Secondary Cache Mode - 0: I/D mixed, 1: I/D separated by SCAddr(17) */ 354 #define MIPS3_CONFIG_SS 0x00200000 355 356 /* Secondary Cache line size */ 357 #define MIPS3_CONFIG_SB_MASK 0x00c00000 358 #define MIPS3_CONFIG_SB_SHIFT 22 359 #define MIPS3_CONFIG_CACHE_L2_LSIZE(config) \ 360 (0x10 << (((config) & MIPS3_CONFIG_SB_MASK) >> MIPS3_CONFIG_SB_SHIFT)) 361 362 /* Write back data rate */ 363 #define MIPS3_CONFIG_EP_MASK 0x0f000000 364 #define MIPS3_CONFIG_EP_SHIFT 24 365 366 /* System clock ratio - this value is CPU dependent */ 367 #define MIPS3_CONFIG_EC_MASK 0x70000000 368 #define MIPS3_CONFIG_EC_SHIFT 28 369 370 /* Master-Checker Mode - 1: enabled */ 371 #define MIPS3_CONFIG_CM 0x80000000 372 373 /* 374 * The bits in the MIPS4 config register. 375 */ 376 377 /* kseg0 coherency algorithm - see MIPS3_TLB_ATTR values */ 378 #define MIPS4_CONFIG_K0_MASK MIPS3_CONFIG_K0_MASK 379 #define MIPS4_CONFIG_DN_MASK 0x00000018 /* Device number */ 380 #define MIPS4_CONFIG_CT 0x00000020 /* CohPrcReqTar */ 381 #define MIPS4_CONFIG_PE 0x00000040 /* PreElmReq */ 382 #define MIPS4_CONFIG_PM_MASK 0x00000180 /* PreReqMax */ 383 #define MIPS4_CONFIG_EC_MASK 0x00001e00 /* SysClkDiv */ 384 #define MIPS4_CONFIG_SB 0x00002000 /* SCBlkSize */ 385 #define MIPS4_CONFIG_SK 0x00004000 /* SCColEn */ 386 #define MIPS4_CONFIG_BE 0x00008000 /* MemEnd */ 387 #define MIPS4_CONFIG_SS_MASK 0x00070000 /* SCSize */ 388 #define MIPS4_CONFIG_SC_MASK 0x00380000 /* SCClkDiv */ 389 #define MIPS4_CONFIG_RESERVED 0x03c00000 /* Reserved wired 0 */ 390 #define MIPS4_CONFIG_DC_MASK 0x1c000000 /* Primary D-Cache size */ 391 #define MIPS4_CONFIG_IC_MASK 0xe0000000 /* Primary I-Cache size */ 392 393 #define MIPS4_CONFIG_DC_SHIFT 26 394 #define MIPS4_CONFIG_IC_SHIFT 29 395 396 #define MIPS4_CONFIG_CACHE_SIZE(config, mask, base, shift) \ 397 ((base) << (((config) & (mask)) >> (shift))) 398 399 #define MIPS4_CONFIG_CACHE_L2_LSIZE(config) \ 400 (((config) & MIPS4_CONFIG_SB) ? 128 : 64) 401 402 /* 403 * Location of exception vectors. 404 * 405 * Common vectors: reset and UTLB miss. 406 */ 407 #define MIPS_RESET_EXC_VEC MIPS_PHYS_TO_KSEG1(0x1FC00000) 408 #define MIPS_UTLB_MISS_EXC_VEC MIPS_PHYS_TO_KSEG0(0) 409 410 /* 411 * MIPS-1 general exception vector (everything else) 412 */ 413 #define MIPS1_GEN_EXC_VEC MIPS_PHYS_TO_KSEG0(0x0080) 414 415 /* 416 * MIPS-III exception vectors 417 */ 418 #define MIPS3_XTLB_MISS_EXC_VEC MIPS_PHYS_TO_KSEG0(0x0080) 419 #define MIPS3_CACHE_ERR_EXC_VEC MIPS_PHYS_TO_KSEG0(0x0100) 420 #define MIPS3_GEN_EXC_VEC MIPS_PHYS_TO_KSEG0(0x0180) 421 422 /* 423 * TX79 (R5900) exception vectors 424 */ 425 #define MIPS_R5900_COUNTER_EXC_VEC MIPS_PHYS_TO_KSEG0(0x0080) 426 #define MIPS_R5900_DEBUG_EXC_VEC MIPS_PHYS_TO_KSEG0(0x0100) 427 428 /* 429 * MIPS32/MIPS64 (and some MIPS3) dedicated interrupt vector. 430 */ 431 #define MIPS3_INTR_EXC_VEC MIPS_PHYS_TO_KSEG0(0x0200) 432 433 /* 434 * Coprocessor 0 registers: 435 * 436 * v--- width for mips I,III,32,64 437 * (3=32bit, 6=64bit, i=impl dep) 438 * 0 MIPS_COP_0_TLB_INDEX 3333 TLB Index. 439 * 1 MIPS_COP_0_TLB_RANDOM 3333 TLB Random. 440 * 2 MIPS_COP_0_TLB_LOW 3... r3k TLB entry low. 441 * 2 MIPS_COP_0_TLB_LO0 .636 r4k TLB entry low. 442 * 3 MIPS_COP_0_TLB_LO1 .636 r4k TLB entry low, extended. 443 * 4 MIPS_COP_0_TLB_CONTEXT 3636 TLB Context. 444 * 5 MIPS_COP_0_TLB_PG_MASK .333 TLB Page Mask register. 445 * 6 MIPS_COP_0_TLB_WIRED .333 Wired TLB number. 446 * 8 MIPS_COP_0_BAD_VADDR 3636 Bad virtual address. 447 * 9 MIPS_COP_0_COUNT .333 Count register. 448 * 10 MIPS_COP_0_TLB_HI 3636 TLB entry high. 449 * 11 MIPS_COP_0_COMPARE .333 Compare (against Count). 450 * 12 MIPS_COP_0_STATUS 3333 Status register. 451 * 13 MIPS_COP_0_CAUSE 3333 Exception cause register. 452 * 14 MIPS_COP_0_EXC_PC 3636 Exception PC. 453 * 15 MIPS_COP_0_PRID 3333 Processor revision identifier. 454 * 16 MIPS_COP_0_CONFIG 3333 Configuration register. 455 * 16/1 MIPS_COP_0_CONFIG1 ..33 Configuration register 1. 456 * 16/2 MIPS_COP_0_CONFIG2 ..33 Configuration register 2. 457 * 16/3 MIPS_COP_0_CONFIG3 ..33 Configuration register 3. 458 * 17 MIPS_COP_0_LLADDR .336 Load Linked Address. 459 * 18 MIPS_COP_0_WATCH_LO .336 WatchLo register. 460 * 19 MIPS_COP_0_WATCH_HI .333 WatchHi register. 461 * 20 MIPS_COP_0_TLB_XCONTEXT .6.6 TLB XContext register. 462 * 23 MIPS_COP_0_DEBUG .... Debug JTAG register. 463 * 24 MIPS_COP_0_DEPC .... DEPC JTAG register. 464 * 25 MIPS_COP_0_PERFCNT ..36 Performance Counter register. 465 * 26 MIPS_COP_0_ECC .3ii ECC / Error Control register. 466 * 27 MIPS_COP_0_CACHE_ERR .3ii Cache Error register. 467 * 28/0 MIPS_COP_0_TAG_LO .3ii Cache TagLo register (instr). 468 * 28/1 MIPS_COP_0_DATA_LO ..ii Cache DataLo register (instr). 469 * 28/2 MIPS_COP_0_TAG_LO ..ii Cache TagLo register (data). 470 * 28/3 MIPS_COP_0_DATA_LO ..ii Cache DataLo register (data). 471 * 29/0 MIPS_COP_0_TAG_HI .3ii Cache TagHi register (instr). 472 * 29/1 MIPS_COP_0_DATA_HI ..ii Cache DataHi register (instr). 473 * 29/2 MIPS_COP_0_TAG_HI ..ii Cache TagHi register (data). 474 * 29/3 MIPS_COP_0_DATA_HI ..ii Cache DataHi register (data). 475 * 30 MIPS_COP_0_ERROR_PC .636 Error EPC register. 476 * 31 MIPS_COP_0_DESAVE .... DESAVE JTAG register. 477 */ 478 #ifdef _LOCORE 479 #define _(n) __CONCAT($,n) 480 #else 481 #define _(n) n 482 #endif 483 #define MIPS_COP_0_TLB_INDEX _(0) 484 #define MIPS_COP_0_TLB_RANDOM _(1) 485 /* Name and meaning of TLB bits for $2 differ on r3k and r4k. */ 486 487 #define MIPS_COP_0_TLB_CONTEXT _(4) 488 /* $5 and $6 new with MIPS-III */ 489 #define MIPS_COP_0_BAD_VADDR _(8) 490 #define MIPS_COP_0_TLB_HI _(10) 491 #define MIPS_COP_0_STATUS _(12) 492 #define MIPS_COP_0_CAUSE _(13) 493 #define MIPS_COP_0_EXC_PC _(14) 494 #define MIPS_COP_0_PRID _(15) 495 496 497 /* MIPS-I */ 498 #define MIPS_COP_0_TLB_LOW _(2) 499 500 /* MIPS-III */ 501 #define MIPS_COP_0_TLB_LO0 _(2) 502 #define MIPS_COP_0_TLB_LO1 _(3) 503 504 #define MIPS_COP_0_TLB_PG_MASK _(5) 505 #define MIPS_COP_0_TLB_WIRED _(6) 506 507 #define MIPS_COP_0_COUNT _(9) 508 #define MIPS_COP_0_COMPARE _(11) 509 510 #define MIPS_COP_0_CONFIG _(16) 511 #define MIPS_COP_0_LLADDR _(17) 512 #define MIPS_COP_0_WATCH_LO _(18) 513 #define MIPS_COP_0_WATCH_HI _(19) 514 #define MIPS_COP_0_TLB_XCONTEXT _(20) 515 #define MIPS_COP_0_ECC _(26) 516 #define MIPS_COP_0_CACHE_ERR _(27) 517 #define MIPS_COP_0_TAG_LO _(28) 518 #define MIPS_COP_0_TAG_HI _(29) 519 #define MIPS_COP_0_ERROR_PC _(30) 520 521 /* MIPS32/64 */ 522 #define MIPS_COP_0_DEBUG _(23) 523 #define MIPS_COP_0_DEPC _(24) 524 #define MIPS_COP_0_PERFCNT _(25) 525 #define MIPS_COP_0_DATA_LO _(28) 526 #define MIPS_COP_0_DATA_HI _(29) 527 #define MIPS_COP_0_DESAVE _(31) 528 529 /* 530 * Values for the code field in a break instruction. 531 */ 532 #define MIPS_BREAK_INSTR 0x0000000d 533 #define MIPS_BREAK_VAL_MASK 0x03ff0000 534 #define MIPS_BREAK_VAL_SHIFT 16 535 #define MIPS_BREAK_KDB_VAL 512 536 #define MIPS_BREAK_SSTEP_VAL 513 537 #define MIPS_BREAK_BRKPT_VAL 514 538 #define MIPS_BREAK_SOVER_VAL 515 539 #define MIPS_BREAK_KDB (MIPS_BREAK_INSTR | \ 540 (MIPS_BREAK_KDB_VAL << MIPS_BREAK_VAL_SHIFT)) 541 #define MIPS_BREAK_SSTEP (MIPS_BREAK_INSTR | \ 542 (MIPS_BREAK_SSTEP_VAL << MIPS_BREAK_VAL_SHIFT)) 543 #define MIPS_BREAK_BRKPT (MIPS_BREAK_INSTR | \ 544 (MIPS_BREAK_BRKPT_VAL << MIPS_BREAK_VAL_SHIFT)) 545 #define MIPS_BREAK_SOVER (MIPS_BREAK_INSTR | \ 546 (MIPS_BREAK_SOVER_VAL << MIPS_BREAK_VAL_SHIFT)) 547 548 /* 549 * Mininum and maximum cache sizes. 550 */ 551 #define MIPS_MIN_CACHE_SIZE (16 * 1024) 552 #define MIPS_MAX_CACHE_SIZE (256 * 1024) 553 #define MIPS3_MAX_PCACHE_SIZE (32 * 1024) /* max. primary cache size */ 554 555 /* 556 * The floating point version and status registers. 557 */ 558 #define MIPS_FPU_ID $0 559 #define MIPS_FPU_CSR $31 560 561 /* 562 * The floating point coprocessor status register bits. 563 */ 564 #define MIPS_FPU_ROUNDING_BITS 0x00000003 565 #define MIPS_FPU_ROUND_RN 0x00000000 566 #define MIPS_FPU_ROUND_RZ 0x00000001 567 #define MIPS_FPU_ROUND_RP 0x00000002 568 #define MIPS_FPU_ROUND_RM 0x00000003 569 #define MIPS_FPU_STICKY_BITS 0x0000007c 570 #define MIPS_FPU_STICKY_INEXACT 0x00000004 571 #define MIPS_FPU_STICKY_UNDERFLOW 0x00000008 572 #define MIPS_FPU_STICKY_OVERFLOW 0x00000010 573 #define MIPS_FPU_STICKY_DIV0 0x00000020 574 #define MIPS_FPU_STICKY_INVALID 0x00000040 575 #define MIPS_FPU_ENABLE_BITS 0x00000f80 576 #define MIPS_FPU_ENABLE_INEXACT 0x00000080 577 #define MIPS_FPU_ENABLE_UNDERFLOW 0x00000100 578 #define MIPS_FPU_ENABLE_OVERFLOW 0x00000200 579 #define MIPS_FPU_ENABLE_DIV0 0x00000400 580 #define MIPS_FPU_ENABLE_INVALID 0x00000800 581 #define MIPS_FPU_EXCEPTION_BITS 0x0003f000 582 #define MIPS_FPU_EXCEPTION_INEXACT 0x00001000 583 #define MIPS_FPU_EXCEPTION_UNDERFLOW 0x00002000 584 #define MIPS_FPU_EXCEPTION_OVERFLOW 0x00004000 585 #define MIPS_FPU_EXCEPTION_DIV0 0x00008000 586 #define MIPS_FPU_EXCEPTION_INVALID 0x00010000 587 #define MIPS_FPU_EXCEPTION_UNIMPL 0x00020000 588 #define MIPS_FPU_COND_BIT 0x00800000 589 #define MIPS_FPU_FLUSH_BIT 0x01000000 /* r4k, MBZ on r3k */ 590 #define MIPS1_FPC_MBZ_BITS 0xff7c0000 591 #define MIPS3_FPC_MBZ_BITS 0xfe7c0000 592 593 594 /* 595 * Constants to determine if have a floating point instruction. 596 */ 597 #define MIPS_OPCODE_SHIFT 26 598 #define MIPS_OPCODE_C1 0x11 599 600 601 /* 602 * The low part of the TLB entry. 603 */ 604 #define MIPS1_TLB_PFN 0xfffff000 605 #define MIPS1_TLB_NON_CACHEABLE_BIT 0x00000800 606 #define MIPS1_TLB_DIRTY_BIT 0x00000400 607 #define MIPS1_TLB_VALID_BIT 0x00000200 608 #define MIPS1_TLB_GLOBAL_BIT 0x00000100 609 610 #define MIPS3_TLB_PFN 0x3fffffc0 611 #define MIPS3_TLB_ATTR_MASK 0x00000038 612 #define MIPS3_TLB_ATTR_SHIFT 3 613 #define MIPS3_TLB_DIRTY_BIT 0x00000004 614 #define MIPS3_TLB_VALID_BIT 0x00000002 615 #define MIPS3_TLB_GLOBAL_BIT 0x00000001 616 617 #define MIPS1_TLB_PHYS_PAGE_SHIFT 12 618 #define MIPS3_TLB_PHYS_PAGE_SHIFT 6 619 #define MIPS1_TLB_PF_NUM MIPS1_TLB_PFN 620 #define MIPS3_TLB_PF_NUM MIPS3_TLB_PFN 621 #define MIPS1_TLB_MOD_BIT MIPS1_TLB_DIRTY_BIT 622 #define MIPS3_TLB_MOD_BIT MIPS3_TLB_DIRTY_BIT 623 624 /* 625 * MIPS3_TLB_ATTR values - coherency algorithm: 626 * 0: cacheable, noncoherent, write-through, no write allocate 627 * 1: cacheable, noncoherent, write-through, write allocate 628 * 2: uncached 629 * 3: cacheable, noncoherent, write-back (noncoherent) 630 * 4: cacheable, coherent, write-back, exclusive (exclusive) 631 * 5: cacheable, coherent, write-back, exclusive on write (sharable) 632 * 6: cacheable, coherent, write-back, update on write (update) 633 * 7: uncached, accelerated (gather STORE operations) 634 */ 635 #define MIPS3_TLB_ATTR_WT 0 /* IDT */ 636 #define MIPS3_TLB_ATTR_WT_WRITEALLOCATE 1 /* IDT */ 637 #define MIPS3_TLB_ATTR_UNCACHED 2 /* R4000/R4400, IDT */ 638 #define MIPS3_TLB_ATTR_WB_NONCOHERENT 3 /* R4000/R4400, IDT */ 639 #define MIPS3_TLB_ATTR_WB_EXCLUSIVE 4 /* R4000/R4400 */ 640 #define MIPS3_TLB_ATTR_WB_SHARABLE 5 /* R4000/R4400 */ 641 #define MIPS3_TLB_ATTR_WB_UPDATE 6 /* R4000/R4400 */ 642 #define MIPS4_TLB_ATTR_UNCACHED_ACCELERATED 7 /* R10000 */ 643 644 645 /* 646 * The high part of the TLB entry. 647 */ 648 #define MIPS1_TLB_VPN 0xfffff000 649 #define MIPS1_TLB_PID 0x00000fc0 650 #define MIPS1_TLB_PID_SHIFT 6 651 652 #define MIPS3_TLB_VPN2 0xffffe000 653 #define MIPS3_TLB_ASID 0x000000ff 654 655 #define MIPS1_TLB_VIRT_PAGE_NUM MIPS1_TLB_VPN 656 #define MIPS3_TLB_VIRT_PAGE_NUM MIPS3_TLB_VPN2 657 #define MIPS3_TLB_PID MIPS3_TLB_ASID 658 #define MIPS_TLB_VIRT_PAGE_SHIFT 12 659 660 /* 661 * r3000: shift count to put the index in the right spot. 662 */ 663 #define MIPS1_TLB_INDEX_SHIFT 8 664 665 /* 666 * The first TLB that write random hits. 667 */ 668 #define MIPS1_TLB_FIRST_RAND_ENTRY 8 669 #define MIPS3_TLB_WIRED_UPAGES 1 670 671 /* 672 * The number of process id entries. 673 */ 674 #define MIPS1_TLB_NUM_PIDS 64 675 #define MIPS3_TLB_NUM_ASIDS 256 676 677 /* 678 * Patch codes to hide CPU design differences between MIPS1 and MIPS3. 679 */ 680 681 /* XXX simonb: this is before MIPS3_PLUS is defined (and is ugly!) */ 682 683 #if !(defined(MIPS3) || defined(MIPS4) || defined(MIPS32) || defined(MIPS64)) \ 684 && defined(MIPS1) /* XXX simonb must be neater! */ 685 #define MIPS_TLB_PID_SHIFT MIPS1_TLB_PID_SHIFT 686 #define MIPS_TLB_NUM_PIDS MIPS1_TLB_NUM_PIDS 687 #endif 688 689 #if (defined(MIPS3) || defined(MIPS4) || defined(MIPS32) || defined(MIPS64)) \ 690 && !defined(MIPS1) /* XXX simonb must be neater! */ 691 #define MIPS_TLB_PID_SHIFT 0 692 #define MIPS_TLB_NUM_PIDS MIPS3_TLB_NUM_ASIDS 693 #endif 694 695 696 #if !defined(MIPS_TLB_PID_SHIFT) 697 #define MIPS_TLB_PID_SHIFT \ 698 ((MIPS_HAS_R4K_MMU) ? 0 : MIPS1_TLB_PID_SHIFT) 699 700 #define MIPS_TLB_NUM_PIDS \ 701 ((MIPS_HAS_R4K_MMU) ? MIPS3_TLB_NUM_ASIDS : MIPS1_TLB_NUM_PIDS) 702 #endif 703 704 /* 705 * CPU processor revision IDs for company ID == 0 (non mips32/64 chips) 706 */ 707 #define MIPS_R2000 0x01 /* MIPS R2000 ISA I */ 708 #define MIPS_R3000 0x02 /* MIPS R3000 ISA I */ 709 #define MIPS_R6000 0x03 /* MIPS R6000 ISA II */ 710 #define MIPS_R4000 0x04 /* MIPS R4000/R4400 ISA III */ 711 #define MIPS_R3LSI 0x05 /* LSI Logic R3000 derivative ISA I */ 712 #define MIPS_R6000A 0x06 /* MIPS R6000A ISA II */ 713 #define MIPS_R3IDT 0x07 /* IDT R3041 or RC36100 ISA I */ 714 #define MIPS_R10000 0x09 /* MIPS R10000 ISA IV */ 715 #define MIPS_R4200 0x0a /* NEC VR4200 ISA III */ 716 #define MIPS_R4300 0x0b /* NEC VR4300 ISA III */ 717 #define MIPS_R4100 0x0c /* NEC VR4100 ISA III */ 718 #define MIPS_R12000 0x0e /* MIPS R12000 ISA IV */ 719 #define MIPS_R14000 0x0f /* MIPS R14000 ISA IV */ 720 #define MIPS_R8000 0x10 /* MIPS R8000 Blackbird/TFP ISA IV */ 721 #define MIPS_RC32300 0x18 /* IDT RC32334,332,355 ISA 32 */ 722 #define MIPS_R4600 0x20 /* QED R4600 Orion ISA III */ 723 #define MIPS_R4700 0x21 /* QED R4700 Orion ISA III */ 724 #define MIPS_R3SONY 0x21 /* Sony R3000 based ISA I */ 725 #define MIPS_R4650 0x22 /* QED R4650 ISA III */ 726 #define MIPS_TX3900 0x22 /* Toshiba TX39 family ISA I */ 727 #define MIPS_R5000 0x23 /* MIPS R5000 ISA IV */ 728 #define MIPS_R3NKK 0x23 /* NKK R3000 based ISA I */ 729 #define MIPS_RC32364 0x26 /* IDT RC32364 ISA 32 */ 730 #define MIPS_RM7000 0x27 /* QED RM7000 ISA IV */ 731 #define MIPS_RM5200 0x28 /* QED RM5200s ISA IV */ 732 #define MIPS_TX4900 0x2d /* Toshiba TX49 family ISA III */ 733 #define MIPS_R5900 0x2e /* Toshiba R5900 (EECore) ISA --- */ 734 #define MIPS_RC64470 0x30 /* IDT RC64474/RC64475 ISA III */ 735 #define MIPS_TX7900 0x38 /* Toshiba TX79 ISA III+*/ 736 #define MIPS_R5400 0x54 /* NEC VR5400 ISA IV */ 737 #define MIPS_R5500 0x55 /* NEC VR5500 ISA IV */ 738 739 /* 740 * CPU revision IDs for some prehistoric processors. 741 */ 742 743 /* For MIPS_R3000 */ 744 #define MIPS_REV_R2000A 0x16 /* R2000A uses R3000 proc revision */ 745 #define MIPS_REV_R3000 0x20 746 #define MIPS_REV_R3000A 0x30 747 748 /* For MIPS_TX3900 */ 749 #define MIPS_REV_TX3912 0x10 750 #define MIPS_REV_TX3922 0x30 751 #define MIPS_REV_TX3927 0x40 752 753 /* For MIPS_R4000 */ 754 #define MIPS_REV_R4000_A 0x00 755 #define MIPS_REV_R4000_B 0x22 756 #define MIPS_REV_R4000_C 0x30 757 #define MIPS_REV_R4400_A 0x40 758 #define MIPS_REV_R4400_B 0x50 759 #define MIPS_REV_R4400_C 0x60 760 761 /* For MIPS_TX4900 */ 762 #define MIPS_REV_TX4927 0x22 763 764 /* 765 * CPU processor revision IDs for company ID == 1 (MIPS) 766 */ 767 #define MIPS_4Kc 0x80 /* MIPS 4Kc ISA 32 */ 768 #define MIPS_5Kc 0x81 /* MIPS 5Kc ISA 64 */ 769 #define MIPS_20Kc 0x82 /* MIPS 20Kc ISA 64 */ 770 #define MIPS_4Kmp 0x83 /* MIPS 4Km/4Kp ISA 32 */ 771 #define MIPS_4KEc 0x84 /* MIPS 4KEc ISA 32 */ 772 #define MIPS_4KEmp 0x85 /* MIPS 4KEm/4KEp ISA 32 */ 773 #define MIPS_4KSc 0x86 /* MIPS 4KSc ISA 32 */ 774 #define MIPS_M4K 0x87 /* MIPS M4K ISA 32 Rel 2 */ 775 #define MIPS_25Kf 0x88 /* MIPS 25Kf ISA 64 */ 776 #define MIPS_5KE 0x89 /* MIPS 5KE ISA 64 Rel 2 */ 777 #define MIPS_4KEc_R2 0x90 /* MIPS 4KEc_R2 ISA 32 Rel 2 */ 778 #define MIPS_4KEmp_R2 0x91 /* MIPS 4KEm/4KEp_R2 ISA 32 Rel 2 */ 779 #define MIPS_4KSd 0x92 /* MIPS 4KSd ISA 32 Rel 2 */ 780 #define MIPS_24K 0x93 /* MIPS 24Kc/24Kf ISA 32 Rel 2 */ 781 #define MIPS_34K 0x95 /* MIPS 34K ISA 32 R2 MT */ 782 #define MIPS_24KE 0x96 /* MIPS 24KEc ISA 32 Rel 2 */ 783 #define MIPS_74K 0x97 /* MIPS 74Kc/74Kf ISA 32 Rel 2 */ 784 785 /* 786 * Alchemy (company ID 3) use the processor ID field to donote the CPU core 787 * revision and the company options field do donate the SOC chip type. 788 */ 789 /* CPU processor revision IDs */ 790 #define MIPS_AU_REV1 0x01 /* Alchemy Au1000 (Rev 1) ISA 32 */ 791 #define MIPS_AU_REV2 0x02 /* Alchemy Au1000 (Rev 2) ISA 32 */ 792 /* CPU company options IDs */ 793 #define MIPS_AU1000 0x00 794 #define MIPS_AU1500 0x01 795 #define MIPS_AU1100 0x02 796 #define MIPS_AU1550 0x03 797 798 /* 799 * CPU processor revision IDs for company ID == 4 (SiByte) 800 */ 801 #define MIPS_SB1 0x01 /* SiByte SB1 ISA 64 */ 802 803 /* 804 * CPU processor revision IDs for company ID == 5 (SandCraft) 805 */ 806 #define MIPS_SR7100 0x04 /* SandCraft SR7100 ISA 64 */ 807 808 /* 809 * FPU processor revision ID 810 */ 811 #define MIPS_SOFT 0x00 /* Software emulation ISA I */ 812 #define MIPS_R2360 0x01 /* MIPS R2360 FPC ISA I */ 813 #define MIPS_R2010 0x02 /* MIPS R2010 FPC ISA I */ 814 #define MIPS_R3010 0x03 /* MIPS R3010 FPC ISA I */ 815 #define MIPS_R6010 0x04 /* MIPS R6010 FPC ISA II */ 816 #define MIPS_R4010 0x05 /* MIPS R4010 FPC ISA II */ 817 #define MIPS_R31LSI 0x06 /* LSI Logic derivate ISA I */ 818 #define MIPS_R3TOSH 0x22 /* Toshiba R3000 based FPU ISA I */ 819 820 #ifdef ENABLE_MIPS_TX3900 821 #include <mips/r3900regs.h> 822 #endif 823 #ifdef MIPS3_5900 824 #include <mips/r5900regs.h> 825 #endif 826 #ifdef MIPS64_SB1 827 #include <mips/sb1regs.h> 828 #endif 829 830 #endif /* _MIPS_CPUREGS_H_ */ 831
Indexes created Tue Oct 28 12:10:06 GMT 2025