cpuregs.h revision 1.97
1 /* $NetBSD: cpuregs.h,v 1.97 2020/05/07 11:43:28 simonb Exp $ */ 2 3 /* 4 * Copyright (c) 2009 Miodrag Vallat. 5 * 6 * Permission to use, copy, modify, and distribute this software for any 7 * purpose with or without fee is hereby granted, provided that the above 8 * copyright notice and this permission notice appear in all copies. 9 * 10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 17 */ 18 19 /* 20 * Copyright (c) 1992, 1993 21 * The Regents of the University of California. All rights reserved. 22 * 23 * This code is derived from software contributed to Berkeley by 24 * Ralph Campbell and Rick Macklem. 25 * 26 * Redistribution and use in source and binary forms, with or without 27 * modification, are permitted provided that the following conditions 28 * are met: 29 * 1. Redistributions of source code must retain the above copyright 30 * notice, this list of conditions and the following disclaimer. 31 * 2. Redistributions in binary form must reproduce the above copyright 32 * notice, this list of conditions and the following disclaimer in the 33 * documentation and/or other materials provided with the distribution. 34 * 3. Neither the name of the University nor the names of its contributors 35 * may be used to endorse or promote products derived from this software 36 * without specific prior written permission. 37 * 38 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 39 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 40 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 41 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 42 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 43 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 44 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 45 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 46 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 47 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 48 * SUCH DAMAGE. 49 * 50 * @(#)machConst.h 8.1 (Berkeley) 6/10/93 51 * 52 * machConst.h -- 53 * 54 * Machine dependent constants. 55 * 56 * Copyright (C) 1989 Digital Equipment Corporation. 57 * Permission to use, copy, modify, and distribute this software and 58 * its documentation for any purpose and without fee is hereby granted, 59 * provided that the above copyright notice appears in all copies. 60 * Digital Equipment Corporation makes no representations about the 61 * suitability of this software for any purpose. It is provided "as is" 62 * without express or implied warranty. 63 * 64 * from: Header: /sprite/src/kernel/mach/ds3100.md/RCS/machConst.h, 65 * v 9.2 89/10/21 15:55:22 jhh Exp SPRITE (DECWRL) 66 * from: Header: /sprite/src/kernel/mach/ds3100.md/RCS/machAddrs.h, 67 * v 1.2 89/08/15 18:28:21 rab Exp SPRITE (DECWRL) 68 * from: Header: /sprite/src/kernel/vm/ds3100.md/RCS/vmPmaxConst.h, 69 * v 9.1 89/09/18 17:33:00 shirriff Exp SPRITE (DECWRL) 70 */ 71 72 #ifndef _MIPS_CPUREGS_H_ 73 #define _MIPS_CPUREGS_H_ 74 75 #include <sys/cdefs.h> /* For __CONCAT() */ 76 77 #if defined(_KERNEL_OPT) 78 #include "opt_cputype.h" 79 #endif 80 81 /* 82 * Address space. 83 * 32-bit mips CPUS partition their 32-bit address space into four segments: 84 * 85 * kuseg 0x00000000 - 0x7fffffff User virtual mem, mapped 86 * kseg0 0x80000000 - 0x9fffffff Physical memory, cached, unmapped 87 * kseg1 0xa0000000 - 0xbfffffff Physical memory, uncached, unmapped 88 * kseg2 0xc0000000 - 0xffffffff kernel-virtual, mapped 89 * 90 * mips1 physical memory is limited to 512Mbytes, which is 91 * doubly mapped in kseg0 (cached) and kseg1 (uncached.) 92 * Caching of mapped addresses is controlled by bits in the TLB entry. 93 */ 94 95 #ifdef _LP64 96 #define MIPS_XUSEG_START (0L << 62) 97 #define MIPS_XUSEG_P(x) (((uint64_t)(x) >> 62) == 0) 98 #define MIPS_USEG_P(x) ((uintptr_t)(x) < 0x80000000L) 99 #define MIPS_XSSEG_START (1L << 62) 100 #define MIPS_XSSEG_P(x) (((uint64_t)(x) >> 62) == 1) 101 #endif 102 103 /* 104 * MIPS addresses are signed and we defining as negative so that 105 * in LP64 kern they get sign-extended correctly. 106 */ 107 #ifndef _LOCORE 108 #define MIPS_KSEG0_START (-0x7fffffffL-1) /* 0x80000000 */ 109 #define MIPS_KSEG1_START -0x60000000L /* 0xa0000000 */ 110 #define MIPS_KSEG2_START -0x40000000L /* 0xc0000000 */ 111 #define MIPS_MAX_MEM_ADDR -0x42000000L /* 0xbe000000 */ 112 #define MIPS_RESERVED_ADDR -0x40380000L /* 0xbfc80000 */ 113 #endif 114 115 #define MIPS_PHYS_MASK 0x1fffffff 116 117 #define MIPS_KSEG0_TO_PHYS(x) ((uintptr_t)(x) & MIPS_PHYS_MASK) 118 #define MIPS_PHYS_TO_KSEG0(x) ((intptr_t)((x) + MIPS_KSEG0_START)) 119 #define MIPS_KSEG1_TO_PHYS(x) ((uintptr_t)(x) & MIPS_PHYS_MASK) 120 #define MIPS_PHYS_TO_KSEG1(x) ((intptr_t)(x) | (intptr_t)MIPS_KSEG1_START) 121 122 #define MIPS_KSEG0_P(x) (((intptr_t)(x) & ~MIPS_PHYS_MASK) == MIPS_KSEG0_START) 123 #define MIPS_KSEG1_P(x) (((intptr_t)(x) & ~MIPS_PHYS_MASK) == MIPS_KSEG1_START) 124 #define MIPS_KSEG2_P(x) ((uintptr_t)MIPS_KSEG2_START <= (uintptr_t)(x)) 125 126 /* Map virtual address to index in mips3 r4k virtually-indexed cache */ 127 #define MIPS3_VA_TO_CINDEX(x) \ 128 (((intptr_t)(x) & 0xffffff) | MIPS_KSEG0_START) 129 130 #ifndef _LOCORE 131 #define MIPS_XSEG_MASK (0x3fffffffffffffffLL) 132 #define MIPS_XKSEG_START (0x3ULL << 62) 133 #define MIPS_XKSEG_P(x) (((uint64_t)(x) >> 62) == 3) 134 135 #define MIPS_XKPHYS_START (0x2ULL << 62) 136 #define MIPS_PHYS_TO_XKPHYS_UNCACHED(x) \ 137 (MIPS_XKPHYS_START | ((uint64_t)(CCA_UNCACHED) << 59) | (x)) 138 #define MIPS_PHYS_TO_XKPHYS_ACC(x) \ 139 (MIPS_XKPHYS_START | ((uint64_t)(mips_options.mips3_cca_devmem) << 59) | (x)) 140 #define MIPS_PHYS_TO_XKPHYS_CACHED(x) \ 141 (mips_options.mips3_xkphys_cached | (x)) 142 #define MIPS_PHYS_TO_XKPHYS(cca,x) \ 143 (MIPS_XKPHYS_START | ((uint64_t)(cca) << 59) | (x)) 144 #define MIPS_XKPHYS_TO_PHYS(x) ((uint64_t)(x) & 0x07ffffffffffffffLL) 145 #define MIPS_XKPHYS_TO_CCA(x) (((uint64_t)(x) >> 59) & 7) 146 #define MIPS_XKPHYS_P(x) (((uint64_t)(x) >> 62) == 2) 147 #endif /* _LOCORE */ 148 149 #define CCA_UNCACHED 2 150 #define CCA_CACHEABLE 3 /* cacheable non-coherent */ 151 #define CCA_SB_CACHEABLE_COHERENT 5 /* cacheable coherent (SiByte ext) */ 152 #define CCA_ACCEL 7 /* non-cached, write combining */ 153 154 /* CPU dependent mtc0 hazard hook */ 155 #if (MIPS32R2 + MIPS64R2) > 0 156 # if (MIPS1 + MIPS3 + MIPS32 + MIPS64) == 0 157 # define COP0_SYNC sll $0,$0,3 /* EHB */ 158 # define JR_HB_RA .set push; .set mips32r2; jr.hb ra; nop; .set pop 159 # else 160 # define COP0_SYNC sll $0,$0,1; sll $0,$0,1; sll $0,$0,3 161 # define JR_HB_RA sll $0,$0,1; sll $0,$0,1; jr ra; sll $0,$0,3 162 # endif 163 #elif (MIPS32 + MIPS64) > 0 164 # define COP0_SYNC sll $0,$0,1; sll $0,$0,1; sll $0,$0,1 165 # define JR_HB_RA sll $0,$0,1; sll $0,$0,1; jr ra; sll $0,$0,1 166 #elif MIPS3 > 0 167 # define COP0_SYNC nop; nop; nop 168 # define JR_HB_RA nop; nop; jr ra; nop 169 #else 170 # define COP0_SYNC nop 171 # define JR_HB_RA jr ra; nop 172 #endif 173 #define COP0_HAZARD_FPUENABLE nop; nop; nop; nop; 174 175 /* 176 * The bits in the cause register. 177 * 178 * Bits common to r3000 and r4000: 179 * 180 * MIPS_CR_BR_DELAY Exception happened in branch delay slot. 181 * MIPS_CR_COP_ERR Coprocessor error. 182 * MIPS_CR_IP Interrupt pending bits defined below. 183 * (same meaning as in CAUSE register). 184 * MIPS_CR_EXC_CODE The exception type (see exception codes below). 185 * 186 * Differences: 187 * r3k has 4 bits of exception type, r4k has 5 bits. 188 */ 189 #define MIPS_CR_BR_DELAY 0x80000000 190 #define MIPS_CR_COP_ERR 0x30000000 191 #define MIPS1_CR_EXC_CODE 0x0000003C /* four bits */ 192 #define MIPS3_CR_EXC_CODE 0x0000007C /* five bits */ 193 #define MIPS_CR_IP 0x0000FF00 194 #define MIPS_CR_EXC_CODE_SHIFT 2 195 196 /* 197 * The bits in the status register. All bits are active when set to 1. 198 * 199 * R3000 status register fields: 200 * MIPS_SR_COP_USABILITY Control the usability of the four coprocessors. 201 * MIPS_SR_TS TLB shutdown. 202 * 203 * MIPS_SR_INT_IE Master (current) interrupt enable bit. 204 * 205 * Differences: 206 * r3k has cache control is via frobbing SR register bits, whereas the 207 * r4k cache control is via explicit instructions. 208 * r3k has a 3-entry stack of kernel/user bits, whereas the 209 * r4k has kernel/supervisor/user. 210 */ 211 #define MIPS_SR_COP_USABILITY 0xf0000000 212 #define MIPS_SR_COP_0_BIT 0x10000000 213 #define MIPS_SR_COP_1_BIT 0x20000000 214 #define MIPS_SR_COP_2_BIT 0x40000000 215 216 /* r4k and r3k differences, see below */ 217 218 #define MIPS_SR_MX 0x01000000 /* MIPS64 */ 219 #define MIPS_SR_PX 0x00800000 /* MIPS64 */ 220 #define MIPS_SR_BEV 0x00400000 /* Use boot exception vector */ 221 #define MIPS_SR_TS 0x00200000 222 223 /* r4k and r3k differences, see below */ 224 225 #define MIPS_SR_INT_IE 0x00000001 226 /*#define MIPS_SR_MBZ 0x0f8000c0*/ /* Never used, true for r3k */ 227 /*#define MIPS_SR_INT_MASK 0x0000ff00*/ 228 229 230 /* 231 * The R2000/R3000-specific status register bit definitions. 232 * all bits are active when set to 1. 233 * 234 * MIPS_SR_PARITY_ERR Parity error. 235 * MIPS_SR_CACHE_MISS Most recent D-cache load resulted in a miss. 236 * MIPS_SR_PARITY_ZERO Zero replaces outgoing parity bits. 237 * MIPS_SR_SWAP_CACHES Swap I-cache and D-cache. 238 * MIPS_SR_ISOL_CACHES Isolate D-cache from main memory. 239 * Interrupt enable bits defined below. 240 * MIPS_SR_KU_OLD Old kernel/user mode bit. 1 => user mode. 241 * MIPS_SR_INT_ENA_OLD Old interrupt enable bit. 242 * MIPS_SR_KU_PREV Previous kernel/user mode bit. 1 => user mode. 243 * MIPS_SR_INT_ENA_PREV Previous interrupt enable bit. 244 * MIPS_SR_KU_CUR Current kernel/user mode bit. 1 => user mode. 245 */ 246 247 #define MIPS1_PARITY_ERR 0x00100000 248 #define MIPS1_CACHE_MISS 0x00080000 249 #define MIPS1_PARITY_ZERO 0x00040000 250 #define MIPS1_SWAP_CACHES 0x00020000 251 #define MIPS1_ISOL_CACHES 0x00010000 252 253 #define MIPS1_SR_KU_OLD 0x00000020 /* 2nd stacked KU/IE*/ 254 #define MIPS1_SR_INT_ENA_OLD 0x00000010 /* 2nd stacked KU/IE*/ 255 #define MIPS1_SR_KU_PREV 0x00000008 /* 1st stacked KU/IE*/ 256 #define MIPS1_SR_INT_ENA_PREV 0x00000004 /* 1st stacked KU/IE*/ 257 #define MIPS1_SR_KU_CUR 0x00000002 /* current KU */ 258 259 /* backwards compatibility */ 260 #define MIPS_SR_PARITY_ERR MIPS1_PARITY_ERR 261 #define MIPS_SR_CACHE_MISS MIPS1_CACHE_MISS 262 #define MIPS_SR_PARITY_ZERO MIPS1_PARITY_ZERO 263 #define MIPS_SR_SWAP_CACHES MIPS1_SWAP_CACHES 264 #define MIPS_SR_ISOL_CACHES MIPS1_ISOL_CACHES 265 266 #define MIPS_SR_KU_OLD MIPS1_SR_KU_OLD 267 #define MIPS_SR_INT_ENA_OLD MIPS1_SR_INT_ENA_OLD 268 #define MIPS_SR_KU_PREV MIPS1_SR_KU_PREV 269 #define MIPS_SR_KU_CUR MIPS1_SR_KU_CUR 270 #define MIPS_SR_INT_ENA_PREV MIPS1_SR_INT_ENA_PREV 271 272 /* 273 * R4000 status register bit definitons, 274 * where different from r2000/r3000. 275 */ 276 #define MIPS3_SR_XX 0x80000000 277 #define MIPS3_SR_RP 0x08000000 278 #define MIPS3_SR_FR 0x04000000 279 #define MIPS3_SR_RE 0x02000000 280 281 #define MIPS3_SR_DIAG_DL 0x01000000 /* QED 52xx */ 282 #define MIPS3_SR_DIAG_IL 0x00800000 /* QED 52xx */ 283 #define MIPS3_SR_PX 0x00800000 /* MIPS64 */ 284 #define MIPS3_SR_SR 0x00100000 285 #define MIPS3_SR_NMI 0x00080000 /* MIPS32/64 */ 286 #define MIPS3_SR_DIAG_CH 0x00040000 287 #define MIPS3_SR_DIAG_CE 0x00020000 288 #define MIPS3_SR_DIAG_PE 0x00010000 289 #define MIPS3_SR_KX 0x00000080 290 #define MIPS3_SR_SX 0x00000040 291 #define MIPS3_SR_UX 0x00000020 292 #define MIPS3_SR_KSU_MASK 0x00000018 293 #define MIPS3_SR_KSU_USER 0x00000010 294 #define MIPS3_SR_KSU_SUPER 0x00000008 295 #define MIPS3_SR_KSU_KERNEL 0x00000000 296 #define MIPS3_SR_ERL 0x00000004 297 #define MIPS3_SR_EXL 0x00000002 298 299 #define MIPS_SR_SOFT_RESET MIPS3_SR_SOFT_RESET 300 #define MIPS_SR_DIAG_CH MIPS3_SR_DIAG_CH 301 #define MIPS_SR_DIAG_CE MIPS3_SR_DIAG_CE 302 #define MIPS_SR_DIAG_PE MIPS3_SR_DIAG_PE 303 #define MIPS_SR_KX MIPS3_SR_KX 304 #define MIPS_SR_SX MIPS3_SR_SX 305 #define MIPS_SR_UX MIPS3_SR_UX 306 307 #define MIPS_SR_KSU_MASK MIPS3_SR_KSU_MASK 308 #define MIPS_SR_KSU_USER MIPS3_SR_KSU_USER 309 #define MIPS_SR_KSU_SUPER MIPS3_SR_KSU_SUPER 310 #define MIPS_SR_KSU_KERNEL MIPS3_SR_KSU_KERNEL 311 #define MIPS_SR_ERL MIPS3_SR_ERL 312 #define MIPS_SR_EXL MIPS3_SR_EXL 313 314 315 /* 316 * The interrupt masks. 317 * If a bit in the mask is 1 then the interrupt is enabled (or pending). 318 */ 319 #define MIPS_INT_MASK 0xff00 320 #define MIPS_INT_MASK_5 0x8000 321 #define MIPS_INT_MASK_4 0x4000 322 #define MIPS_INT_MASK_3 0x2000 323 #define MIPS_INT_MASK_2 0x1000 324 #define MIPS_INT_MASK_1 0x0800 325 #define MIPS_INT_MASK_0 0x0400 326 #define MIPS_HARD_INT_MASK 0xfc00 327 #define MIPS_SOFT_INT_MASK_1 0x0200 328 #define MIPS_SOFT_INT_MASK_0 0x0100 329 #define MIPS_SOFT_INT_MASK 0x0300 330 #define MIPS_INT_MASK_SHIFT 8 331 332 /* 333 * mips3 CPUs have on-chip timer at INT_MASK_5. Each platform can 334 * choose to enable this interrupt. 335 */ 336 #if defined(MIPS3_ENABLE_CLOCK_INTR) 337 #define MIPS3_INT_MASK MIPS_INT_MASK 338 #define MIPS3_HARD_INT_MASK MIPS_HARD_INT_MASK 339 #else 340 #define MIPS3_INT_MASK (MIPS_INT_MASK & ~MIPS_INT_MASK_5) 341 #define MIPS3_HARD_INT_MASK (MIPS_HARD_INT_MASK & ~MIPS_INT_MASK_5) 342 #endif 343 344 /* 345 * The bits in the context register. 346 */ 347 #define MIPS1_CNTXT_PTE_BASE 0xFFE00000 348 #define MIPS1_CNTXT_BAD_VPN 0x001FFFFC 349 350 #define MIPS3_CNTXT_PTE_BASE 0xFF800000 351 #define MIPS3_CNTXT_BAD_VPN2 0x007FFFF0 352 353 /* 354 * The bits in the MIPS3 config register. 355 * 356 * bit 0..5: R/W, Bit 6..31: R/O 357 */ 358 359 /* kseg0 coherency algorithm - see MIPS3_TLB_ATTR values */ 360 #define MIPS3_CONFIG_K0_MASK 0x00000007 361 362 /* 363 * R/W Update on Store Conditional 364 * 0: Store Conditional uses coherency algorithm specified by TLB 365 * 1: Store Conditional uses cacheable coherent update on write 366 */ 367 #define MIPS3_CONFIG_CU 0x00000008 368 369 #define MIPS3_CONFIG_DB 0x00000010 /* Primary D-cache line size */ 370 #define MIPS3_CONFIG_IB 0x00000020 /* Primary I-cache line size */ 371 #define MIPS3_CONFIG_CACHE_L1_LSIZE(config, bit) \ 372 (((config) & (bit)) ? 32 : 16) 373 374 #define MIPS3_CONFIG_DC_MASK 0x000001c0 /* Primary D-cache size */ 375 #define MIPS3_CONFIG_DC_SHIFT 6 376 #define MIPS3_CONFIG_IC_MASK 0x00000e00 /* Primary I-cache size */ 377 #define MIPS3_CONFIG_IC_SHIFT 9 378 #define MIPS3_CONFIG_C_DEFBASE 0x1000 /* default base 2^12 */ 379 380 /* Cache size mode indication: available only on Vr41xx CPUs */ 381 #define MIPS3_CONFIG_CS 0x00001000 382 #define MIPS3_CONFIG_C_4100BASE 0x0400 /* base is 2^10 if CS=1 */ 383 #define MIPS3_CONFIG_CACHE_SIZE(config, mask, base, shift) \ 384 ((base) << (((config) & (mask)) >> (shift))) 385 386 /* External cache enable: Controls L2 for R5000/Rm527x and L3 for Rm7000 */ 387 #define MIPS3_CONFIG_SE 0x00001000 388 389 /* Block ordering: 0: sequential, 1: sub-block */ 390 #define MIPS3_CONFIG_EB 0x00002000 391 392 /* ECC mode - 0: ECC mode, 1: parity mode */ 393 #define MIPS3_CONFIG_EM 0x00004000 394 395 /* BigEndianMem - 0: kernel and memory are little endian, 1: big endian */ 396 #define MIPS3_CONFIG_BE 0x00008000 397 398 /* Dirty Shared coherency state - 0: enabled, 1: disabled */ 399 #define MIPS3_CONFIG_SM 0x00010000 400 401 /* Secondary Cache - 0: present, 1: not present */ 402 #define MIPS3_CONFIG_SC 0x00020000 403 404 /* System Port width - 0: 64-bit, 1: 32-bit (QED RM523x), 2,3: reserved */ 405 #define MIPS3_CONFIG_EW_MASK 0x000c0000 406 #define MIPS3_CONFIG_EW_SHIFT 18 407 408 /* Secondary Cache port width - 0: 128-bit data path to S-cache, 1: reserved */ 409 #define MIPS3_CONFIG_SW 0x00100000 410 411 /* Split Secondary Cache Mode - 0: I/D mixed, 1: I/D separated by SCAddr(17) */ 412 #define MIPS3_CONFIG_SS 0x00200000 413 414 /* Secondary Cache line size */ 415 #define MIPS3_CONFIG_SB_MASK 0x00c00000 416 #define MIPS3_CONFIG_SB_SHIFT 22 417 #define MIPS3_CONFIG_CACHE_L2_LSIZE(config) \ 418 (0x10 << (((config) & MIPS3_CONFIG_SB_MASK) >> MIPS3_CONFIG_SB_SHIFT)) 419 420 /* Write back data rate */ 421 #define MIPS3_CONFIG_EP_MASK 0x0f000000 422 #define MIPS3_CONFIG_EP_SHIFT 24 423 424 /* System clock ratio - this value is CPU dependent */ 425 #define MIPS3_CONFIG_EC_MASK 0x70000000 426 #define MIPS3_CONFIG_EC_SHIFT 28 427 428 /* Master-Checker Mode - 1: enabled */ 429 #define MIPS3_CONFIG_CM 0x80000000 430 431 /* 432 * The bits in the MIPS4 config register. 433 */ 434 435 /* kseg0 coherency algorithm - see MIPS3_TLB_ATTR values */ 436 #define MIPS4_CONFIG_K0_MASK MIPS3_CONFIG_K0_MASK 437 #define MIPS4_CONFIG_DN_MASK 0x00000018 /* Device number */ 438 #define MIPS4_CONFIG_CT 0x00000020 /* CohPrcReqTar */ 439 #define MIPS4_CONFIG_PE 0x00000040 /* PreElmReq */ 440 #define MIPS4_CONFIG_PM_MASK 0x00000180 /* PreReqMax */ 441 #define MIPS4_CONFIG_EC_MASK 0x00001e00 /* SysClkDiv */ 442 #define MIPS4_CONFIG_SB 0x00002000 /* SCBlkSize */ 443 #define MIPS4_CONFIG_SK 0x00004000 /* SCColEn */ 444 #define MIPS4_CONFIG_BE 0x00008000 /* MemEnd */ 445 #define MIPS4_CONFIG_SS_MASK 0x00070000 /* SCSize */ 446 #define MIPS4_CONFIG_SC_MASK 0x00380000 /* SCClkDiv */ 447 #define MIPS4_CONFIG_RESERVED 0x03c00000 /* Reserved wired 0 */ 448 #define MIPS4_CONFIG_DC_MASK 0x1c000000 /* Primary D-Cache size */ 449 #define MIPS4_CONFIG_IC_MASK 0xe0000000 /* Primary I-Cache size */ 450 451 #define MIPS4_CONFIG_DC_SHIFT 26 452 #define MIPS4_CONFIG_IC_SHIFT 29 453 454 #define MIPS4_CONFIG_CACHE_SIZE(config, mask, base, shift) \ 455 ((base) << (((config) & (mask)) >> (shift))) 456 457 #define MIPS4_CONFIG_CACHE_L2_LSIZE(config) \ 458 (((config) & MIPS4_CONFIG_SB) ? 128 : 64) 459 460 /* 461 * Location of exception vectors. 462 * 463 * Common vectors: reset and UTLB miss. 464 */ 465 #define MIPS_RESET_EXC_VEC MIPS_PHYS_TO_KSEG1(0x1FC00000) 466 #define MIPS_UTLB_MISS_EXC_VEC MIPS_PHYS_TO_KSEG0(0) 467 468 /* 469 * MIPS-1 general exception vector (everything else) 470 */ 471 #define MIPS1_GEN_EXC_VEC MIPS_PHYS_TO_KSEG0(0x0080) 472 473 /* 474 * MIPS-III exception vectors 475 */ 476 #define MIPS3_XTLB_MISS_EXC_VEC MIPS_PHYS_TO_KSEG0(0x0080) 477 #define MIPS3_CACHE_ERR_EXC_VEC MIPS_PHYS_TO_KSEG0(0x0100) 478 #define MIPS3_GEN_EXC_VEC MIPS_PHYS_TO_KSEG0(0x0180) 479 480 /* 481 * MIPS32/MIPS64 (and some MIPS3) dedicated interrupt vector. 482 */ 483 #define MIPS3_INTR_EXC_VEC MIPS_PHYS_TO_KSEG0(0x0200) 484 485 /* 486 * Coprocessor 0 registers: 487 * 488 * v--- width for mips I,III,32,64 489 * (3=32bit, 6=64bit, i=impl dep) 490 * 0 MIPS_COP_0_TLB_INDEX 3333 TLB Index. 491 * 1 MIPS_COP_0_TLB_RANDOM 3333 TLB Random. 492 * 2 MIPS_COP_0_TLB_LOW 3... r3k TLB entry low. 493 * 2 MIPS_COP_0_TLB_LO0 .636 r4k TLB entry low. 494 * 3 MIPS_COP_0_TLB_LO1 .636 r4k TLB entry low, extended. 495 * 4 MIPS_COP_0_TLB_CONTEXT 3636 TLB Context. 496 * 4/2 MIPS_COP_0_USERLOCAL ..36 UserLocal. 497 * 5 MIPS_COP_0_TLB_PG_MASK .333 TLB Page Mask register. 498 * 5/1 MIPS_COP_0_PG_GRAIN ..33 PageGrain register 499 * 6 MIPS_COP_0_TLB_WIRED .333 Wired TLB number. 500 * 7 MIPS_COP_0_HWRENA ..33 rdHWR Enable. 501 * 8 MIPS_COP_0_BAD_VADDR 3636 Bad virtual address. 502 * 9 MIPS_COP_0_COUNT .333 Count register. 503 * 10 MIPS_COP_0_TLB_HI 3636 TLB entry high. 504 * 11 MIPS_COP_0_COMPARE .333 Compare (against Count). 505 * 12 MIPS_COP_0_STATUS 3333 Status register. 506 * 12/1 MIPS_COP_0_INTCTL ..33 Interrupt Control. 507 * 12/2 MIPS_COP_0_SRSCTL ..33 Shadow Register Set Selectors. 508 * 12/3 MIPS_COP_0_SRSMAP ..33 Shadow Set Map. 509 * 13 MIPS_COP_0_CAUSE 3333 Exception cause register. 510 * 14 MIPS_COP_0_EXC_PC 3636 Exception PC. 511 * 15 MIPS_COP_0_PRID 3333 Processor revision identifier. 512 * 15/1 MIPS_COP_0_EBASE ..33 Exception Base. 513 * 16 MIPS_COP_0_CONFIG 3333 Configuration register. 514 * 16/1 MIPS_COP_0_CONFIG1 ..33 Configuration register 1. 515 * 16/2 MIPS_COP_0_CONFIG2 ..33 Configuration register 2. 516 * 16/3 MIPS_COP_0_CONFIG3 ..33 Configuration register 3. 517 * 16/4 MIPS_COP_0_CONFIG4 ..33 Configuration register 6. 518 * 16/5 MIPS_COP_0_CONFIG5 ..33 Configuration register 7. 519 * 16/6 MIPS_COP_0_CONFIG6 ..33 Configuration register 6. 520 * 16/7 MIPS_COP_0_CONFIG7 ..33 Configuration register 7. 521 * 17 MIPS_COP_0_LLADDR .336 Load Linked Address. 522 * 18 MIPS_COP_0_WATCH_LO .336 WatchLo register. 523 * 19 MIPS_COP_0_WATCH_HI .333 WatchHi register. 524 * 20 MIPS_COP_0_TLB_XCONTEXT .6.6 TLB XContext register. 525 * 22 MIPS_COP_0_OSSCRATCH ...6 [RMI] OS Scratch register. (select 0..7) 526 * 22 MIPS_COP_0_DIAG ...6 [LOONGSON2] Diagnostic register. 527 * 23 MIPS_COP_0_DEBUG .... Debug JTAG register. 528 * 24 MIPS_COP_0_DEPC .... DEPC JTAG register. 529 * 25 MIPS_COP_0_PERFCNT ..36 Performance Counter register. 530 * 26 MIPS_COP_0_ECC .3ii ECC / Error Control register. 531 * 27 MIPS_COP_0_CACHE_ERR .3ii Cache Error register. 532 * 28/0 MIPS_COP_0_TAG_LO .3ii Cache TagLo register (instr). 533 * 28/1 MIPS_COP_0_DATA_LO ..ii Cache DataLo register (instr). 534 * 28/2 MIPS_COP_0_TAG_LO ..ii Cache TagLo register (data). 535 * 28/3 MIPS_COP_0_DATA_LO ..ii Cache DataLo register (data). 536 * 29/0 MIPS_COP_0_TAG_HI .3ii Cache TagHi register (instr). 537 * 29/1 MIPS_COP_0_DATA_HI ..ii Cache DataHi register (instr). 538 * 29/2 MIPS_COP_0_TAG_HI ..ii Cache TagHi register (data). 539 * 29/3 MIPS_COP_0_DATA_HI ..ii Cache DataHi register (data). 540 * 30 MIPS_COP_0_ERROR_PC .636 Error EPC register. 541 * 31 MIPS_COP_0_DESAVE .... DESAVE JTAG register. 542 */ 543 #ifdef _LOCORE 544 #define _(n) __CONCAT($,n) 545 #else 546 #define _(n) n 547 #endif 548 #define MIPS_COP_0_TLB_INDEX _(0) 549 #define MIPS_COP_0_TLB_RANDOM _(1) 550 /* Name and meaning of TLB bits for $2 differ on r3k and r4k. */ 551 552 #define MIPS_COP_0_TLB_CONTEXT _(4) 553 /* $5 and $6 new with MIPS-III */ 554 #define MIPS_COP_0_BAD_VADDR _(8) 555 #define MIPS_COP_0_TLB_HI _(10) 556 #define MIPS_COP_0_STATUS _(12) 557 #define MIPS_COP_0_CAUSE _(13) 558 #define MIPS_COP_0_EXC_PC _(14) 559 #define MIPS_COP_0_PRID _(15) 560 561 562 /* MIPS-I */ 563 #define MIPS_COP_0_TLB_LOW _(2) 564 565 /* MIPS-III */ 566 #define MIPS_COP_0_TLB_LO0 _(2) 567 #define MIPS_COP_0_TLB_LO1 _(3) 568 569 #define MIPS_COP_0_TLB_PG_MASK _(5) 570 #define MIPS_COP_0_TLB_WIRED _(6) 571 572 #define MIPS_COP_0_COUNT _(9) 573 #define MIPS_COP_0_COMPARE _(11) 574 575 #define MIPS_COP_0_CONFIG _(16) 576 #define MIPS_COP_0_LLADDR _(17) 577 #define MIPS_COP_0_WATCH_LO _(18) 578 #define MIPS_COP_0_WATCH_HI _(19) 579 #define MIPS_COP_0_TLB_XCONTEXT _(20) 580 #define MIPS_COP_0_ECC _(26) 581 #define MIPS_COP_0_CACHE_ERR _(27) 582 #define MIPS_COP_0_TAG_LO _(28) 583 #define MIPS_COP_0_TAG_HI _(29) 584 #define MIPS_COP_0_ERROR_PC _(30) 585 586 /* MIPS32/64 */ 587 #define MIPS_COP_0_CONTEXT _(4) 588 #define MIPS_COP_0_CTXCONFIG _(4), 1 589 #define MIPS_COP_0_USERLOCAL _(4), 2 590 #define MIPS_COP_0_XCTXCONFIG _(4), 3 /* MIPS64 */ 591 #define MIPS_COP_0_PGGRAIN _(5), 1 592 #define MIPS_COP_0_SEGCTL0 _(5), 2 593 #define MIPS_COP_0_SEGCTL1 _(5), 3 594 #define MIPS_COP_0_SEGCTL2 _(5), 4 595 #define MIPS_COP_0_PWBASE _(5), 5 596 #define MIPS_COP_0_PWFIELD _(5), 6 597 #define MIPS_COP_0_PWSIZE _(5), 7 598 #define MIPS_COP_0_PWCTL _(6), 6 599 #define MIPS_COP_0_HWRENA _(7) 600 #define MIPS_COP_0_BADINSTR _(8), 1 601 #define MIPS_COP_0_BADINSTRP _(8), 2 602 #define MIPS_COP_0_INTCTL _(12), 1 603 #define MIPS_COP_0_SRSCTL _(12), 2 604 #define MIPS_COP_0_SRSMAP _(12), 3 605 #define MIPS_COP_0_NESTEDEXC _(13), 5 606 #define MIPS_COP_0_NESTED_EPC _(14), 2 607 #define MIPS_COP_0_EBASE _(15), 1 608 #define MIPS_COP_0_CDMMBASE _(15), 2 609 #define MIPS_COP_0_CMGCRBASE _(15), 3 610 #define MIPS_COP_0_CONFIG1 _(16), 1 611 #define MIPS_COP_0_CONFIG2 _(16), 2 612 #define MIPS_COP_0_CONFIG3 _(16), 3 613 #define MIPS_COP_0_CONFIG4 _(16), 4 614 #define MIPS_COP_0_CONFIG5 _(16), 5 615 #define MIPS_COP_0_OSSCRATCH _(22) /* RMI */ 616 #define MIPS_COP_0_DIAG _(22) 617 #define MIPS_COP_0_DEBUG _(23) 618 #define MIPS_COP_0_DEPC _(24) 619 #define MIPS_COP_0_PERFCNT _(25) 620 #define MIPS_COP_0_DATA_LO _(28) 621 #define MIPS_COP_0_DATA_HI _(29) 622 #define MIPS_COP_0_DESAVE _(31) 623 624 #define MIPS_DIAG_RAS_DISABLE 0x00000001 /* Loongson2 */ 625 #define MIPS_DIAG_BTB_CLEAR 0x00000002 /* Loongson2 */ 626 #define MIPS_DIAG_ITLB_CLEAR 0x00000004 /* Loongson2 */ 627 628 /* 629 * Values for the code field in a break instruction. 630 */ 631 #define MIPS_BREAK_INSTR 0x0000000d 632 #define MIPS_BREAK_VAL_MASK 0x03ff0000 633 #define MIPS_BREAK_VAL_SHIFT 16 634 #define MIPS_BREAK_KDB_VAL 512 635 #define MIPS_BREAK_SSTEP_VAL 513 636 #define MIPS_BREAK_BRKPT_VAL 514 637 #define MIPS_BREAK_SOVER_VAL 515 638 #define MIPS_BREAK_KDB (MIPS_BREAK_INSTR | \ 639 (MIPS_BREAK_KDB_VAL << MIPS_BREAK_VAL_SHIFT)) 640 #define MIPS_BREAK_SSTEP (MIPS_BREAK_INSTR | \ 641 (MIPS_BREAK_SSTEP_VAL << MIPS_BREAK_VAL_SHIFT)) 642 #define MIPS_BREAK_BRKPT (MIPS_BREAK_INSTR | \ 643 (MIPS_BREAK_BRKPT_VAL << MIPS_BREAK_VAL_SHIFT)) 644 #define MIPS_BREAK_SOVER (MIPS_BREAK_INSTR | \ 645 (MIPS_BREAK_SOVER_VAL << MIPS_BREAK_VAL_SHIFT)) 646 647 /* 648 * Mininum and maximum cache sizes. 649 */ 650 #define MIPS_MIN_CACHE_SIZE (16 * 1024) 651 #define MIPS_MAX_CACHE_SIZE (256 * 1024) 652 #define MIPS3_MAX_PCACHE_SIZE (32 * 1024) /* max. primary cache size */ 653 654 /* 655 * The floating point version and status registers. 656 */ 657 #define MIPS_FPU_ID $0 658 #define MIPS_FPU_CSR $31 659 660 /* 661 * The floating point coprocessor status register bits. 662 */ 663 #define MIPS_FPU_ROUNDING_BITS 0x00000003 664 #define MIPS_FPU_ROUND_RN 0x00000000 665 #define MIPS_FPU_ROUND_RZ 0x00000001 666 #define MIPS_FPU_ROUND_RP 0x00000002 667 #define MIPS_FPU_ROUND_RM 0x00000003 668 #define MIPS_FPU_STICKY_BITS 0x0000007c 669 #define MIPS_FPU_STICKY_INEXACT 0x00000004 670 #define MIPS_FPU_STICKY_UNDERFLOW 0x00000008 671 #define MIPS_FPU_STICKY_OVERFLOW 0x00000010 672 #define MIPS_FPU_STICKY_DIV0 0x00000020 673 #define MIPS_FPU_STICKY_INVALID 0x00000040 674 #define MIPS_FPU_ENABLE_BITS 0x00000f80 675 #define MIPS_FPU_ENABLE_INEXACT 0x00000080 676 #define MIPS_FPU_ENABLE_UNDERFLOW 0x00000100 677 #define MIPS_FPU_ENABLE_OVERFLOW 0x00000200 678 #define MIPS_FPU_ENABLE_DIV0 0x00000400 679 #define MIPS_FPU_ENABLE_INVALID 0x00000800 680 #define MIPS_FPU_EXCEPTION_BITS 0x0003f000 681 #define MIPS_FPU_EXCEPTION_INEXACT 0x00001000 682 #define MIPS_FPU_EXCEPTION_UNDERFLOW 0x00002000 683 #define MIPS_FPU_EXCEPTION_OVERFLOW 0x00004000 684 #define MIPS_FPU_EXCEPTION_DIV0 0x00008000 685 #define MIPS_FPU_EXCEPTION_INVALID 0x00010000 686 #define MIPS_FPU_EXCEPTION_UNIMPL 0x00020000 687 #define MIPS_FPU_COND_BIT 0x00800000 688 #define MIPS_FPU_FLUSH_BIT 0x01000000 /* r4k, MBZ on r3k */ 689 #define MIPS1_FPC_MBZ_BITS 0xff7c0000 690 #define MIPS3_FPC_MBZ_BITS 0xfe7c0000 691 692 693 /* 694 * Constants to determine if have a floating point instruction. 695 */ 696 #define MIPS_OPCODE_SHIFT 26 697 #define MIPS_OPCODE_C1 0x11 698 699 700 /* 701 * The low part of the TLB entry. 702 */ 703 #define MIPS1_TLB_PFN 0xfffff000 704 #define MIPS1_TLB_NON_CACHEABLE_BIT 0x00000800 705 #define MIPS1_TLB_DIRTY_BIT 0x00000400 706 #define MIPS1_TLB_VALID_BIT 0x00000200 707 #define MIPS1_TLB_GLOBAL_BIT 0x00000100 708 709 #define MIPS3_TLB_PFN 0x3fffffc0 710 #define MIPS3_TLB_ATTR_MASK 0x00000038 711 #define MIPS3_TLB_ATTR_SHIFT 3 712 #define MIPS3_TLB_DIRTY_BIT 0x00000004 713 #define MIPS3_TLB_VALID_BIT 0x00000002 714 #define MIPS3_TLB_GLOBAL_BIT 0x00000001 715 716 #define MIPS1_TLB_PHYS_PAGE_SHIFT 12 717 #define MIPS3_TLB_PHYS_PAGE_SHIFT 6 718 #define MIPS1_TLB_PF_NUM MIPS1_TLB_PFN 719 #define MIPS3_TLB_PF_NUM MIPS3_TLB_PFN 720 #define MIPS1_TLB_MOD_BIT MIPS1_TLB_DIRTY_BIT 721 #define MIPS3_TLB_MOD_BIT MIPS3_TLB_DIRTY_BIT 722 723 /* 724 * MIPS3_TLB_ATTR (CCA) values - coherency algorithm: 725 * 0: cacheable, noncoherent, write-through, no write allocate 726 * 1: cacheable, noncoherent, write-through, write allocate 727 * 2: uncached 728 * 3: cacheable, noncoherent, write-back (noncoherent) 729 * 4: cacheable, coherent, write-back, exclusive (exclusive) 730 * 5: cacheable, coherent, write-back, exclusive on write (sharable) 731 * 6: cacheable, coherent, write-back, update on write (update) 732 * 7: uncached, accelerated (gather STORE operations) 733 */ 734 #define MIPS3_TLB_ATTR_WT 0 /* IDT */ 735 #define MIPS3_TLB_ATTR_WT_WRITEALLOCATE 1 /* IDT */ 736 #define MIPS3_TLB_ATTR_UNCACHED 2 /* R4000/R4400, IDT */ 737 #define MIPS3_TLB_ATTR_WB_NONCOHERENT 3 /* R4000/R4400, IDT */ 738 #define MIPS3_TLB_ATTR_WB_EXCLUSIVE 4 /* R4000/R4400 */ 739 #define MIPS3_TLB_ATTR_WB_SHARABLE 5 /* R4000/R4400 */ 740 #define MIPS3_TLB_ATTR_WB_UPDATE 6 /* R4000/R4400 */ 741 #define MIPS4_TLB_ATTR_UNCACHED_ACCELERATED 7 /* R10000 */ 742 743 744 /* 745 * The high part of the TLB entry. 746 */ 747 #define MIPS1_TLB_VPN 0xfffff000 748 #define MIPS1_TLB_PID 0x00000fc0 749 #define MIPS1_TLB_PID_SHIFT 6 750 751 #define MIPS3_TLB_VPN2 0xffffe000 752 #define MIPS3_TLB_EHINV 0x00000400 /* mipsNN R3 */ 753 #define MIPS3_TLB_ASID 0x000000ff 754 755 #define MIPS1_TLB_VIRT_PAGE_NUM MIPS1_TLB_VPN 756 #define MIPS3_TLB_VIRT_PAGE_NUM MIPS3_TLB_VPN2 757 #define MIPS3_TLB_PID MIPS3_TLB_ASID 758 #define MIPS_TLB_VIRT_PAGE_SHIFT 12 759 760 /* 761 * r3000: shift count to put the index in the right spot. 762 */ 763 #define MIPS1_TLB_INDEX_SHIFT 8 764 765 /* 766 * The first TLB that write random hits. 767 */ 768 #define MIPS1_TLB_FIRST_RAND_ENTRY 8 769 #define MIPS3_TLB_WIRED_UPAGES 1 770 771 /* 772 * The number of process id entries. 773 */ 774 #define MIPS1_TLB_NUM_PIDS 64 775 #define MIPS3_TLB_NUM_ASIDS 256 776 777 /* 778 * Patch codes to hide CPU design differences between MIPS1 and MIPS3. 779 */ 780 781 /* XXX simonb: this is before MIPS3_PLUS is defined (and is ugly!) */ 782 783 #if (MIPS3 + MIPS4 + MIPS32 + MIPS32R2 + MIPS64 + MIPS64R2) == 0 && MIPS1 != 0 784 #define MIPS_TLB_PID_SHIFT MIPS1_TLB_PID_SHIFT 785 #define MIPS_TLB_PID MIPS1_TLB_PID 786 #define MIPS_TLB_NUM_PIDS MIPS1_TLB_NUM_PIDS 787 #endif 788 789 #if (MIPS3 + MIPS4 + MIPS32 + MIPS32R2 + MIPS64 + MIPS64R2) != 0 && MIPS1 == 0 790 #define MIPS_TLB_PID_SHIFT 0 791 #define MIPS_TLB_PID MIPS3_TLB_PID 792 #define MIPS_TLB_NUM_PIDS MIPS3_TLB_NUM_ASIDS 793 #endif 794 795 796 #if !defined(MIPS_TLB_PID_SHIFT) 797 #define MIPS_TLB_PID_SHIFT \ 798 ((MIPS_HAS_R4K_MMU) ? 0 : MIPS1_TLB_PID_SHIFT) 799 800 #define MIPS_TLB_PID \ 801 ((MIPS_HAS_R4K_MMU) ? MIPS3_TLB_PID : MIPS1_TLB_PID) 802 803 #define MIPS_TLB_NUM_PIDS \ 804 ((MIPS_HAS_R4K_MMU) ? MIPS3_TLB_NUM_ASIDS : MIPS1_TLB_NUM_PIDS) 805 #endif 806 807 /* 808 * Bits defined for HWREna (CP0 register 7, select 0). 809 */ 810 #define MIPS_HWRENA_IMPL31 __BIT(31) 811 #define MIPS_HWRENA_IMPL30 __BIT(30) 812 #define MIPS_HWRENA_UL __BIT(29) /* Userlocal */ 813 #define MIPS_HWRENA_CCRES __BIT(3) 814 #define MIPS_HWRENA_CC __BIT(2) 815 #define MIPS_HWRENA_SYNCI_STEP __BIT(1) 816 #define MIPS_HWRENA_CPUNUM __BIT(0) 817 818 /* 819 * Bits defined for EBASE (CP0 register 15, select 1). 820 */ 821 #define MIPS_EBASE_CPUNUM __BITS(9, 0) 822 823 /* 824 * Hints for the prefetch instruction 825 */ 826 827 /* 828 * Prefetched data is expected to be read (not modified) 829 */ 830 #define PREF_LOAD 0 831 #define PREF_LOAD_STREAMED 4 /* but not reused extensively; it */ 832 /* "streams" through cache. */ 833 #define PREF_LOAD_RETAINED 6 /* and reused extensively; it should */ 834 /* be "retained" in the cache. */ 835 836 /* 837 * Prefetched data is expected to be stored or modified 838 */ 839 #define PREF_STORE 1 840 #define PREF_STORE_STREAMED 5 /* but not reused extensively; it */ 841 /* "streams" through cache. */ 842 #define PREF_STORE_RETAINED 7 /* and reused extensively; it should */ 843 /* be "retained" in the cache. */ 844 845 /* 846 * data is no longer expected to be used. For a WB cache, schedule a 847 * writeback of any dirty data and afterwards free the cache lines. 848 */ 849 #define PREF_WB_INV 25 850 #define PREF_NUDGE PREF_WB_INV 851 852 /* 853 * Prepare for writing an entire cache line without the overhead 854 * involved in filling the line from memory. 855 */ 856 #define PREF_PREPAREFORSTORE 30 857 858 /* 859 * CPU processor revision IDs for company ID == 0 (non mips32/64 chips) 860 */ 861 #define MIPS_R2000 0x01 /* MIPS R2000 ISA I */ 862 #define MIPS_R3000 0x02 /* MIPS R3000 ISA I */ 863 #define MIPS_R6000 0x03 /* MIPS R6000 ISA II */ 864 #define MIPS_R4000 0x04 /* MIPS R4000/R4400 ISA III */ 865 #define MIPS_R3LSI 0x05 /* LSI Logic R3000 derivative ISA I */ 866 #define MIPS_R6000A 0x06 /* MIPS R6000A ISA II */ 867 #define MIPS_R3IDT 0x07 /* IDT R3041 or RC36100 ISA I */ 868 #define MIPS_R10000 0x09 /* MIPS R10000 ISA IV */ 869 #define MIPS_R4200 0x0a /* NEC VR4200 ISA III */ 870 #define MIPS_R4300 0x0b /* NEC VR4300 ISA III */ 871 #define MIPS_R4100 0x0c /* NEC VR4100 ISA III */ 872 #define MIPS_R12000 0x0e /* MIPS R12000 ISA IV */ 873 #define MIPS_R14000 0x0f /* MIPS R14000 ISA IV */ 874 #define MIPS_R8000 0x10 /* MIPS R8000 Blackbird/TFP ISA IV */ 875 #define MIPS_RC32300 0x18 /* IDT RC32334,332,355 ISA 32 */ 876 #define MIPS_R4600 0x20 /* QED R4600 Orion ISA III */ 877 #define MIPS_R4700 0x21 /* QED R4700 Orion ISA III */ 878 #define MIPS_R3SONY 0x21 /* Sony R3000 based ISA I */ 879 #define MIPS_R4650 0x22 /* QED R4650 ISA III */ 880 #define MIPS_TX3900 0x22 /* Toshiba TX39 family ISA I */ 881 #define MIPS_R5000 0x23 /* MIPS R5000 ISA IV */ 882 #define MIPS_R3NKK 0x23 /* NKK R3000 based ISA I */ 883 #define MIPS_RC32364 0x26 /* IDT RC32364 ISA 32 */ 884 #define MIPS_RM7000 0x27 /* QED RM7000 ISA IV */ 885 #define MIPS_RM5200 0x28 /* QED RM5200s ISA IV */ 886 #define MIPS_TX4900 0x2d /* Toshiba TX49 family ISA III */ 887 #define MIPS_R5900 0x2e /* Toshiba R5900 (EECore) ISA --- */ 888 #define MIPS_RC64470 0x30 /* IDT RC64474/RC64475 ISA III */ 889 #define MIPS_TX7900 0x38 /* Toshiba TX79 ISA III+*/ 890 #define MIPS_R5400 0x54 /* NEC VR5400 ISA IV */ 891 #define MIPS_R5500 0x55 /* NEC VR5500 ISA IV */ 892 #define MIPS_LOONGSON2 0x63 /* ICT Loongson-2 ISA III */ 893 894 /* 895 * CPU revision IDs for some prehistoric processors. 896 */ 897 898 /* For MIPS_R3000 */ 899 #define MIPS_REV_R2000A 0x16 /* R2000A uses R3000 proc revision */ 900 #define MIPS_REV_R3000 0x20 901 #define MIPS_REV_R3000A 0x30 902 903 /* For MIPS_TX3900 */ 904 #define MIPS_REV_TX3912 0x10 905 #define MIPS_REV_TX3922 0x30 906 #define MIPS_REV_TX3927 0x40 907 908 /* For MIPS_R4000 */ 909 #define MIPS_REV_R4000_A 0x00 910 #define MIPS_REV_R4000_B 0x22 911 #define MIPS_REV_R4000_C 0x30 912 #define MIPS_REV_R4400_A 0x40 913 #define MIPS_REV_R4400_B 0x50 914 #define MIPS_REV_R4400_C 0x60 915 916 /* For MIPS_TX4900 */ 917 #define MIPS_REV_TX4927 0x22 918 919 /* For MIPS_LOONGSON2 */ 920 #define MIPS_REV_LOONGSON2E 0x02 921 #define MIPS_REV_LOONGSON2F 0x03 922 923 /* 924 * CPU processor revision IDs for company ID == 1 (MIPS) 925 */ 926 #define MIPS_4Kc 0x80 /* MIPS 4Kc ISA 32 */ 927 #define MIPS_5Kc 0x81 /* MIPS 5Kc ISA 64 */ 928 #define MIPS_20Kc 0x82 /* MIPS 20Kc ISA 64 */ 929 #define MIPS_4Kmp 0x83 /* MIPS 4Km/4Kp ISA 32 */ 930 #define MIPS_4KEc 0x84 /* MIPS 4KEc ISA 32 */ 931 #define MIPS_4KEmp 0x85 /* MIPS 4KEm/4KEp ISA 32 */ 932 #define MIPS_4KSc 0x86 /* MIPS 4KSc ISA 32 */ 933 #define MIPS_M4K 0x87 /* MIPS M4K ISA 32 Rel 2 */ 934 #define MIPS_25Kf 0x88 /* MIPS 25Kf ISA 64 */ 935 #define MIPS_5KE 0x89 /* MIPS 5KE ISA 64 Rel 2 */ 936 #define MIPS_4KEc_R2 0x90 /* MIPS 4KEc_R2 ISA 32 Rel 2 */ 937 #define MIPS_4KEmp_R2 0x91 /* MIPS 4KEm/4KEp_R2 ISA 32 Rel 2 */ 938 #define MIPS_4KSd 0x92 /* MIPS 4KSd ISA 32 Rel 2 */ 939 #define MIPS_24K 0x93 /* MIPS 24Kc/24Kf ISA 32 Rel 2 */ 940 #define MIPS_34K 0x95 /* MIPS 34K ISA 32 R2 MT */ 941 #define MIPS_24KE 0x96 /* MIPS 24KEc ISA 32 Rel 2 */ 942 #define MIPS_74K 0x97 /* MIPS 74Kc/74Kf ISA 32 Rel 2 */ 943 #define MIPS_1004K 0x99 /* MIPS 1004Kc/1004Kf ISA 32 Rel 2 */ 944 #define MIPS_1074K 0x9a /* MIPS 1074Kc/1074Kf ISA 32 Rel 2 */ 945 #define MIPS_interAptiv 0xa1 /* MIPS interAptiv ISA 32 R3 MT */ 946 947 /* 948 * CPU processor revision IDs for company ID == 2 (Broadcom) 949 */ 950 #define MIPS_BCM3302 0x90 /* MIPS 4KEc_R2-like? ISA 32 Rel 2 */ 951 952 /* 953 * Alchemy (company ID 3) use the processor ID field to donote the CPU core 954 * revision and the company options field do donate the SOC chip type. 955 */ 956 /* CPU processor revision IDs */ 957 #define MIPS_AU_REV1 0x01 /* Alchemy Au1000 (Rev 1) ISA 32 */ 958 #define MIPS_AU_REV2 0x02 /* Alchemy Au1000 (Rev 2) ISA 32 */ 959 /* CPU company options IDs */ 960 #define MIPS_AU1000 0x00 961 #define MIPS_AU1500 0x01 962 #define MIPS_AU1100 0x02 963 #define MIPS_AU1550 0x03 964 965 /* 966 * CPU processor revision IDs for company ID == 4 (SiByte) 967 */ 968 #define MIPS_SB1 0x01 /* SiByte SB1 ISA 64 */ 969 #define MIPS_SB1_11 0x11 /* SiByte SB1 (rev 0x11) ISA 64 */ 970 971 /* 972 * CPU processor revision IDs for company ID == 5 (SandCraft) 973 */ 974 #define MIPS_SR7100 0x04 /* SandCraft SR7100 ISA 64 */ 975 976 /* 977 * CPU revision IDs for company ID == 12 (RMI) 978 * note: unlisted Rev values may indicate pre-production silicon 979 */ 980 #define MIPS_XLR_B2 0x04 /* RMI XLR Production Rev B2 */ 981 #define MIPS_XLR_C4 0x91 /* RMI XLR Production Rev C4 */ 982 983 /* 984 * CPU processor IDs for company ID == 12 (RMI) 985 */ 986 #define MIPS_XLR308B 0x06 /* RMI XLR308-B ISA 64 */ 987 #define MIPS_XLR508B 0x07 /* RMI XLR508-B ISA 64 */ 988 #define MIPS_XLR516B 0x08 /* RMI XLR516-B ISA 64 */ 989 #define MIPS_XLR532B 0x09 /* RMI XLR532-B ISA 64 */ 990 #define MIPS_XLR716B 0x0a /* RMI XLR716-B ISA 64 */ 991 #define MIPS_XLR732B 0x0b /* RMI XLR732-B ISA 64 */ 992 #define MIPS_XLR732C 0x00 /* RMI XLR732-C ISA 64 */ 993 #define MIPS_XLR716C 0x02 /* RMI XLR716-C ISA 64 */ 994 #define MIPS_XLR532C 0x08 /* RMI XLR532-C ISA 64 */ 995 #define MIPS_XLR516C 0x0a /* RMI XLR516-C ISA 64 */ 996 #define MIPS_XLR508C 0x0b /* RMI XLR508-C ISA 64 */ 997 #define MIPS_XLR308C 0x0f /* RMI XLR308-C ISA 64 */ 998 #define MIPS_XLS616 0x40 /* RMI XLS616 ISA 64 */ 999 #define MIPS_XLS416 0x44 /* RMI XLS416 ISA 64 */ 1000 #define MIPS_XLS608 0x4A /* RMI XLS608 ISA 64 */ 1001 #define MIPS_XLS408 0x4E /* RMI XLS406 ISA 64 */ 1002 #define MIPS_XLS404 0x4F /* RMI XLS404 ISA 64 */ 1003 #define MIPS_XLS408LITE 0x88 /* RMI XLS408-Lite ISA 64 */ 1004 #define MIPS_XLS404LITE 0x8C /* RMI XLS404-Lite ISA 64 */ 1005 #define MIPS_XLS208 0x8E /* RMI XLS208 ISA 64 */ 1006 #define MIPS_XLS204 0x8F /* RMI XLS204 ISA 64 */ 1007 #define MIPS_XLS108 0xCE /* RMI XLS108 ISA 64 */ 1008 #define MIPS_XLS104 0xCF /* RMI XLS104 ISA 64 */ 1009 1010 /* 1011 * CPU processor IDs for company ID == 13 (Cavium) 1012 */ 1013 #define MIPS_CN38XX 0x00 /* Cavium Octeon CN38XX ISA 64 */ 1014 #define MIPS_CN31XX 0x01 /* Cavium Octeon CN31XX ISA 64 */ 1015 #define MIPS_CN30XX 0x02 /* Cavium Octeon CN30XX ISA 64 */ 1016 #define MIPS_CN58XX 0x03 /* Cavium Octeon CN58XX ISA 64 */ 1017 #define MIPS_CN56XX 0x04 /* Cavium Octeon CN56XX ISA 64 */ 1018 #define MIPS_CN50XX 0x06 /* Cavium Octeon CN50XX ISA 64 */ 1019 #define MIPS_CN52XX 0x07 /* Cavium Octeon CN52XX ISA 64 */ 1020 #define MIPS_CN63XX 0x90 /* Cavium Octeon CN63XX ISA 64 */ 1021 #define MIPS_CN68XX 0x91 /* Cavium Octeon CN68XX ISA 64 */ 1022 #define MIPS_CN66XX 0x92 /* Cavium Octeon CN66XX ISA 64 */ 1023 #define MIPS_CN61XX 0x93 /* Cavium Octeon CN61XX ISA 64 */ 1024 #define MIPS_CNF71XX 0x94 /* Cavium Octeon CNF71XX ISA 64 */ 1025 #define MIPS_CN78XX 0x95 /* Cavium Octeon CN78XX ISA 64 */ 1026 #define MIPS_CN70XX 0x96 /* Cavium Octeon CN70XX ISA 64 */ 1027 1028 /* 1029 * CPU processor revision IDs for company ID == 7 (Microsoft) 1030 */ 1031 #define MIPS_eMIPS 0x04 /* MSR's eMIPS */ 1032 1033 /* 1034 * CPU processor revision IDs for company ID == e1 (Ingenic) 1035 */ 1036 #define MIPS_XBURST 0x02 /* Ingenic XBurst */ 1037 1038 /* 1039 * FPU processor revision ID 1040 */ 1041 #define MIPS_SOFT 0x00 /* Software emulation ISA I */ 1042 #define MIPS_R2360 0x01 /* MIPS R2360 FPC ISA I */ 1043 #define MIPS_R2010 0x02 /* MIPS R2010 FPC ISA I */ 1044 #define MIPS_R3010 0x03 /* MIPS R3010 FPC ISA I */ 1045 #define MIPS_R6010 0x04 /* MIPS R6010 FPC ISA II */ 1046 #define MIPS_R4010 0x05 /* MIPS R4010 FPC ISA II */ 1047 #define MIPS_R31LSI 0x06 /* LSI Logic derivate ISA I */ 1048 #define MIPS_R3TOSH 0x22 /* Toshiba R3000 based FPU ISA I */ 1049 1050 #ifdef ENABLE_MIPS_TX3900 1051 #include <mips/r3900regs.h> 1052 #endif 1053 #ifdef MIPS64_SB1 1054 #include <mips/sb1regs.h> 1055 #endif 1056 #if defined(MIPS64_XLP) || defined(MIPS64_XLR) || defined(MIPS64_XLS) 1057 #include <mips/rmi/rmixlreg.h> 1058 #endif 1059 1060 #ifdef MIPS3_LOONGSON2 1061 /* 1062 * Loongson 2E/2F specific defines 1063 */ 1064 1065 /* 1066 * Address Window registers physical addresses 1067 * 1068 * The Loongson 2F processor has an AXI crossbar with four possible bus 1069 * masters, each one having four programmable address windows. 1070 * 1071 * Each window is defined with three 64-bit registers: 1072 * - a base address register, defining the address in the master address 1073 * space (base register). 1074 * - an address mask register, defining which address bits are valid in this 1075 * window. A given address matches a window if (addr & mask) == base. 1076 * - the location of the window base in the target, as well at the target 1077 * number itself (mmap register). The lower 20 bits of the address are 1078 * forced as zeroes regardless of their value in this register. 1079 * The translated address is thus (addr & ~mask) | (mmap & ~0xfffff). 1080 */ 1081 1082 #define LOONGSON_AWR_BASE_ADDRESS 0x3ff00000ULL 1083 1084 #define LOONGSON_AWR_BASE(master, window) \ 1085 (LOONGSON_AWR_BASE_ADDRESS + (window) * 0x08 + (master) * 0x60 + 0x00) 1086 #define LOONGSON_AWR_SIZE(master, window) \ 1087 (LOONGSON_AWR_BASE_ADDRESS + (window) * 0x08 + (master) * 0x60 + 0x20) 1088 #define LOONGSON_AWR_MMAP(master, window) \ 1089 (LOONGSON_AWR_BASE_ADDRESS + (window) * 0x08 + (master) * 0x60 + 0x40) 1090 1091 /* 1092 * Bits in the diagnostic register 1093 */ 1094 1095 #define COP_0_DIAG_ITLB_CLEAR 0x04 1096 #define COP_0_DIAG_BTB_CLEAR 0x02 1097 #define COP_0_DIAG_RAS_DISABLE 0x01 1098 1099 #endif /* MIPS3_LOONGSON2 */ 1100 1101 #endif /* _MIPS_CPUREGS_H_ */ 1102
Indexes created Wed Oct 29 20:09:47 GMT 2025