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intr.h revision 1.4 
      1 /* $NetBSD: intr.h,v 1.4 2011/02/20 07:45:47 matt Exp $ */
      2 /*-
      3  * Copyright (c) 2009, 2010 The NetBSD Foundation, Inc.
      4  * All rights reserved.
      5  *
      6  * This code is derived from software contributed to The NetBSD Foundation
      7  * by Matt Thomas <matt (at) 3am-software.com>.
      8  *
      9  * Redistribution and use in source and binary forms, with or without
     10  * modification, are permitted provided that the following conditions
     11  * are met:
     12  * 1. Redistributions of source code must retain the above copyright
     13  *    notice, this list of conditions and the following disclaimer.
     14  * 2. Redistributions in binary form must reproduce the above copyright
     15  *    notice, this list of conditions and the following disclaimer in the
     16  *    documentation and/or other materials provided with the distribution.
     17  *
     18  * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
     19  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
     20  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
     21  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
     22  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
     23  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
     24  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
     25  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
     26  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
     27  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
     28  * POSSIBILITY OF SUCH DAMAGE.
     29  */
     30 
     31 #ifndef _MIPS_INTR_H_
     32 #define	_MIPS_INTR_H_
     33 
     34 #ifdef _KERNEL_OPT
     35 #include "opt_multiprocessor.h"
     36 #endif
     37 
     38 /*
     39  * This is a common <machine/intr.h> for all MIPS platforms.
     40  */
     41 
     42 #define	IPL_NONE	0
     43 #define	IPL_SOFTCLOCK	(IPL_NONE+1)
     44 #define	IPL_SOFTBIO	(IPL_SOFTCLOCK)	/* shares SWINT with softclock */
     45 #define	IPL_SOFTNET	(IPL_SOFTBIO+1)
     46 #define	IPL_SOFTSERIAL	(IPL_SOFTNET)	/* shares SWINT with softnet */
     47 #define	IPL_VM		(IPL_SOFTSERIAL+1)
     48 #define	IPL_SCHED	(IPL_VM+1)
     49 #define	IPL_DDB		(IPL_SCHED+1)
     50 #define	IPL_HIGH	(IPL_DDB+1)
     51 
     52 #define	_IPL_N		(IPL_HIGH+1)
     53 #define	_IPL_NAMES(pfx)	{ pfx"none", pfx"softclock/bio", pfx"softnet/serial", \
     54 			  pfx"vm", pfx"sched", pfx"ddb", pfx"high" }
     55 
     56 #define	IST_UNUSABLE	-1		/* interrupt cannot be used */
     57 #define	IST_NONE	0		/* none (dummy) */
     58 #define	IST_PULSE	1		/* pulsed */
     59 #define	IST_EDGE	2		/* edge-triggered */
     60 #define	IST_LEVEL	3		/* level-triggered */
     61 #define	IST_LEVEL_HIGH	4		/* level triggered, active high */
     62 #define	IST_LEVEL_LOW	5		/* level triggered, active low */
     63 
     64 #define	IPI_NOP		0		/* do nothing, interrupt only */
     65 #define	IPI_AST		1		/* force ast */
     66 #define	IPI_SHOOTDOWN	2		/* do a tlb shootdown */
     67 #define	IPI_SYNCICACHE	3		/* sync icache for pages */
     68 #define	IPI_KPREEMPT	4		/* schedule a kernel preemption */
     69 #define	IPI_SUSPEND	5		/* DDB suspend signaling */
     70 #define	IPI_HALT	6		/* halt cpu */
     71 #define	NIPIS		7
     72 
     73 #ifdef __INTR_PRIVATE
     74 struct splsw {
     75 	int	(*splsw_splhigh)(void);
     76 	int	(*splsw_splsched)(void);
     77 	int	(*splsw_splvm)(void);
     78 	int	(*splsw_splsoftserial)(void);
     79 	int	(*splsw_splsoftnet)(void);
     80 	int	(*splsw_splsoftbio)(void);
     81 	int	(*splsw_splsoftclock)(void);
     82 	int	(*splsw_splraise)(int);
     83 	void	(*splsw_spl0)(void);
     84 	void	(*splsw_splx)(int);
     85 	int	(*splsw_splhigh_noprof)(void);
     86 	void	(*splsw_splx_noprof)(int);
     87 	void	(*splsw__setsoftintr)(uint32_t);
     88 	void	(*splsw__clrsoftintr)(uint32_t);
     89 	int	(*splsw_splintr)(uint32_t *);
     90 	void	(*splsw_splcheck)(void);
     91 };
     92 
     93 struct ipl_sr_map {
     94 	uint32_t sr_bits[_IPL_N];
     95 };
     96 #else
     97 struct splsw;
     98 #endif /* __INTR_PRIVATE */
     99 
    100 typedef int ipl_t;
    101 typedef struct {
    102         ipl_t _spl;
    103 } ipl_cookie_t;
    104 
    105 #ifdef _KERNEL
    106 
    107 #if defined(MULTIPROCESSOR) && defined(__HAVE_FAST_SOFTINTS)
    108 #define __HAVE_PREEMPTION	1
    109 #define SOFTINT_KPREEMPT	(SOFTINT_COUNT+0)
    110 #endif
    111 
    112 #ifdef __INTR_PRIVATE
    113 extern	struct splsw	mips_splsw;
    114 extern	struct ipl_sr_map ipl_sr_map;
    115 #endif /* __INTR_PRIVATE */
    116 
    117 int	splhigh(void);
    118 int	splhigh_noprof(void);
    119 int	splsched(void);
    120 int	splvm(void);
    121 int	splsoftserial(void);
    122 int	splsoftnet(void);
    123 int	splsoftbio(void);
    124 int	splsoftclock(void);
    125 int	splraise(int);
    126 void	splx(int);
    127 void	splx_noprof(int);
    128 void	spl0(void);
    129 int	splintr(uint32_t *);
    130 void	_setsoftintr(uint32_t);
    131 void	_clrsoftintr(uint32_t);
    132 
    133 struct cpu_info;
    134 
    135 void	ipi_init(struct cpu_info *);
    136 void	ipi_process(struct cpu_info *, uint64_t);
    137 
    138 /*
    139  * These make no sense *NOT* to be inlined.
    140  */
    141 static inline ipl_cookie_t
    142 makeiplcookie(ipl_t s)
    143 {
    144 	return (ipl_cookie_t){._spl = s};
    145 }
    146 
    147 static inline int
    148 splraiseipl(ipl_cookie_t icookie)
    149 {
    150 	return splraise(icookie._spl);
    151 }
    152 
    153 #endif /* _KERNEL */
    154 #endif /* _MIPS_INTR_H_ */
    155