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intr.h revision 1.9 
      1 /* $NetBSD: intr.h,v 1.9 2015/06/01 22:55:12 matt Exp $ */
      2 
      3 /*-
      4  * Copyright (c) 2009, 2010 The NetBSD Foundation, Inc.
      5  * All rights reserved.
      6  *
      7  * This code is derived from software contributed to The NetBSD Foundation
      8  * by Matt Thomas <matt (at) 3am-software.com>.
      9  *
     10  * Redistribution and use in source and binary forms, with or without
     11  * modification, are permitted provided that the following conditions
     12  * are met:
     13  * 1. Redistributions of source code must retain the above copyright
     14  *    notice, this list of conditions and the following disclaimer.
     15  * 2. Redistributions in binary form must reproduce the above copyright
     16  *    notice, this list of conditions and the following disclaimer in the
     17  *    documentation and/or other materials provided with the distribution.
     18  *
     19  * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
     20  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
     21  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
     22  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
     23  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
     24  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
     25  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
     26  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
     27  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
     28  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
     29  * POSSIBILITY OF SUCH DAMAGE.
     30  */
     31 
     32 #ifndef _MIPS_INTR_H_
     33 #define	_MIPS_INTR_H_
     34 
     35 #ifdef _KERNEL_OPT
     36 #include "opt_multiprocessor.h"
     37 #endif
     38 
     39 /*
     40  * This is a common <machine/intr.h> for all MIPS platforms.
     41  */
     42 
     43 #define	IPL_NONE	0
     44 #define	IPL_SOFTCLOCK	(IPL_NONE+1)
     45 #define	IPL_SOFTBIO	(IPL_SOFTCLOCK)	/* shares SWINT with softclock */
     46 #define	IPL_SOFTNET	(IPL_SOFTBIO+1)
     47 #define	IPL_SOFTSERIAL	(IPL_SOFTNET)	/* shares SWINT with softnet */
     48 #define	IPL_VM		(IPL_SOFTSERIAL+1)
     49 #define	IPL_SCHED	(IPL_VM+1)
     50 #define	IPL_DDB		(IPL_SCHED+1)
     51 #define	IPL_HIGH	(IPL_DDB+1)
     52 
     53 #define	IPL_SAFEPRI	IPL_SOFTSERIAL
     54 
     55 #define	_IPL_N		(IPL_HIGH+1)
     56 #define	_IPL_NAMES(pfx)	{ pfx"none", pfx"softclock/bio", pfx"softnet/serial", \
     57 			  pfx"vm", pfx"sched", pfx"ddb", pfx"high" }
     58 
     59 #define	IST_UNUSABLE	-1		/* interrupt cannot be used */
     60 #define	IST_NONE	0		/* none (dummy) */
     61 #define	IST_PULSE	1		/* pulsed */
     62 #define	IST_EDGE	2		/* edge-triggered */
     63 #define	IST_LEVEL	3		/* level-triggered */
     64 #define	IST_LEVEL_HIGH	4		/* level triggered, active high */
     65 #define	IST_LEVEL_LOW	5		/* level triggered, active low */
     66 
     67 #define IST_MPSAFE	0x100		/* interrupt is MPSAFE */
     68 
     69 #define	IPI_NOP		0		/* do nothing, interrupt only */
     70 #define	IPI_AST		1		/* force ast */
     71 #define	IPI_SHOOTDOWN	2		/* do a tlb shootdown */
     72 #define	IPI_SYNCICACHE	3		/* sync icache for pages */
     73 #define	IPI_KPREEMPT	4		/* schedule a kernel preemption */
     74 #define	IPI_SUSPEND	5		/* DDB suspend signaling */
     75 #define	IPI_HALT	6		/* halt cpu */
     76 #define	IPI_XCALL	7		/* xcall */
     77 #define	IPI_GENERIC	8		/* generic IPI */
     78 #define	NIPIS		9
     79 
     80 #ifdef __INTR_PRIVATE
     81 struct splsw {
     82 	int	(*splsw_splhigh)(void);
     83 	int	(*splsw_splsched)(void);
     84 	int	(*splsw_splvm)(void);
     85 	int	(*splsw_splsoftserial)(void);
     86 	int	(*splsw_splsoftnet)(void);
     87 	int	(*splsw_splsoftbio)(void);
     88 	int	(*splsw_splsoftclock)(void);
     89 	int	(*splsw_splraise)(int);
     90 	void	(*splsw_spl0)(void);
     91 	void	(*splsw_splx)(int);
     92 	int	(*splsw_splhigh_noprof)(void);
     93 	void	(*splsw_splx_noprof)(int);
     94 	void	(*splsw__setsoftintr)(uint32_t);
     95 	void	(*splsw__clrsoftintr)(uint32_t);
     96 	int	(*splsw_splintr)(uint32_t *);
     97 	void	(*splsw_splcheck)(void);
     98 };
     99 
    100 struct ipl_sr_map {
    101 	uint32_t sr_bits[_IPL_N];
    102 };
    103 #else
    104 struct splsw;
    105 #endif /* __INTR_PRIVATE */
    106 
    107 typedef int ipl_t;
    108 typedef struct {
    109         ipl_t _spl;
    110 } ipl_cookie_t;
    111 
    112 #ifdef _KERNEL
    113 
    114 #if defined(MULTIPROCESSOR) && defined(__HAVE_FAST_SOFTINTS)
    115 #define __HAVE_PREEMPTION	1
    116 #define SOFTINT_KPREEMPT	(SOFTINT_COUNT+0)
    117 #endif
    118 
    119 #ifdef __INTR_PRIVATE
    120 extern	struct splsw	mips_splsw;
    121 extern	struct ipl_sr_map ipl_sr_map;
    122 #endif /* __INTR_PRIVATE */
    123 
    124 int	splhigh(void);
    125 int	splhigh_noprof(void);
    126 int	splsched(void);
    127 int	splvm(void);
    128 int	splsoftserial(void);
    129 int	splsoftnet(void);
    130 int	splsoftbio(void);
    131 int	splsoftclock(void);
    132 int	splraise(int);
    133 void	splx(int);
    134 void	splx_noprof(int);
    135 void	spl0(void);
    136 int	splintr(uint32_t *);
    137 void	_setsoftintr(uint32_t);
    138 void	_clrsoftintr(uint32_t);
    139 
    140 struct cpu_info;
    141 
    142 void	ipi_init(struct cpu_info *);
    143 void	ipi_process(struct cpu_info *, uint64_t);
    144 
    145 /*
    146  * These make no sense *NOT* to be inlined.
    147  */
    148 static inline ipl_cookie_t
    149 makeiplcookie(ipl_t s)
    150 {
    151 	return (ipl_cookie_t){._spl = s};
    152 }
    153 
    154 static inline int
    155 splraiseipl(ipl_cookie_t icookie)
    156 {
    157 	return splraise(icookie._spl);
    158 }
    159 
    160 #endif /* _KERNEL */
    161 #endif /* _MIPS_INTR_H_ */
    162