mips3_pte.h revision 1.14
1 /* $NetBSD: mips3_pte.h,v 1.14 2002/03/05 15:37:32 simonb Exp $ */ 2 3 /* 4 * Copyright (c) 1988 University of Utah. 5 * Copyright (c) 1992, 1993 6 * The Regents of the University of California. All rights reserved. 7 * 8 * This code is derived from software contributed to Berkeley by 9 * the Systems Programming Group of the University of Utah Computer 10 * Science Department and Ralph Campbell. 11 * 12 * Redistribution and use in source and binary forms, with or without 13 * modification, are permitted provided that the following conditions 14 * are met: 15 * 1. Redistributions of source code must retain the above copyright 16 * notice, this list of conditions and the following disclaimer. 17 * 2. Redistributions in binary form must reproduce the above copyright 18 * notice, this list of conditions and the following disclaimer in the 19 * documentation and/or other materials provided with the distribution. 20 * 3. All advertising materials mentioning features or use of this software 21 * must display the following acknowledgement: 22 * This product includes software developed by the University of 23 * California, Berkeley and its contributors. 24 * 4. Neither the name of the University nor the names of its contributors 25 * may be used to endorse or promote products derived from this software 26 * without specific prior written permission. 27 * 28 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 29 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 30 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 31 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 32 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 33 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 34 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 35 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 36 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 37 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 38 * SUCH DAMAGE. 39 * 40 * from: Utah Hdr: pte.h 1.11 89/09/03 41 * 42 * from: @(#)pte.h 8.1 (Berkeley) 6/10/93 43 */ 44 45 /* 46 * R4000 hardware page table entry 47 */ 48 49 #ifndef _LOCORE 50 struct mips3_pte { 51 #if BYTE_ORDER == BIG_ENDIAN 52 unsigned int pg_prot:2, /* SW: access control */ 53 pg_pfnum:24, /* HW: core page frame number or 0 */ 54 pg_attr:3, /* HW: cache attribute */ 55 pg_m:1, /* HW: dirty bit */ 56 pg_v:1, /* HW: valid bit */ 57 pg_g:1; /* HW: ignore asid bit */ 58 #endif 59 #if BYTE_ORDER == LITTLE_ENDIAN 60 unsigned int pg_g:1, /* HW: ignore asid bit */ 61 pg_v:1, /* HW: valid bit */ 62 pg_m:1, /* HW: dirty bit */ 63 pg_attr:3, /* HW: cache attribute */ 64 pg_pfnum:24, /* HW: core page frame number or 0 */ 65 pg_prot:2; /* SW: access control */ 66 #endif 67 }; 68 69 /* 70 * Structure defining an tlb entry data set. 71 */ 72 73 struct tlb { 74 int tlb_mask; 75 int tlb_hi; /* XXX should be 64 bits */ 76 int tlb_lo0; /* XXX maybe 64 bits (only 32 really used) */ 77 int tlb_lo1; /* XXX maybe 64 bits (only 32 really used) */ 78 }; 79 #endif /* _LOCORE */ 80 81 #define MIPS3_PG_WIRED 0x80000000 /* SW */ 82 #define MIPS3_PG_RO 0x40000000 /* SW */ 83 84 #define MIPS3_PG_SVPN 0xfffff000 /* Software page no mask */ 85 #define MIPS3_PG_HVPN 0xffffe000 /* Hardware page no mask */ 86 #define MIPS3_PG_ODDPG 0x00001000 /* Odd even pte entry */ 87 #define MIPS3_PG_ASID 0x000000ff /* Address space ID */ 88 #define MIPS3_PG_G 0x00000001 /* Global; ignore ASID if in lo0 & lo1 */ 89 #define MIPS3_PG_V 0x00000002 /* Valid */ 90 #define MIPS3_PG_NV 0x00000000 91 #define MIPS3_PG_D 0x00000004 /* Dirty */ 92 #define MIPS3_PG_ATTR 0x0000003f 93 94 #define MIPS3_CCA_TO_PG(cca) ((cca) << 3) 95 96 #define MIPS3_PG_UNCACHED MIPS3_CCA_TO_PG(2) 97 #ifdef HPCMIPS_L1CACHE_DISABLE /* MIPS3_L1CACHE_DISABLE */ 98 #define MIPS3_PG_CACHED MIPS3_PG_UNCACHED /* XXX: brain damaged!!! */ 99 #else /* HPCMIPS_L1CACHE_DISABLE */ 100 #define MIPS3_PG_CACHED mips3_pg_cached 101 #define MIPS3_DEFAULT_PG_CACHED MIPS3_CCA_TO_PG(3) 102 #endif /* ! HPCMIPS_L1CACHE_DISABLE */ 103 #define MIPS3_PG_CACHEMODE MIPS3_CCA_TO_PG(7) 104 105 /* Write protected */ 106 #define MIPS3_PG_ROPAGE (MIPS3_PG_V | MIPS3_PG_RO | MIPS3_PG_CACHED) 107 108 /* Not wr-prot not clean */ 109 #define MIPS3_PG_RWPAGE (MIPS3_PG_V | MIPS3_PG_D | MIPS3_PG_CACHED) 110 111 /* Not wr-prot but clean */ 112 #define MIPS3_PG_CWPAGE (MIPS3_PG_V | MIPS3_PG_CACHED) 113 #define MIPS3_PG_IOPAGE(cca) \ 114 (MIPS3_PG_G | MIPS3_PG_V | MIPS3_PG_D | MIPS3_CCA_TO_PG(cca)) 115 #define MIPS3_PG_FRAME 0x3fffffc0 116 #ifdef MIPS3_4100 /* VR4100 core */ 117 #define MIPS3_PG_SHIFT 4 118 #else 119 #define MIPS3_PG_SHIFT 6 120 #endif 121 122 /* pte accessor macros */ 123 124 #define mips3_pfn_is_ext(x) ((x) & 0x3c000000) 125 #define mips3_paddr_to_tlbpfn(x) \ 126 (((paddr_t)(x) >> MIPS3_PG_SHIFT) & MIPS3_PG_FRAME) 127 #define mips3_tlbpfn_to_paddr(x) \ 128 ((paddr_t)((x) & MIPS3_PG_FRAME) << MIPS3_PG_SHIFT) 129 #define mips3_vad_to_vpn(x) ((vaddr_t)(x) & MIPS3_PG_SVPN) 130 #define mips3_vpn_to_vad(x) ((x) & MIPS3_PG_SVPN) 131 132 #define MIPS3_PTE_TO_PADDR(pte) (mips3_tlbpfn_to_paddr(pte)) 133 #define MIPS3_PAGE_IS_RDONLY(pte,va) \ 134 (pmap_is_page_ro(pmap_kernel(), mips_trunc_page(va), (pte))) 135 136 137 #define MIPS3_PG_SIZE_4K 0x00000000 138 #define MIPS3_PG_SIZE_16K 0x00006000 139 #define MIPS3_PG_SIZE_64K 0x0001e000 140 #define MIPS3_PG_SIZE_256K 0x0007e000 141 #define MIPS3_PG_SIZE_1M 0x001fe000 142 #define MIPS3_PG_SIZE_4M 0x007fe000 143 #define MIPS3_PG_SIZE_16M 0x01ffe000 144
Indexes created Tue Sep 23 23:09:58 GMT 2025