mips3_pte.h revision 1.26
1 /* $NetBSD: mips3_pte.h,v 1.26 2011/02/08 20:20:19 rmind Exp $ */ 2 3 /* 4 * Copyright (c) 1988 University of Utah. 5 * Copyright (c) 1992, 1993 6 * The Regents of the University of California. All rights reserved. 7 * 8 * This code is derived from software contributed to Berkeley by 9 * the Systems Programming Group of the University of Utah Computer 10 * Science Department and Ralph Campbell. 11 * 12 * Redistribution and use in source and binary forms, with or without 13 * modification, are permitted provided that the following conditions 14 * are met: 15 * 1. Redistributions of source code must retain the above copyright 16 * notice, this list of conditions and the following disclaimer. 17 * 2. Redistributions in binary form must reproduce the above copyright 18 * notice, this list of conditions and the following disclaimer in the 19 * documentation and/or other materials provided with the distribution. 20 * 3. Neither the name of the University nor the names of its contributors 21 * may be used to endorse or promote products derived from this software 22 * without specific prior written permission. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 25 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 27 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 30 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 31 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 32 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 33 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 34 * SUCH DAMAGE. 35 * 36 * from: Utah Hdr: pte.h 1.11 89/09/03 37 * 38 * from: @(#)pte.h 8.1 (Berkeley) 6/10/93 39 */ 40 41 /* 42 * R4000 hardware page table entry 43 */ 44 45 #ifndef _LOCORE 46 struct mips3_pte { 47 #if BYTE_ORDER == BIG_ENDIAN 48 unsigned int pg_prot:2, /* SW: access control */ 49 pg_pfnum:24, /* HW: core page frame number or 0 */ 50 pg_attr:3, /* HW: cache attribute */ 51 pg_m:1, /* HW: dirty bit */ 52 pg_v:1, /* HW: valid bit */ 53 pg_g:1; /* HW: ignore asid bit */ 54 #endif 55 #if BYTE_ORDER == LITTLE_ENDIAN 56 unsigned int pg_g:1, /* HW: ignore asid bit */ 57 pg_v:1, /* HW: valid bit */ 58 pg_m:1, /* HW: dirty bit */ 59 pg_attr:3, /* HW: cache attribute */ 60 pg_pfnum:24, /* HW: core page frame number or 0 */ 61 pg_prot:2; /* SW: access control */ 62 #endif 63 }; 64 65 /* 66 * Structure defining an tlb entry data set. 67 */ 68 69 struct tlb { 70 int tlb_mask; 71 int tlb_hi; /* XXX should be 64 bits */ 72 int tlb_lo0; /* XXX maybe 64 bits (only 32 really used) */ 73 int tlb_lo1; /* XXX maybe 64 bits (only 32 really used) */ 74 }; 75 #endif /* _LOCORE */ 76 77 #define MIPS3_PG_WIRED 0x80000000 /* SW */ 78 #define MIPS3_PG_RO 0x40000000 /* SW */ 79 80 #ifdef ENABLE_MIPS_16KB_PAGE 81 #define MIPS3_PG_SVPN 0xffffc000 /* Software page no mask */ 82 #define MIPS3_PG_HVPN 0xffff8000 /* Hardware page no mask */ 83 #define MIPS3_PG_ODDPG 0x00004000 /* Odd even pte entry */ 84 #elif defined(ENABLE_MIPS_4KB_PAGE) || 1 85 #define MIPS3_PG_SVPN 0xfffff000 /* Software page no mask */ 86 #define MIPS3_PG_HVPN 0xffffe000 /* Hardware page no mask */ 87 #define MIPS3_PG_ODDPG 0x00001000 /* Odd even pte entry */ 88 #endif 89 #define MIPS3_PG_ASID 0x000000ff /* Address space ID */ 90 #define MIPS3_PG_G 0x00000001 /* Global; ignore ASID if in lo0 & lo1 */ 91 #define MIPS3_PG_V 0x00000002 /* Valid */ 92 #define MIPS3_PG_NV 0x00000000 93 #define MIPS3_PG_D 0x00000004 /* Dirty */ 94 #define MIPS3_PG_ATTR 0x0000003f 95 96 #define MIPS3_CCA_TO_PG(cca) ((cca) << 3) 97 #define MIPS3_PG_TO_CCA(cca) (((cca) >> 3) & 7) 98 99 #define MIPS3_XPHYS_UNCACHED MIPS_PHYS_TO_XKPHYS(2, 0) 100 #define MIPS3_PG_UNCACHED MIPS3_CCA_TO_PG(2) 101 #ifdef HPCMIPS_L1CACHE_DISABLE /* MIPS3_L1CACHE_DISABLE */ 102 #define MIPS3_DEFAULT_XKPHYS_CACHED MIPS3_DEFAULT_XKPHYS_UNCACHED 103 #define MIPS3_PG_CACHED MIPS3_PG_UNCACHED /* XXX: brain damaged!!! */ 104 #else /* HPCMIPS_L1CACHE_DISABLE */ 105 #define MIPS3_DEFAULT_XKPHYS_CACHED MIPS_PHYS_TO_XKPHYS(3, 0) 106 #define MIPS3_PG_CACHED mips3_pg_cached 107 #define MIPS3_DEFAULT_PG_CACHED MIPS3_CCA_TO_PG(3) 108 #endif /* ! HPCMIPS_L1CACHE_DISABLE */ 109 #define MIPS3_PG_CACHEMODE MIPS3_CCA_TO_PG(7) 110 111 /* Write protected */ 112 #define MIPS3_PG_ROPAGE (MIPS3_PG_V | MIPS3_PG_RO | MIPS3_PG_CACHED) 113 114 /* Not wr-prot not clean */ 115 #define MIPS3_PG_RWPAGE (MIPS3_PG_V | MIPS3_PG_D | MIPS3_PG_CACHED) 116 117 /* Not wr-prot not clean not cached */ 118 #define MIPS3_PG_RWNCPAGE (MIPS3_PG_V | MIPS3_PG_D | MIPS3_PG_UNCACHED) 119 120 /* Not wr-prot but clean */ 121 #define MIPS3_PG_CWPAGE (MIPS3_PG_V | MIPS3_PG_CACHED) 122 123 /* Not wr-prot but clean not cached*/ 124 #define MIPS3_PG_CWNCPAGE (MIPS3_PG_V | MIPS3_PG_UNCACHED) 125 126 #define MIPS3_PG_IOPAGE(cca) \ 127 (MIPS3_PG_G | MIPS3_PG_V | MIPS3_PG_D | MIPS3_CCA_TO_PG(cca)) 128 #define MIPS3_PG_FRAME 0x3fffffc0 129 130 #define MIPS3_DEFAULT_PG_SHIFT 6 131 #define MIPS3_4100_PG_SHIFT 4 132 133 /* NEC Vr4100 CPUs have different PFN layout to support 1kbytes/page */ 134 #if defined(MIPS3_4100) 135 #define MIPS3_PG_SHIFT mips3_pg_shift 136 #else 137 #define MIPS3_PG_SHIFT MIPS3_DEFAULT_PG_SHIFT 138 #endif 139 140 /* pte accessor macros */ 141 142 #define mips3_pfn_is_ext(x) ((x) & 0x3c000000) 143 #define mips3_paddr_to_tlbpfn(x) \ 144 (((paddr_t)(x) >> MIPS3_PG_SHIFT) & MIPS3_PG_FRAME) 145 #define mips3_tlbpfn_to_paddr(x) \ 146 ((paddr_t)((x) & MIPS3_PG_FRAME) << MIPS3_PG_SHIFT) 147 #define mips3_vad_to_vpn(x) ((vaddr_t)(x) & MIPS3_PG_SVPN) 148 #define mips3_vpn_to_vad(x) ((x) & MIPS3_PG_SVPN) 149 150 #define MIPS3_PTE_TO_PADDR(pte) (mips3_tlbpfn_to_paddr(pte)) 151 #define MIPS3_PAGE_IS_RDONLY(pte,va) \ 152 (pmap_is_page_ro(pmap_kernel(), mips_trunc_page(va), (pte))) 153 154 155 #define MIPS3_PG_SIZE_4K 0x00000000 156 #define MIPS3_PG_SIZE_16K 0x00006000 157 #define MIPS3_PG_SIZE_64K 0x0001e000 158 #define MIPS3_PG_SIZE_256K 0x0007e000 159 #define MIPS3_PG_SIZE_1M 0x001fe000 160 #define MIPS3_PG_SIZE_4M 0x007fe000 161 #define MIPS3_PG_SIZE_16M 0x01ffe000 162 #define MIPS3_PG_SIZE_64M 0x07ffe000 163 #define MIPS3_PG_SIZE_256M 0x1fffe000 164 165 #define MIPS3_PG_SIZE_MASK_TO_SIZE(pg_mask) \ 166 ((((pg_mask) | 0x00001fff) + 1) / 2) 167 168 #define MIPS3_PG_SIZE_TO_MASK(pg_size) \ 169 ((((pg_size) * 2) - 1) & ~0x00001fff) 170 171 /* NEC Vr41xx uses different pagemask values. */ 172 #define MIPS4100_PG_SIZE_1K 0x00000000 173 #define MIPS4100_PG_SIZE_4K 0x00001800 174 #define MIPS4100_PG_SIZE_16K 0x00007800 175 #define MIPS4100_PG_SIZE_64K 0x0001f800 176 #define MIPS4100_PG_SIZE_256K 0x0007f800 177 178 #define MIPS4100_PG_SIZE_MASK_TO_SIZE(pg_mask) \ 179 ((((pg_mask) | 0x000007ff) + 1) / 2) 180 181 #define MIPS4100_PG_SIZE_TO_MASK(pg_size) \ 182 ((((pg_size) * 2) - 1) & ~0x000007ff) 183 184
Indexes created Fri Sep 26 20:09:58 GMT 2025