mipsNN.h revision 1.3
1 /* $NetBSD: mipsNN.h,v 1.3 2003/02/07 17:38:48 cgd Exp $ */ 2 3 /* 4 * Copyright 2000, 2001 5 * Broadcom Corporation. All rights reserved. 6 * 7 * This software is furnished under license and may be used and copied only 8 * in accordance with the following terms and conditions. Subject to these 9 * conditions, you may download, copy, install, use, modify and distribute 10 * modified or unmodified copies of this software in source and/or binary 11 * form. No title or ownership is transferred hereby. 12 * 13 * 1) Any source code used, modified or distributed must reproduce and 14 * retain this copyright notice and list of conditions as they appear in 15 * the source file. 16 * 17 * 2) No right is granted to use any trade name, trademark, or logo of 18 * Broadcom Corporation. The "Broadcom Corporation" name may not be 19 * used to endorse or promote products derived from this software 20 * without the prior written permission of Broadcom Corporation. 21 * 22 * 3) THIS SOFTWARE IS PROVIDED "AS-IS" AND ANY EXPRESS OR IMPLIED 23 * WARRANTIES, INCLUDING BUT NOT LIMITED TO, ANY IMPLIED WARRANTIES OF 24 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR 25 * NON-INFRINGEMENT ARE DISCLAIMED. IN NO EVENT SHALL BROADCOM BE LIABLE 26 * FOR ANY DAMAGES WHATSOEVER, AND IN PARTICULAR, BROADCOM SHALL NOT BE 27 * LIABLE FOR DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 28 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 29 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR 30 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 31 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE 32 * OR OTHERWISE), EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 33 */ 34 35 /* 36 * Values related to the MIPS32/MIPS64 Privileged Resource Architecture. 37 */ 38 39 #define _MIPSNN_SHIFT(reg) __MIPSNN_SHIFT(reg) 40 #define __MIPSNN_SHIFT(reg) MIPSNN_ ## reg ## _SHIFT 41 #define _MIPSNN_MASK(reg) __MIPSNN_MASK(reg) 42 #define __MIPSNN_MASK(reg) MIPSNN_ ## reg ## _MASK 43 44 #define MIPSNN_GET(reg, x) \ 45 ((unsigned)((x) & _MIPSNN_MASK(reg)) >> _MIPSNN_SHIFT(reg)) 46 #define MIPSNN_PUT(reg, val) \ 47 (((x) << _MIPSNN_SHIFT(reg)) & _MIPSNN_MASK(reg)) 48 49 /* 50 * Values in Configuration Register (CP0 Register 16, Select 0) 51 */ 52 53 /* "M" (R): Configuration Register 1 present if set. Defined as always set. */ 54 #define MIPSNN_CFG_M 0x80000000 55 56 /* Reserved for CPU implementations. */ 57 // reserved 0x7fff0000 58 59 /* "BE" (R): Big endian if set, little endian if clear. */ 60 #define MIPSNN_CFG_BE 0x00008000 61 62 /* "AT" (R): architecture type implemented by processor */ 63 #define MIPSNN_CFG_AT_MASK 0x00006000 64 #define MIPSNN_CFG_AT_SHIFT 13 65 66 #define MIPSNN_CFG_AT_MIPS32 0 /* MIPS32 */ 67 #define MIPSNN_CFG_AT_MIPS64S 1 /* MIPS64S */ 68 #define MIPSNN_CFG_AT_MIPS64 2 /* MIPS64 */ 69 // reserved 3 70 71 /* "AR" (R): Architecture revision level implemented by proc. */ 72 #define MIPSNN_CFG_AR_MASK 0x00001c00 73 #define MIPSNN_CFG_AR_SHIFT 10 74 75 #define MIPSNN_CFG_AR_REV1 0 /* Revision 1 */ 76 // reserved other values 77 78 /* "MT" (R): MMU type implemented by processor */ 79 #define MIPSNN_CFG_MT_MASK 0x00000380 80 #define MIPSNN_CFG_MT_SHIFT 7 81 82 #define MIPSNN_CFG_MT_NONE 0 /* No MMU */ 83 #define MIPSNN_CFG_MT_TLB 1 /* Std TLB */ 84 #define MIPSNN_CFG_MT_BAT 2 /* Std BAT */ 85 #define MIPSNN_CFG_MT_FIXED 3 /* Std Fixed mapping */ 86 // reserved other values 87 88 /* Reserved. Write as 0, reads as 0. */ 89 // reserved 0x00000070 90 91 /* "M" (R): Virtual instruction cache if set. */ 92 #define MIPSNN_CFG_VI 0x00000008 93 94 /* "K0" (RW): Kseg0 coherency algorithm. (values are TLB_ATTRs) */ 95 #define MIPSNN_CFG_K0_MASK 0x00000007 96 #define MIPSNN_CFG_K0_SHIFT 0 97 98 99 /* 100 * Values in Configuration Register 1 (CP0 Register 16, Select 1) 101 */ 102 103 /* Reserved for Configuration Register 2 present. Write as 0, reads as 0. */ 104 // reserved 0x80000000 105 106 /* MS (R): Number of TLB entries - 1. */ 107 #define MIPSNN_CFG1_MS_MASK 0x7e000000 108 #define MIPSNN_CFG1_MS_SHIFT 25 109 110 #define MIPSNN_CFG1_MS(x) (MIPSNN_GET(CFG1_MS, (x)) + 1) 111 112 /* "IS" (R): (Primary) I-cache sets per way. */ 113 #define MIPSNN_CFG1_IS_MASK 0x01c00000 114 #define MIPSNN_CFG1_IS_SHIFT 22 115 116 #define MIPSNN_CFG1_IS_RSVD 7 /* rsvd value, otherwise: */ 117 #define MIPSNN_CFG1_IS(x) (64 << MIPSNN_GET(CFG1_IS, (x))) 118 119 /* "IL" (R): (Primary) I-cache line size. */ 120 #define MIPSNN_CFG1_IL_MASK 0x00380000 121 #define MIPSNN_CFG1_IL_SHIFT 19 122 123 #define MIPSNN_CFG1_IL_NONE 0 /* No I-cache, */ 124 #define MIPSNN_CFG1_IL_RSVD 7 /* rsvd value, otherwise: */ 125 #define MIPSNN_CFG1_IL(x) (2 << MIPSNN_GET(CFG1_IL, (x))) 126 127 /* "IA" (R): (Primary) I-cache associativity (ways - 1). */ 128 #define MIPSNN_CFG1_IA_MASK 0x00070000 129 #define MIPSNN_CFG1_IA_SHIFT 16 130 131 #define MIPSNN_CFG1_IA(x) MIPSNN_GET(CFG1_IA, (x)) 132 133 /* "DS" (R): (Primary) D-cache sets per way. */ 134 #define MIPSNN_CFG1_DS_MASK 0x0000e000 135 #define MIPSNN_CFG1_DS_SHIFT 13 136 137 #define MIPSNN_CFG1_DS_RSVD 7 /* rsvd value, otherwise: */ 138 #define MIPSNN_CFG1_DS(x) (64 << MIPSNN_GET(CFG1_DS, (x))) 139 140 /* "DL" (R): (Primary) D-cache line size. */ 141 #define MIPSNN_CFG1_DL_MASK 0x00001c00 142 #define MIPSNN_CFG1_DL_SHIFT 10 143 144 #define MIPSNN_CFG1_DL_NONE 0 /* No D-cache, */ 145 #define MIPSNN_CFG1_DL_RSVD 7 /* rsvd value, otherwise: */ 146 #define MIPSNN_CFG1_DL(x) (2 << MIPSNN_GET(CFG1_DL, (x))) 147 148 /* "DA" (R): (Primary) D-cache associativity (ways - 1). */ 149 #define MIPSNN_CFG1_DA_MASK 0x00000380 150 #define MIPSNN_CFG1_DA_SHIFT 7 151 152 #define MIPSNN_CFG1_DA(x) MIPSNN_GET(CFG1_DA, (x)) 153 154 /* Reserved. Write as 0, reads as 0. */ 155 // reserved 0x00000060 156 157 /* "PC" (R): Performance Counters implemented if set. */ 158 #define MIPSNN_CFG1_PC 0x00000010 159 160 /* "WR" (R): Watch registers implemented if set. */ 161 #define MIPSNN_CFG1_WR 0x00000008 162 163 /* "CA" (R): Code compressiong (MIPS16) implemented if set. */ 164 #define MIPSNN_CFG1_CA 0x00000004 165 166 /* "EP" (R): EJTAG implemented if set. */ 167 #define MIPSNN_CFG1_EP 0x00000002 168 169 /* "FP" (R): FPU implemented if set. */ 170 #define MIPSNN_CFG1_FP 0x00000001 171
Indexes created Mon Sep 22 05:09:51 GMT 2025