mipsNN.h revision 1.4
1 /* $NetBSD: mipsNN.h,v 1.4 2006/03/20 18:31:29 gdamore Exp $ */ 2 3 /* 4 * Copyright 2000, 2001 5 * Broadcom Corporation. All rights reserved. 6 * 7 * This software is furnished under license and may be used and copied only 8 * in accordance with the following terms and conditions. Subject to these 9 * conditions, you may download, copy, install, use, modify and distribute 10 * modified or unmodified copies of this software in source and/or binary 11 * form. No title or ownership is transferred hereby. 12 * 13 * 1) Any source code used, modified or distributed must reproduce and 14 * retain this copyright notice and list of conditions as they appear in 15 * the source file. 16 * 17 * 2) No right is granted to use any trade name, trademark, or logo of 18 * Broadcom Corporation. The "Broadcom Corporation" name may not be 19 * used to endorse or promote products derived from this software 20 * without the prior written permission of Broadcom Corporation. 21 * 22 * 3) THIS SOFTWARE IS PROVIDED "AS-IS" AND ANY EXPRESS OR IMPLIED 23 * WARRANTIES, INCLUDING BUT NOT LIMITED TO, ANY IMPLIED WARRANTIES OF 24 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR 25 * NON-INFRINGEMENT ARE DISCLAIMED. IN NO EVENT SHALL BROADCOM BE LIABLE 26 * FOR ANY DAMAGES WHATSOEVER, AND IN PARTICULAR, BROADCOM SHALL NOT BE 27 * LIABLE FOR DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 28 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 29 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR 30 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 31 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE 32 * OR OTHERWISE), EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 33 */ 34 35 /* 36 * Values related to the MIPS32/MIPS64 Privileged Resource Architecture. 37 */ 38 39 #define _MIPSNN_SHIFT(reg) __MIPSNN_SHIFT(reg) 40 #define __MIPSNN_SHIFT(reg) MIPSNN_ ## reg ## _SHIFT 41 #define _MIPSNN_MASK(reg) __MIPSNN_MASK(reg) 42 #define __MIPSNN_MASK(reg) MIPSNN_ ## reg ## _MASK 43 44 #define MIPSNN_GET(reg, x) \ 45 ((unsigned)((x) & _MIPSNN_MASK(reg)) >> _MIPSNN_SHIFT(reg)) 46 #define MIPSNN_PUT(reg, val) \ 47 (((x) << _MIPSNN_SHIFT(reg)) & _MIPSNN_MASK(reg)) 48 49 /* 50 * Values in Configuration Register (CP0 Register 16, Select 0) 51 */ 52 53 /* "M" (R): Configuration Register 1 present if set. Defined as always set. */ 54 #define MIPSNN_CFG_M 0x80000000 55 56 /* Reserved for CPU implementations. */ 57 // reserved 0x7fff0000 58 59 /* "BE" (R): Big endian if set, little endian if clear. */ 60 #define MIPSNN_CFG_BE 0x00008000 61 62 /* "AT" (R): architecture type implemented by processor */ 63 #define MIPSNN_CFG_AT_MASK 0x00006000 64 #define MIPSNN_CFG_AT_SHIFT 13 65 66 #define MIPSNN_CFG_AT_MIPS32 0 /* MIPS32 */ 67 #define MIPSNN_CFG_AT_MIPS64S 1 /* MIPS64S */ 68 #define MIPSNN_CFG_AT_MIPS64 2 /* MIPS64 */ 69 // reserved 3 70 71 /* "AR" (R): Architecture revision level implemented by proc. */ 72 #define MIPSNN_CFG_AR_MASK 0x00001c00 73 #define MIPSNN_CFG_AR_SHIFT 10 74 75 #define MIPSNN_CFG_AR_REV1 0 /* Revision 1 */ 76 #define MIPSNN_CFG_AR_REV2 1 /* Revision 2 */ 77 // reserved other values 78 79 /* "MT" (R): MMU type implemented by processor */ 80 #define MIPSNN_CFG_MT_MASK 0x00000380 81 #define MIPSNN_CFG_MT_SHIFT 7 82 83 #define MIPSNN_CFG_MT_NONE 0 /* No MMU */ 84 #define MIPSNN_CFG_MT_TLB 1 /* Std TLB */ 85 #define MIPSNN_CFG_MT_BAT 2 /* Std BAT */ 86 #define MIPSNN_CFG_MT_FIXED 3 /* Std Fixed mapping */ 87 // reserved other values 88 89 /* Reserved. Write as 0, reads as 0. */ 90 // reserved 0x00000070 91 92 /* "M" (R): Virtual instruction cache if set. */ 93 #define MIPSNN_CFG_VI 0x00000008 94 95 /* "K0" (RW): Kseg0 coherency algorithm. (values are TLB_ATTRs) */ 96 #define MIPSNN_CFG_K0_MASK 0x00000007 97 #define MIPSNN_CFG_K0_SHIFT 0 98 99 100 /* 101 * Values in Configuration Register 1 (CP0 Register 16, Select 1) 102 */ 103 104 /* M (R): Configuration Register 2 present. */ 105 #define MIPSNN_CFG1_M 0x80000000 106 107 /* MS (R): Number of TLB entries - 1. */ 108 #define MIPSNN_CFG1_MS_MASK 0x7e000000 109 #define MIPSNN_CFG1_MS_SHIFT 25 110 111 #define MIPSNN_CFG1_MS(x) (MIPSNN_GET(CFG1_MS, (x)) + 1) 112 113 /* "IS" (R): (Primary) I-cache sets per way. */ 114 #define MIPSNN_CFG1_IS_MASK 0x01c00000 115 #define MIPSNN_CFG1_IS_SHIFT 22 116 117 #define MIPSNN_CFG1_IS_RSVD 7 /* rsvd value, otherwise: */ 118 #define MIPSNN_CFG1_IS(x) (64 << MIPSNN_GET(CFG1_IS, (x))) 119 120 /* "IL" (R): (Primary) I-cache line size. */ 121 #define MIPSNN_CFG1_IL_MASK 0x00380000 122 #define MIPSNN_CFG1_IL_SHIFT 19 123 124 #define MIPSNN_CFG1_IL_NONE 0 /* No I-cache, */ 125 #define MIPSNN_CFG1_IL_RSVD 7 /* rsvd value, otherwise: */ 126 #define MIPSNN_CFG1_IL(x) (2 << MIPSNN_GET(CFG1_IL, (x))) 127 128 /* "IA" (R): (Primary) I-cache associativity (ways - 1). */ 129 #define MIPSNN_CFG1_IA_MASK 0x00070000 130 #define MIPSNN_CFG1_IA_SHIFT 16 131 132 #define MIPSNN_CFG1_IA(x) MIPSNN_GET(CFG1_IA, (x)) 133 134 /* "DS" (R): (Primary) D-cache sets per way. */ 135 #define MIPSNN_CFG1_DS_MASK 0x0000e000 136 #define MIPSNN_CFG1_DS_SHIFT 13 137 138 #define MIPSNN_CFG1_DS_RSVD 7 /* rsvd value, otherwise: */ 139 #define MIPSNN_CFG1_DS(x) (64 << MIPSNN_GET(CFG1_DS, (x))) 140 141 /* "DL" (R): (Primary) D-cache line size. */ 142 #define MIPSNN_CFG1_DL_MASK 0x00001c00 143 #define MIPSNN_CFG1_DL_SHIFT 10 144 145 #define MIPSNN_CFG1_DL_NONE 0 /* No D-cache, */ 146 #define MIPSNN_CFG1_DL_RSVD 7 /* rsvd value, otherwise: */ 147 #define MIPSNN_CFG1_DL(x) (2 << MIPSNN_GET(CFG1_DL, (x))) 148 149 /* "DA" (R): (Primary) D-cache associativity (ways - 1). */ 150 #define MIPSNN_CFG1_DA_MASK 0x00000380 151 #define MIPSNN_CFG1_DA_SHIFT 7 152 153 #define MIPSNN_CFG1_DA(x) MIPSNN_GET(CFG1_DA, (x)) 154 155 /* "C2" (R): Coprocessor 2 implemented if set. */ 156 #define MIPSNN_CFG1_C2 0x00000040 157 158 /* "MD" (R): MDMX ASE implemented if set. */ 159 #define MIPSNN_CFG1_MD 0x00000020 160 161 /* "PC" (R): Performance Counters implemented if set. */ 162 #define MIPSNN_CFG1_PC 0x00000010 163 164 /* "WR" (R): Watch registers implemented if set. */ 165 #define MIPSNN_CFG1_WR 0x00000008 166 167 /* "CA" (R): Code compressiong (MIPS16) implemented if set. */ 168 #define MIPSNN_CFG1_CA 0x00000004 169 170 /* "EP" (R): EJTAG implemented if set. */ 171 #define MIPSNN_CFG1_EP 0x00000002 172 173 /* "FP" (R): FPU implemented if set. */ 174 #define MIPSNN_CFG1_FP 0x00000001 175 176 /* 177 * Values in Configuration Register 2 (CP0 Register 16, Select 2) 178 */ 179 180 /* "M" (R): Configuration Register 3 present. */ 181 #define MIPSNN_CFG2_M 0x80000000 182 183 /* "TU" (RW): Implementation specific tertiary cache status and control. */ 184 #define MIPSNN_CFG2_TU_MASK 0x70000000 185 #define MIPSNN_CFG2_TU_SHIFT 28 186 187 /* "TS" (R): Tertiary cache sets per way. */ 188 #define MIPSNN_CFG2_TS_MASK 0x07000000 189 #define MIPSNN_CFG2_TS_SHIFT 24 190 191 #define MIPSNN_CFG2_TS(x) (64 << MIPSNN_GET(CFG2_TS, (x))) 192 193 /* "TL" (R): Tertiary cache line size. */ 194 #define MIPSNN_CFG2_TL_MASK 0x00700000 195 #define MIPSNN_CFG2_TL_SHIFT 20 196 197 #define MIPSNN_CFG2_TL_NONE 0 /* No Tertiary cache */ 198 #define MIPSNN_CFG2_TL(x) (2 << MIPSNN_GET(CFG2_TL, (x))) 199 200 /* "TA" (R): Tertiary cache associativity (ways - 1). */ 201 #define MIPSNN_CFG2_TA_MASK 0x00070000 202 #define MIPSNN_CFG2_TA_SHIFT 16 203 204 #define MIPSNN_CFG2_TA(x) MIPSNN_GET(CFG2_TA, (x)) 205 206 /* "SU" (RW): Implementation specific secondary cache status and control. */ 207 #define MIPSNN_CFG2_SU_MASK 0x0000f000 208 #define MIPSNN_CFG2_SU_SHIFT 12 209 210 /* "SS" (R): Secondary cache sets per way. */ 211 #define MIPSNN_CFG2_SS_MASK 0x00000700 212 #define MIPSNN_CFG2_SS_SHIFT 8 213 214 #define MIPSNN_CFG2_SS(x) (64 << MIPSNN_GET(CFG2_SS, (x))) 215 216 /* "SL" (R): Secdonary cache line size. */ 217 #define MIPSNN_CFG2_SL_MASK 0x00000070 218 #define MIPSNN_CFG2_SL_SHIFT 4 219 220 #define MIPSNN_CFG2_SL_NONE 0 /* No Secondary cache */ 221 #define MIPSNN_CFG2_SL(x) (2 << MIPSNN_GET(CFG2_SL, (x))) 222 223 /* "SA" (R): Secondary cache associativity (ways - 1). */ 224 #define MIPSNN_CFG2_SA_MASK 0x00000007 225 #define MIPSNN_CFG2_SA_SHIFT 0 226 227 #define MIPSNN_CFG2_SA(x) MIPSNN_GET(CFG2_SA, (x)) 228 229 /* 230 * Values in Configuration Register 3 (CP0 Register 16, Select 3) 231 */ 232 233 /* "M" (R): Configuration Register 4 present. */ 234 #define MIPSNN_CFG3_M 0x80000000 235 236 /* "DSPP" (R): DSPP ASE extension present. */ 237 #define MIPSNN_CFG3_DSPP 0x00000400 238 239 /* "LPA" (R): Large physical addresses implemented. (MIPS64 rev 2 only). */ 240 #define MIPSNN_CFG3_LPA 0x00000080 241 242 /* "VEIC" (R): External interrupt controller present. (rev 2 only). */ 243 #define MIPSNN_CFG3_VEIC 0x00000040 244 245 /* "VINT" (R): Vectored interrupts implemented. (rev 2 only). */ 246 #define MIPSNN_CFG3_VINT 0x00000020 247 248 /* "SP" (R): Small (1K) page support implemented. (rev 2 only). */ 249 #define MIPSNN_CFG3_SP 0x00000010 250 251 /* "MT" (R): MT ASE extension implemented. */ 252 #define MIPSNN_CFG3_MT 0x00000004 253 254 /* "SM" (R): SmartMIPS ASE extension implemented. */ 255 #define MIPSNN_CFG3_SM 0x00000002 256 257 /* "TL" (R): Trace Logic implemented. */ 258 #define MIPSNN_CFG3_TL 0x00000001 259
Indexes created Mon Sep 22 13:09:51 GMT 2025