pmap.h revision 1.54.26.14
1 /* $NetBSD: pmap.h,v 1.54.26.14 2010/08/16 18:01:13 matt Exp $ */ 2 3 /* 4 * Copyright (c) 1992, 1993 5 * The Regents of the University of California. All rights reserved. 6 * 7 * This code is derived from software contributed to Berkeley by 8 * Ralph Campbell. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. Neither the name of the University nor the names of its contributors 19 * may be used to endorse or promote products derived from this software 20 * without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 27 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 28 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 29 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 30 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 31 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 32 * SUCH DAMAGE. 33 * 34 * @(#)pmap.h 8.1 (Berkeley) 6/10/93 35 */ 36 37 /* 38 * Copyright (c) 1987 Carnegie-Mellon University 39 * 40 * This code is derived from software contributed to Berkeley by 41 * Ralph Campbell. 42 * 43 * Redistribution and use in source and binary forms, with or without 44 * modification, are permitted provided that the following conditions 45 * are met: 46 * 1. Redistributions of source code must retain the above copyright 47 * notice, this list of conditions and the following disclaimer. 48 * 2. Redistributions in binary form must reproduce the above copyright 49 * notice, this list of conditions and the following disclaimer in the 50 * documentation and/or other materials provided with the distribution. 51 * 3. All advertising materials mentioning features or use of this software 52 * must display the following acknowledgement: 53 * This product includes software developed by the University of 54 * California, Berkeley and its contributors. 55 * 4. Neither the name of the University nor the names of its contributors 56 * may be used to endorse or promote products derived from this software 57 * without specific prior written permission. 58 * 59 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 60 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 61 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 62 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 63 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 64 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 65 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 66 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 67 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 68 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 69 * SUCH DAMAGE. 70 * 71 * @(#)pmap.h 8.1 (Berkeley) 6/10/93 72 */ 73 74 #ifndef _MIPS_PMAP_H_ 75 #define _MIPS_PMAP_H_ 76 77 #include <mips/cpuregs.h> /* for KSEG0 below */ 78 //#include <mips/pte.h> 79 80 /* 81 * The user address space is 2Gb (0x0 - 0x80000000). 82 * User programs are laid out in memory as follows: 83 * address 84 * USRTEXT 0x00001000 85 * USRDATA USRTEXT + text_size 86 * USRSTACK 0x7FFFFFFF 87 * 88 * The user address space is mapped using a two level structure where 89 * virtual address bits 30..22 are used to index into a segment table which 90 * points to a page worth of PTEs (4096 page can hold 1024 PTEs). 91 * Bits 21..12 are then used to index a PTE which describes a page within 92 * a segment. 93 * 94 * The wired entries in the TLB will contain the following: 95 * 0-1 (UPAGES) for curproc user struct and kernel stack. 96 * 97 * Note: The kernel doesn't use the same data structures as user programs. 98 * All the PTE entries are stored in a single array in Sysmap which is 99 * dynamically allocated at boot time. 100 */ 101 102 #define mips_trunc_seg(x) ((vaddr_t)(x) & ~SEGOFSET) 103 #define mips_round_seg(x) (((vaddr_t)(x) + SEGOFSET) & ~SEGOFSET) 104 105 #ifdef _LP64 106 #define PMAP_SEGTABSIZE NSEGPG 107 #else 108 #define PMAP_SEGTABSIZE (1 << (31 - SEGSHIFT)) 109 #endif 110 111 union pt_entry; 112 113 union segtab { 114 #ifdef _LP64 115 union segtab *seg_seg[PMAP_SEGTABSIZE]; 116 #endif 117 union pt_entry *seg_tab[PMAP_SEGTABSIZE]; 118 }; 119 120 /* 121 * Structure defining an tlb entry data set. 122 */ 123 struct tlb { 124 vaddr_t tlb_hi; /* should be 64 bits */ 125 uint32_t tlb_lo0; /* XXX maybe 64 bits (only 32 really used) */ 126 uint32_t tlb_lo1; /* XXX maybe 64 bits (only 32 really used) */ 127 }; 128 129 struct tlbmask { 130 vaddr_t tlb_hi; /* should be 64 bits */ 131 uint32_t tlb_lo0; /* XXX maybe 64 bits (only 32 really used) */ 132 uint32_t tlb_lo1; /* XXX maybe 64 bits (only 32 really used) */ 133 uint32_t tlb_mask; 134 }; 135 136 #ifdef _KERNEL 137 struct pmap; 138 typedef bool (*pte_callback_t)(struct pmap *, vaddr_t, vaddr_t, 139 union pt_entry *, uintptr_t); 140 union pt_entry *pmap_pte_lookup(struct pmap *, vaddr_t); 141 union pt_entry *pmap_pte_reserve(struct pmap *, vaddr_t, int); 142 void pmap_pte_process(struct pmap *, vaddr_t, vaddr_t, pte_callback_t, 143 uintptr_t); 144 void pmap_segtab_activate(struct pmap *, struct lwp *); 145 void pmap_segtab_init(struct pmap *); 146 void pmap_segtab_destroy(struct pmap *); 147 #endif /* _KERNEL */ 148 149 /* 150 * Per TLB (normally same as CPU) asid info 151 */ 152 struct pmap_asid_info { 153 LIST_ENTRY(pmap_asid_info) pai_link; 154 uint32_t pai_asid; /* TLB address space tag */ 155 }; 156 157 #define TLBINFO_LOCK(ti) mutex_spin_enter((ti)->ti_lock) 158 #define TLBINFO_UNLOCK(ti) mutex_spin_exit((ti)->ti_lock) 159 #define PMAP_PAI_ASIDVALID_P(pai, ti) ((pai)->pai_asid != 0) 160 #define PMAP_PAI(pmap, ti) (&(pmap)->pm_pai[tlbinfo_index(ti)]) 161 #define PAI_PMAP(pai, ti) \ 162 ((pmap_t)((intptr_t)(pai) \ 163 - offsetof(struct pmap, pm_pai[tlbinfo_index(ti)]))) 164 165 /* 166 * Machine dependent pmap structure. 167 */ 168 typedef struct pmap { 169 #ifdef MULTIPROCESSOR 170 volatile uint32_t pm_active; /* pmap was active on ... */ 171 volatile uint32_t pm_onproc; /* pmap is active on ... */ 172 volatile u_int pm_shootdown_pending; 173 #endif 174 union segtab *pm_segtab; /* pointers to pages of PTEs */ 175 u_int pm_count; /* pmap reference count */ 176 u_int pm_flags; 177 #define PMAP_DEFERRED_ACTIVATE 0x0001 178 struct pmap_statistics pm_stats; /* pmap statistics */ 179 struct pmap_asid_info pm_pai[1]; 180 } *pmap_t; 181 182 enum tlb_invalidate_op { 183 TLBINV_NOBODY=0, 184 TLBINV_ONE=1, 185 TLBINV_ALLUSER=2, 186 TLBINV_ALLKERNEL=3, 187 TLBINV_ALL=4 188 }; 189 190 struct pmap_tlb_info { 191 char ti_name[8]; 192 uint32_t ti_asid_hint; /* probable next ASID to use */ 193 uint32_t ti_asids_free; /* # of ASIDs free */ 194 #define tlbinfo_noasids_p(ti) ((ti)->ti_asids_free == 0) 195 kmutex_t *ti_lock; 196 u_int ti_wired; /* # of wired TLB entries */ 197 uint32_t ti_asid_mask; 198 uint32_t ti_asid_max; 199 LIST_HEAD(, pmap_asid_info) ti_pais; /* list of active ASIDs */ 200 #ifdef MULTIPROCESSOR 201 pmap_t ti_victim; 202 uint32_t ti_synci_page_bitmap; /* page indices needing a syncicache */ 203 uint32_t ti_cpu_mask; /* bitmask of CPUs sharing this TLB */ 204 enum tlb_invalidate_op ti_tlbinvop; 205 u_int ti_index; 206 #define tlbinfo_index(ti) ((ti)->ti_index) 207 struct evcnt ti_evcnt_synci_asts; 208 struct evcnt ti_evcnt_synci_all; 209 struct evcnt ti_evcnt_synci_pages; 210 struct evcnt ti_evcnt_synci_deferred; 211 struct evcnt ti_evcnt_synci_desired; 212 struct evcnt ti_evcnt_synci_duplicate; 213 #else 214 #define tlbinfo_index(ti) (0) 215 #endif 216 u_long ti_asid_bitmap[256 / (sizeof(u_long) * 8)]; 217 }; 218 219 220 #ifdef _KERNEL 221 222 struct pmap_kernel { 223 struct pmap kernel_pmap; 224 #ifdef MULTIPROCESSOR 225 struct pmap_asid_info kernel_pai[MAXCPUS-1]; 226 #endif 227 }; 228 229 extern struct pmap_kernel kernel_pmap_store; 230 extern struct pmap_tlb_info pmap_tlb0_info; 231 #ifdef MULTIPROCESSOR 232 extern struct pmap_tlb_info *pmap_tlbs[MAXCPUS]; 233 extern u_int pmap_ntlbs; 234 #endif 235 extern paddr_t mips_avail_start; 236 extern paddr_t mips_avail_end; 237 extern vaddr_t mips_virtual_end; 238 239 #define pmap_kernel() (&kernel_pmap_store.kernel_pmap) 240 #define pmap_wired_count(pmap) ((pmap)->pm_stats.wired_count) 241 #define pmap_resident_count(pmap) ((pmap)->pm_stats.resident_count) 242 243 #define pmap_phys_address(x) mips_ptob(x) 244 245 /* 246 * Bootstrap the system enough to run with virtual memory. 247 */ 248 void pmap_bootstrap(void); 249 250 void pmap_remove_all(pmap_t); 251 void pmap_set_modified(paddr_t); 252 void pmap_procwr(struct proc *, vaddr_t, size_t); 253 #define PMAP_NEED_PROCWR 254 255 #ifdef MULTIPROCESSOR 256 void pmap_tlb_shootdown_process(void); 257 bool pmap_tlb_shootdown_bystanders(pmap_t pmap); 258 void pmap_tlb_info_attach(struct pmap_tlb_info *, struct cpu_info *); 259 void pmap_tlb_syncicache_ast(struct cpu_info *); 260 void pmap_tlb_syncicache_wanted(struct cpu_info *); 261 void pmap_tlb_syncicache(vaddr_t, uint32_t); 262 #endif 263 void pmap_tlb_info_init(struct pmap_tlb_info *); 264 void pmap_tlb_asid_acquire(pmap_t pmap, struct lwp *l); 265 void pmap_tlb_asid_deactivate(pmap_t pmap); 266 void pmap_tlb_asid_release_all(pmap_t pmap); 267 int pmap_tlb_update_addr(pmap_t pmap, vaddr_t, uint32_t, bool); 268 void pmap_tlb_invalidate_addr(pmap_t pmap, vaddr_t); 269 270 uint16_t pmap_pvlist_lock(struct vm_page *, bool); 271 272 /* 273 * pmap_prefer() helps reduce virtual-coherency exceptions in 274 * the virtually-indexed cache on mips3 CPUs. 275 */ 276 #ifdef MIPS3_PLUS 277 #define PMAP_PREFER(pa, va, sz, td) pmap_prefer((pa), (va), (sz), (td)) 278 void pmap_prefer(vaddr_t, vaddr_t *, vsize_t, int); 279 #endif /* MIPS3_PLUS */ 280 281 #define PMAP_STEAL_MEMORY /* enable pmap_steal_memory() */ 282 283 /* 284 * Alternate mapping hooks for pool pages. Avoids thrashing the TLB. 285 */ 286 vaddr_t mips_pmap_map_poolpage(paddr_t); 287 paddr_t mips_pmap_unmap_poolpage(vaddr_t); 288 struct vm_page *mips_pmap_alloc_poolpage(int); 289 #define PMAP_ALLOC_POOLPAGE(flags) mips_pmap_alloc_poolpage(flags) 290 #define PMAP_MAP_POOLPAGE(pa) mips_pmap_map_poolpage(pa) 291 #define PMAP_UNMAP_POOLPAGE(va) mips_pmap_unmap_poolpage(va) 292 293 /* 294 * Other hooks for the pool allocator. 295 */ 296 #ifdef _LP64 297 #define POOL_VTOPHYS(va) (MIPS_KSEG0_P(va) \ 298 ? MIPS_KSEG0_TO_PHYS(va) \ 299 : MIPS_XKPHYS_TO_PHYS(va)) 300 #else 301 #define POOL_VTOPHYS(va) MIPS_KSEG0_TO_PHYS((vaddr_t)(va)) 302 #endif 303 304 /* 305 * Select CCA to use for unmanaged pages. 306 */ 307 #define PMAP_CCA_FOR_PA(pa) CCA_UNCACHED /* uncached */ 308 309 #if defined(_MIPS_PADDR_T_64BIT) || defined(_LP64) 310 #define PMAP_NOCACHE 0x4000000000000000ULL 311 #endif 312 313 #endif /* _KERNEL */ 314 #endif /* _MIPS_PMAP_H_ */ 315
Indexes created Mon Oct 20 08:09:54 GMT 2025