pmap.h revision 1.54.26.16
1 /* $NetBSD: pmap.h,v 1.54.26.16 2011/02/05 06:00:12 cliff Exp $ */ 2 3 /* 4 * Copyright (c) 1992, 1993 5 * The Regents of the University of California. All rights reserved. 6 * 7 * This code is derived from software contributed to Berkeley by 8 * Ralph Campbell. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. Neither the name of the University nor the names of its contributors 19 * may be used to endorse or promote products derived from this software 20 * without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 27 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 28 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 29 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 30 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 31 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 32 * SUCH DAMAGE. 33 * 34 * @(#)pmap.h 8.1 (Berkeley) 6/10/93 35 */ 36 37 /* 38 * Copyright (c) 1987 Carnegie-Mellon University 39 * 40 * This code is derived from software contributed to Berkeley by 41 * Ralph Campbell. 42 * 43 * Redistribution and use in source and binary forms, with or without 44 * modification, are permitted provided that the following conditions 45 * are met: 46 * 1. Redistributions of source code must retain the above copyright 47 * notice, this list of conditions and the following disclaimer. 48 * 2. Redistributions in binary form must reproduce the above copyright 49 * notice, this list of conditions and the following disclaimer in the 50 * documentation and/or other materials provided with the distribution. 51 * 3. All advertising materials mentioning features or use of this software 52 * must display the following acknowledgement: 53 * This product includes software developed by the University of 54 * California, Berkeley and its contributors. 55 * 4. Neither the name of the University nor the names of its contributors 56 * may be used to endorse or promote products derived from this software 57 * without specific prior written permission. 58 * 59 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 60 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 61 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 62 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 63 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 64 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 65 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 66 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 67 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 68 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 69 * SUCH DAMAGE. 70 * 71 * @(#)pmap.h 8.1 (Berkeley) 6/10/93 72 */ 73 74 #ifndef _MIPS_PMAP_H_ 75 #define _MIPS_PMAP_H_ 76 77 #include "opt_multiprocessor.h" 78 79 #include <mips/cpuregs.h> /* for KSEG0 below */ 80 //#include <mips/pte.h> 81 82 /* 83 * The user address space is 2Gb (0x0 - 0x80000000). 84 * User programs are laid out in memory as follows: 85 * address 86 * USRTEXT 0x00001000 87 * USRDATA USRTEXT + text_size 88 * USRSTACK 0x7FFFFFFF 89 * 90 * The user address space is mapped using a two level structure where 91 * virtual address bits 30..22 are used to index into a segment table which 92 * points to a page worth of PTEs (4096 page can hold 1024 PTEs). 93 * Bits 21..12 are then used to index a PTE which describes a page within 94 * a segment. 95 * 96 * The wired entries in the TLB will contain the following: 97 * 0-1 (UPAGES) for curproc user struct and kernel stack. 98 * 99 * Note: The kernel doesn't use the same data structures as user programs. 100 * All the PTE entries are stored in a single array in Sysmap which is 101 * dynamically allocated at boot time. 102 */ 103 104 #define mips_trunc_seg(x) ((vaddr_t)(x) & ~SEGOFSET) 105 #define mips_round_seg(x) (((vaddr_t)(x) + SEGOFSET) & ~SEGOFSET) 106 107 #ifdef _LP64 108 #define PMAP_SEGTABSIZE NSEGPG 109 #else 110 #define PMAP_SEGTABSIZE (1 << (31 - SEGSHIFT)) 111 #endif 112 113 union pt_entry; 114 115 union segtab { 116 #ifdef _LP64 117 union segtab *seg_seg[PMAP_SEGTABSIZE]; 118 #endif 119 union pt_entry *seg_tab[PMAP_SEGTABSIZE]; 120 }; 121 122 /* 123 * Structure defining an tlb entry data set. 124 */ 125 struct tlb { 126 vaddr_t tlb_hi; /* should be 64 bits */ 127 uint32_t tlb_lo0; /* XXX maybe 64 bits (only 32 really used) */ 128 uint32_t tlb_lo1; /* XXX maybe 64 bits (only 32 really used) */ 129 }; 130 131 struct tlbmask { 132 vaddr_t tlb_hi; /* should be 64 bits */ 133 uint32_t tlb_lo0; /* XXX maybe 64 bits (only 32 really used) */ 134 uint32_t tlb_lo1; /* XXX maybe 64 bits (only 32 really used) */ 135 uint32_t tlb_mask; 136 }; 137 138 #ifdef _KERNEL 139 struct pmap; 140 typedef bool (*pte_callback_t)(struct pmap *, vaddr_t, vaddr_t, 141 union pt_entry *, uintptr_t); 142 union pt_entry *pmap_pte_lookup(struct pmap *, vaddr_t); 143 union pt_entry *pmap_pte_reserve(struct pmap *, vaddr_t, int); 144 void pmap_pte_process(struct pmap *, vaddr_t, vaddr_t, pte_callback_t, 145 uintptr_t); 146 void pmap_segtab_activate(struct pmap *, struct lwp *); 147 void pmap_segtab_init(struct pmap *); 148 void pmap_segtab_destroy(struct pmap *); 149 #endif /* _KERNEL */ 150 151 /* 152 * Per TLB (normally same as CPU) asid info 153 */ 154 struct pmap_asid_info { 155 LIST_ENTRY(pmap_asid_info) pai_link; 156 uint32_t pai_asid; /* TLB address space tag */ 157 }; 158 159 #define TLBINFO_LOCK(ti) mutex_spin_enter((ti)->ti_lock) 160 #define TLBINFO_UNLOCK(ti) mutex_spin_exit((ti)->ti_lock) 161 #define PMAP_PAI_ASIDVALID_P(pai, ti) ((pai)->pai_asid != 0) 162 #define PMAP_PAI(pmap, ti) (&(pmap)->pm_pai[tlbinfo_index(ti)]) 163 #define PAI_PMAP(pai, ti) \ 164 ((pmap_t)((intptr_t)(pai) \ 165 - offsetof(struct pmap, pm_pai[tlbinfo_index(ti)]))) 166 167 /* 168 * Machine dependent pmap structure. 169 */ 170 typedef struct pmap { 171 #ifdef MULTIPROCESSOR 172 volatile uint32_t pm_active; /* pmap was active on ... */ 173 volatile uint32_t pm_onproc; /* pmap is active on ... */ 174 volatile u_int pm_shootdown_pending; 175 #endif 176 union segtab *pm_segtab; /* pointers to pages of PTEs */ 177 u_int pm_count; /* pmap reference count */ 178 u_int pm_flags; 179 #define PMAP_DEFERRED_ACTIVATE 0x0001 180 struct pmap_statistics pm_stats; /* pmap statistics */ 181 struct pmap_asid_info pm_pai[1]; 182 } *pmap_t; 183 184 enum tlb_invalidate_op { 185 TLBINV_NOBODY=0, 186 TLBINV_ONE=1, 187 TLBINV_ALLUSER=2, 188 TLBINV_ALLKERNEL=3, 189 TLBINV_ALL=4 190 }; 191 192 struct pmap_tlb_info { 193 char ti_name[8]; 194 uint32_t ti_asid_hint; /* probable next ASID to use */ 195 uint32_t ti_asids_free; /* # of ASIDs free */ 196 #define tlbinfo_noasids_p(ti) ((ti)->ti_asids_free == 0) 197 kmutex_t *ti_lock; 198 u_int ti_wired; /* # of wired TLB entries */ 199 uint32_t ti_asid_mask; 200 uint32_t ti_asid_max; 201 LIST_HEAD(, pmap_asid_info) ti_pais; /* list of active ASIDs */ 202 #ifdef MULTIPROCESSOR 203 pmap_t ti_victim; 204 uint32_t ti_synci_page_bitmap; /* page indices needing a syncicache */ 205 uint32_t ti_cpu_mask; /* bitmask of CPUs sharing this TLB */ 206 enum tlb_invalidate_op ti_tlbinvop; 207 u_int ti_index; 208 #define tlbinfo_index(ti) ((ti)->ti_index) 209 struct evcnt ti_evcnt_synci_asts; 210 struct evcnt ti_evcnt_synci_all; 211 struct evcnt ti_evcnt_synci_pages; 212 struct evcnt ti_evcnt_synci_deferred; 213 struct evcnt ti_evcnt_synci_desired; 214 struct evcnt ti_evcnt_synci_duplicate; 215 #else 216 #define tlbinfo_index(ti) (0) 217 #endif 218 u_long ti_asid_bitmap[256 / (sizeof(u_long) * 8)]; 219 }; 220 221 222 #ifdef _KERNEL 223 224 struct pmap_kernel { 225 struct pmap kernel_pmap; 226 #ifdef MULTIPROCESSOR 227 struct pmap_asid_info kernel_pai[MAXCPUS-1]; 228 #endif 229 }; 230 231 extern struct pmap_kernel kernel_pmap_store; 232 extern struct pmap_tlb_info pmap_tlb0_info; 233 #ifdef MULTIPROCESSOR 234 extern struct pmap_tlb_info *pmap_tlbs[MAXCPUS]; 235 extern u_int pmap_ntlbs; 236 #endif 237 extern paddr_t mips_avail_start; 238 extern paddr_t mips_avail_end; 239 extern vaddr_t mips_virtual_end; 240 241 #define pmap_kernel() (&kernel_pmap_store.kernel_pmap) 242 #define pmap_wired_count(pmap) ((pmap)->pm_stats.wired_count) 243 #define pmap_resident_count(pmap) ((pmap)->pm_stats.resident_count) 244 245 #define pmap_phys_address(x) mips_ptob(x) 246 247 /* 248 * Bootstrap the system enough to run with virtual memory. 249 */ 250 void pmap_bootstrap(void); 251 252 void pmap_remove_all(pmap_t); 253 void pmap_set_modified(paddr_t); 254 void pmap_procwr(struct proc *, vaddr_t, size_t); 255 #define PMAP_NEED_PROCWR 256 257 #ifdef MULTIPROCESSOR 258 void pmap_tlb_shootdown_process(void); 259 bool pmap_tlb_shootdown_bystanders(pmap_t pmap); 260 void pmap_tlb_info_attach(struct pmap_tlb_info *, struct cpu_info *); 261 void pmap_tlb_syncicache_ast(struct cpu_info *); 262 void pmap_tlb_syncicache_wanted(struct cpu_info *); 263 void pmap_tlb_syncicache(vaddr_t, uint32_t); 264 #endif 265 void pmap_tlb_info_init(struct pmap_tlb_info *); 266 void pmap_tlb_asid_acquire(pmap_t pmap, struct lwp *l); 267 void pmap_tlb_asid_deactivate(pmap_t pmap); 268 void pmap_tlb_asid_check(void); 269 void pmap_tlb_asid_release_all(pmap_t pmap); 270 int pmap_tlb_update_addr(pmap_t pmap, vaddr_t, uint32_t, bool); 271 void pmap_tlb_invalidate_addr(pmap_t pmap, vaddr_t); 272 273 uint16_t pmap_pvlist_lock(struct vm_page *, bool); 274 275 /* 276 * pmap_prefer() helps reduce virtual-coherency exceptions in 277 * the virtually-indexed cache on mips3 CPUs. 278 */ 279 #ifdef MIPS3_PLUS 280 #define PMAP_PREFER(pa, va, sz, td) pmap_prefer((pa), (va), (sz), (td)) 281 void pmap_prefer(vaddr_t, vaddr_t *, vsize_t, int); 282 #endif /* MIPS3_PLUS */ 283 284 #define PMAP_STEAL_MEMORY /* enable pmap_steal_memory() */ 285 286 /* 287 * Alternate mapping hooks for pool pages. Avoids thrashing the TLB. 288 */ 289 vaddr_t mips_pmap_map_poolpage(paddr_t); 290 paddr_t mips_pmap_unmap_poolpage(vaddr_t); 291 struct vm_page *mips_pmap_alloc_poolpage(int); 292 #define PMAP_ALLOC_POOLPAGE(flags) mips_pmap_alloc_poolpage(flags) 293 #define PMAP_MAP_POOLPAGE(pa) mips_pmap_map_poolpage(pa) 294 #define PMAP_UNMAP_POOLPAGE(va) mips_pmap_unmap_poolpage(va) 295 296 /* 297 * Other hooks for the pool allocator. 298 */ 299 #ifdef _LP64 300 #define POOL_VTOPHYS(va) (MIPS_KSEG0_P(va) \ 301 ? MIPS_KSEG0_TO_PHYS(va) \ 302 : MIPS_XKPHYS_TO_PHYS(va)) 303 #else 304 #define POOL_VTOPHYS(va) MIPS_KSEG0_TO_PHYS((vaddr_t)(va)) 305 #endif 306 307 /* 308 * Select CCA to use for unmanaged pages. 309 */ 310 #define PMAP_CCA_FOR_PA(pa) CCA_UNCACHED /* uncached */ 311 312 #if defined(_MIPS_PADDR_T_64BIT) || defined(_LP64) 313 #define PMAP_NOCACHE 0x4000000000000000ULL 314 #endif 315 316 #endif /* _KERNEL */ 317 #endif /* _MIPS_PMAP_H_ */ 318
Indexes created Mon Oct 20 03:09:53 GMT 2025