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r3900regs.h revision 1.1 
      1 /*	$NetBSD: r3900regs.h,v 1.1 1999/11/29 11:13:11 uch Exp $ */
      2 
      3 /*
      4  * Copyright (c) 1999, by UCHIYAMA Yasushi
      5  * All rights reserved.
      6  *
      7  * Redistribution and use in source and binary forms, with or without
      8  * modification, are permitted provided that the following conditions
      9  * are met:
     10  * 1. Redistributions of source code must retain the above copyright
     11  *    notice, this list of conditions and the following disclaimer.
     12  * 2. The name of the developer may NOT be used to endorse or promote products
     13  *    derived from this software without specific prior written permission.
     14  *
     15  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
     16  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
     17  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
     18  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
     19  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
     20  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
     21  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
     22  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
     23  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
     24  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
     25  * SUCH DAMAGE.
     26  *
     27  */
     28 /*
     29  *	[address space]
     30  *	kseg2		0xc0000000 - 0xfeffffff
     31  *	reserved	0xff000000 - 0xfffeffff
     32  *	kseg2		0xffff0000 - 0xffffffff
     33  * -> vmparam.h VM_MAX_KERNEL_ADDRESS
     34  */
     35 
     36 /*
     37  *	[cause register]
     38  */
     39 #define	R3900_CR_EXC_CODE	MIPS3_CR_EXC_CODE /* five bits */
     40 #undef MIPS1_CR_EXC_CODE
     41 #define MIPS1_CR_EXC_CODE	R3900_CR_EXC_CODE
     42 
     43 /*
     44  *	[status register]
     45  *	R3900 don't have PE, CM, PZ, SwC and IsC.
     46  */
     47 #define R3900_SR_NMI		0x00100000 /* r3k PE position */
     48 #undef MIPS1_PARITY_ERR
     49 #undef MIPS1_CACHE_MISS
     50 #undef MIPS1_PARITY_ZERO
     51 #undef MIPS1_SWAP_CACHES
     52 #undef MIPS1_ISOL_CACHES
     53 
     54 /*
     55  *	[context register]
     56  * - no changes.
     57  */
     58 
     59 
     60 /*
     61  *	TX3900 Coprocessor 0 registers
     62  */
     63 #define	R3900_COP_0_CONFIG	$3
     64 #define	R3900_COP_0_DEBUG	$16
     65 #define	R3900_COP_0_DEPC	$17
     66 
     67 #define R3920_COP_0_PAGEMASK	$5
     68 #define R3920_COP_0_WIRED	$6
     69 #define	R3920_COP_0_CACHE	$7
     70 #define R3920_COP_0_TAG_LO	$20
     71 
     72 /*
     73  *	TLB entry
     74  *	3912 ... TLB entry is 64bits wide and R3000A compatible
     75  *	3922 ... TLB entry is 96bits wide
     76  */
     77 
     78 /*
     79  *	Index register
     80  *	3912 ... index field[8:12] (32 entry)
     81  */
     82 #define R3900_TLB_NUM_TLB_ENTRIES	32
     83 #define R3920_TLB_NUM_TLB_ENTRIES	64
     84 #undef MIPS1_TLB_NUM_TLB_ENTRIES
     85 #ifdef TX391X
     86 #define MIPS1_TLB_NUM_TLB_ENTRIES	R3900_TLB_NUM_TLB_ENTRIES
     87 #elif defined TX392X
     88 #define MIPS1_TLB_NUM_TLB_ENTRIES	R3920_TLB_NUM_TLB_ENTRIES
     89 #endif
     90 
     91 /*
     92  *	Config register (R3900 specific)
     93  */
     94 #define R3900_CONFIG_ICS_SHIFT		19
     95 #define R3900_CONFIG_ICS_MASK		0x00380000
     96 #define R3900_CONFIG_ICS_1KB		0x00000000
     97 #define R3900_CONFIG_ICS_2KB		0x00080000
     98 #define R3900_CONFIG_ICS_4KB		0x00100000
     99 #define R3900_CONFIG_ICS_8KB		0x00180000
    100 #define R3900_CONFIG_ICS_16KB		0x00200000
    101 
    102 #define R3900_CONFIG_DCS_SHIFT		16
    103 #define R3900_CONFIG_DCS_1KB		0x00000000
    104 #define R3900_CONFIG_DCS_2KB		0x00010000
    105 #define R3900_CONFIG_DCS_4KB		0x00020000
    106 #define R3900_CONFIG_DCS_8KB		0x00030000
    107 #define R3900_CONFIG_DCS_16KB		0x00040000
    108 
    109 
    110 #define R3900_CONFIG_DCS_MASK		0x00070000
    111 #define R3900_CONFIG_CWFON		0x00004000
    112 #define R3900_CONFIG_WBON		0x00002000
    113 #define R3900_CONFIG_RF_SHIFT		10
    114 #define R3900_CONFIG_RF_MASK		0x00000c00
    115 #define R3900_CONFIG_DOZE		0x00000200
    116 #define R3900_CONFIG_HALT		0x00000100
    117 #define R3900_CONFIG_LOCK		0x00000080
    118 #define R3900_CONFIG_ICE		0x00000020
    119 #define R3900_CONFIG_DCE		0x00000010
    120 #define R3900_CONFIG_IRSIZE_SHIFT	2
    121 #define R3900_CONFIG_IRSIZE_MASK	0x0000000c
    122 #define R3900_CONFIG_DRSIZE_SHIFT	0
    123 #define R3900_CONFIG_DRSIZE_MASK	0x00000003
    124 
    125 /*
    126  *	R3900 CACHE instruction (not MIPS3 cache op)
    127  */
    128 #define R3900_MIN_CACHE_SIZE		1024
    129 #define R3900_MAX_DCACHE_SIZE		(8 * 1024)
    130 #ifndef OP_CACHE
    131 #define OP_CACHE	057
    132 #endif
    133 #define R3900_CACHE(op, offset, base) \
    134 	.word (OP_CACHE << 26 | ((base) << 21) | ((op) << 16) | \
    135 	((offset) & 0xffff))
    136 #define R3900_CACHE_I_INDEXINVALIDATE	0
    137 #define R3900_CACHE_D_HITINVALIDATE	0x11
    138 
    139 #define	CPUREG_A0	4
    140 #define CPUREG_T0	8
    141 
    142 
    143