r3900regs.h revision 1.4.10.1
1 /* $NetBSD: r3900regs.h,v 1.4.10.1 2002/01/08 00:26:17 nathanw Exp $ */ 2 3 /*- 4 * Copyright (c) 1999, 2000 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by UCHIYAMA Yasushi. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /* 40 * [address space] 41 * kseg2 0xc0000000 - 0xfeffffff 42 * reserved 0xff000000 - 0xfffeffff 43 * kseg2 0xffff0000 - 0xffffffff 44 * -> vmparam.h VM_MAX_KERNEL_ADDRESS 45 */ 46 47 /* 48 * [cause register] 49 */ 50 #define R3900_CR_EXC_CODE MIPS3_CR_EXC_CODE /* five bits */ 51 #undef MIPS1_CR_EXC_CODE 52 #define MIPS1_CR_EXC_CODE R3900_CR_EXC_CODE 53 54 /* 55 * [status register] 56 * R3900 don't have PE, CM, PZ, SwC and IsC. 57 */ 58 #define R3900_SR_NMI 0x00100000 /* r3k PE position */ 59 #if 0 60 #undef MIPS1_PARITY_ERR 61 #undef MIPS1_CACHE_MISS 62 #undef MIPS1_PARITY_ZERO 63 #undef MIPS1_SWAP_CACHES 64 #undef MIPS1_ISOL_CACHES 65 #endif 66 67 /* 68 * [context register] 69 * - no changes. 70 */ 71 72 73 /* 74 * TX3900 Coprocessor 0 registers 75 */ 76 #define R3900_COP_0_CONFIG $3 77 #define R3900_COP_0_DEBUG $16 78 #define R3900_COP_0_DEPC $17 79 80 #define R3920_COP_0_PAGEMASK $5 81 #define R3920_COP_0_WIRED $6 82 #define R3920_COP_0_CACHE $7 83 #define R3920_COP_0_TAG_LO $20 84 85 /* 86 * TLB entry 87 * 3912 ... TLB entry is 64bits wide and R3000A compatible 88 * 3922 ... TLB entry is 96bits wide 89 */ 90 91 /* 92 * Index register 93 * 3912 ... index field[8:12] (32 entry) 94 */ 95 #define R3900_TLB_NUM_TLB_ENTRIES 32 96 #define R3920_TLB_NUM_TLB_ENTRIES 64 97 #undef MIPS1_TLB_NUM_TLB_ENTRIES 98 #ifdef TX391X 99 #define MIPS1_TLB_NUM_TLB_ENTRIES R3900_TLB_NUM_TLB_ENTRIES 100 #elif defined TX392X 101 #define MIPS1_TLB_NUM_TLB_ENTRIES R3920_TLB_NUM_TLB_ENTRIES 102 #endif 103 104 /* 105 * Config register (R3900 specific) 106 */ 107 #define R3900_CONFIG_ICS_SHIFT 19 108 #define R3900_CONFIG_ICS_MASK 0x00380000 109 #define R3900_CONFIG_ICS_1KB 0x00000000 110 #define R3900_CONFIG_ICS_2KB 0x00080000 111 #define R3900_CONFIG_ICS_4KB 0x00100000 112 #define R3900_CONFIG_ICS_8KB 0x00180000 113 #define R3900_CONFIG_ICS_16KB 0x00200000 114 115 #define R3900_CONFIG_DCS_SHIFT 16 116 #define R3900_CONFIG_DCS_1KB 0x00000000 117 #define R3900_CONFIG_DCS_2KB 0x00010000 118 #define R3900_CONFIG_DCS_4KB 0x00020000 119 #define R3900_CONFIG_DCS_8KB 0x00030000 120 #define R3900_CONFIG_DCS_16KB 0x00040000 121 122 #define R3900_CONFIG_DCS_MASK 0x00070000 123 #define R3900_CONFIG_CWFON 0x00004000 124 #define R3900_CONFIG_WBON 0x00002000 125 #define R3900_CONFIG_RF_SHIFT 10 126 #define R3900_CONFIG_RF_MASK 0x00000c00 127 #define R3900_CONFIG_DOZE 0x00000200 128 #define R3900_CONFIG_HALT 0x00000100 129 #define R3900_CONFIG_LOCK 0x00000080 130 #define R3900_CONFIG_ICE 0x00000020 131 #define R3900_CONFIG_DCE 0x00000010 132 #define R3900_CONFIG_IRSIZE_SHIFT 2 133 #define R3900_CONFIG_IRSIZE_MASK 0x0000000c 134 #define R3900_CONFIG_DRSIZE_SHIFT 0 135 #define R3900_CONFIG_DRSIZE_MASK 0x00000003 136 137 /* 138 * CACHE 139 */ 140 /* Cache size (limit) */ 141 /* R3900/R3920 */ 142 #define R3900_C_SIZE_MIN 1024 143 #define R3900_C_SIZE_MAX 8192 144 /* Cache line size */ 145 /* R3900 */ 146 #define R3900_C_LSIZE_I 16 147 #define R3900_C_LSIZE_D 4 148 /* R3920 */ 149 #define R3920_C_LSIZE_I 16 150 #define R3920_C_LSIZE_D 16 151 /* Cache operation */ 152 /* R3900 */ 153 #define R3900_C_IINV_I 0x00 154 #define R3900_C_IWBINV_D 0x01 155 #define R3900_C_ILRUC_I 0x04 156 #define R3900_C_ILRUC_D 0x05 157 #define R3900_C_ILCKC_D 0x09 /* R3900 only */ 158 #define R3900_C_HINV_D 0x11 159 /* R3920 */ 160 #define R3920_C_IINV_I 0x00 161 #define R3920_C_IWBINV_D 0x01 162 #define R3920_C_ILRUC_I 0x04 163 #define R3920_C_ILRUC_D 0x05 164 #define R3920_C_ILDTAG_I 0x0c /* R3920 only */ 165 #define R3920_C_ILDTAG_D 0x0d /* R3920 only */ 166 #define R3920_C_HINV_I 0x10 /* R3920 only */ 167 #define R3920_C_HINV_D 0x11 168 #define R3920_C_HWBINV_D 0x14 /* R3920 only */ 169 #define R3920_C_HWB_D 0x18 /* R3920 only */ 170 #define R3920_C_ISTTAG_I 0x1c /* R3920 only */ 171 #define R3920_C_ISTTAG_D 0x1d /* R3920 only */ 172
Indexes created Tue Oct 21 16:10:11 GMT 2025