apbus.c revision 1.11
1 /* $NetBSD: apbus.c,v 1.11 2015/03/25 11:25:10 macallan Exp $ */ 2 3 /*- 4 * Copyright (c) 2014 Michael Lorenz 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 17 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 18 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 19 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 20 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 21 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 22 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 23 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 24 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 25 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 26 * POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 /* catch-all for on-chip peripherals */ 30 31 #include <sys/cdefs.h> 32 __KERNEL_RCSID(0, "$NetBSD: apbus.c,v 1.11 2015/03/25 11:25:10 macallan Exp $"); 33 34 #include "locators.h" 35 #define _MIPS_BUS_DMA_PRIVATE 36 37 #include <sys/param.h> 38 #include <sys/bus.h> 39 #include <sys/device.h> 40 #include <sys/extent.h> 41 #include <sys/systm.h> 42 43 #include <mips/ingenic/ingenic_var.h> 44 #include <mips/ingenic/ingenic_regs.h> 45 46 #include "opt_ingenic.h" 47 48 static int apbus_match(device_t, cfdata_t, void *); 49 static void apbus_attach(device_t, device_t, void *); 50 static int apbus_print(void *, const char *); 51 static void apbus_bus_mem_init(bus_space_tag_t, void *); 52 53 CFATTACH_DECL_NEW(apbus, 0, apbus_match, apbus_attach, NULL, NULL); 54 55 static struct mips_bus_space apbus_mbst; 56 bus_space_tag_t apbus_memt = NULL; 57 58 struct mips_bus_dma_tag apbus_dmat = { 59 ._bounce_alloc_hi = 0x10000000, 60 ._dmamap_ops = _BUS_DMAMAP_OPS_INITIALIZER, 61 ._dmamem_ops = _BUS_DMAMEM_OPS_INITIALIZER, 62 ._dmatag_ops = _BUS_DMATAG_OPS_INITIALIZER, 63 }; 64 65 typedef struct apbus_dev { 66 const char *name; 67 bus_addr_t addr; 68 uint32_t irq; 69 } apbus_dev_t; 70 71 static const apbus_dev_t apbus_devs[] = { 72 { "dwctwo", JZ_DWC2_BASE, 21}, 73 { "ohci", JZ_OHCI_BASE, 5 }, 74 { "ehci", JZ_EHCI_BASE, 20}, 75 { "dme", JZ_DME_BASE, -1}, /* irq via gpio abuse */ 76 { "jzgpio", JZ_GPIO_A_BASE, 17}, 77 { "jzgpio", JZ_GPIO_B_BASE, 16}, 78 { "jzgpio", JZ_GPIO_C_BASE, 15}, 79 { "jzgpio", JZ_GPIO_D_BASE, 14}, 80 { "jzgpio", JZ_GPIO_E_BASE, 13}, 81 { "jzgpio", JZ_GPIO_F_BASE, 12}, 82 { "jziic", JZ_SMB0_BASE, 60}, 83 { "jziic", JZ_SMB1_BASE, 59}, 84 { "jziic", JZ_SMB2_BASE, 58}, 85 { "jziic", JZ_SMB3_BASE, 57}, 86 { "jziic", JZ_SMB4_BASE, 56}, 87 { "jzfb", -1, -1}, 88 { NULL, -1, -1} 89 }; 90 91 void 92 apbus_init(void) 93 { 94 static bool done = false; 95 if (done) 96 return; 97 done = true; 98 99 apbus_bus_mem_init(&apbus_mbst, NULL); 100 apbus_memt = &apbus_mbst; 101 } 102 103 int 104 apbus_match(device_t parent, cfdata_t match, void *aux) 105 { 106 struct mainbusdev { 107 const char *md_name; 108 } *aa = aux; 109 if (strcmp(aa->md_name, "apbus") == 0) return 1; 110 return 0; 111 } 112 113 void 114 apbus_attach(device_t parent, device_t self, void *aux) 115 { 116 uint32_t reg, mpll, m, n, p, mclk, pclk, pdiv; 117 aprint_normal("\n"); 118 119 /* should have been called early on */ 120 apbus_init(); 121 122 #ifdef INGENIC_DEBUG 123 printf("core ctrl: %08x\n", MFC0(12, 2)); 124 printf("core status: %08x\n", MFC0(12, 3)); 125 printf("REIM: %08x\n", MFC0(12, 4)); 126 printf("ID: %08x\n", MFC0(15, 1)); 127 #endif 128 /* assuming we're using MPLL */ 129 mpll = readreg(JZ_CPMPCR); 130 m = (mpll & JZ_PLLM_M) >> JZ_PLLM_S; 131 n = (mpll & JZ_PLLN_M) >> JZ_PLLN_S; 132 p = (mpll & JZ_PLLP_M) >> JZ_PLLP_S; 133 134 /* assuming 48MHz EXTCLK */ 135 mclk = (48000 * (m + 1) / (n + 1)) / (p + 1); 136 137 reg = readreg(JZ_CPCCR); 138 pdiv = (reg & JZ_PDIV_M) >> JZ_PDIV_S; 139 pclk = mclk / pdiv; 140 #ifdef INGENIC_DEBUG 141 printf("mclk %d kHz\n", mclk); 142 printf("pclk %d kHz\n", pclk); 143 #endif 144 145 /* enable clocks */ 146 reg = readreg(JZ_CLKGR1); 147 reg &= ~(1 << 0); /* SMB3 clock */ 148 reg &= ~(1 << 8); /* OTG1 clock */ 149 reg &= ~(1 << 11); /* AHB_MON clock */ 150 reg &= ~(1 << 12); /* SMB4 clock */ 151 writereg(JZ_CLKGR1, reg); 152 153 reg = readreg(JZ_CLKGR0); 154 reg &= ~(1 << 2); /* OTG0 clock */ 155 reg &= ~(1 << 5); /* SMB0 clock */ 156 reg &= ~(1 << 6); /* SMB1 clock */ 157 reg &= ~(1 << 24); /* UHC clock */ 158 reg &= ~(1 << 25); /* SMB2 clock */ 159 writereg(JZ_CLKGR0, reg); 160 161 /* wake up the USB part */ 162 reg = readreg(JZ_OPCR); 163 reg |= OPCR_SPENDN0 | OPCR_SPENDN1; 164 writereg(JZ_OPCR, reg); 165 166 /* setup GPIOs for I2C buses */ 167 /* iic0 */ 168 gpio_as_dev0(3, 30); 169 gpio_as_dev0(3, 31); 170 /* iic1 */ 171 gpio_as_dev0(4, 30); 172 gpio_as_dev0(4, 31); 173 /* iic2 */ 174 gpio_as_dev2(5, 16); 175 gpio_as_dev2(5, 17); 176 /* iic3 */ 177 gpio_as_dev1(3, 10); 178 gpio_as_dev1(3, 11); 179 /* iic4 */ 180 /* make sure these aren't SMB4 */ 181 gpio_as_dev3(4, 3); 182 gpio_as_dev3(4, 4); 183 /* these are supposed to be connected to the RTC */ 184 gpio_as_dev1(4, 12); 185 gpio_as_dev1(4, 13); 186 /* these can be DDC2 or SMB4, set them to DDC2 */ 187 gpio_as_dev0(5, 24); 188 gpio_as_dev0(5, 25); 189 190 #ifdef INGENIC_DEBUG 191 printf("JZ_CLKGR0 %08x\n", readreg(JZ_CLKGR0)); 192 printf("JZ_CLKGR1 %08x\n", readreg(JZ_CLKGR1)); 193 printf("JZ_SPCR0 %08x\n", readreg(JZ_SPCR0)); 194 printf("JZ_SPCR1 %08x\n", readreg(JZ_SPCR1)); 195 printf("JZ_SRBC %08x\n", readreg(JZ_SRBC)); 196 printf("JZ_OPCR %08x\n", readreg(JZ_OPCR)); 197 printf("JZ_UHCCDR %08x\n", readreg(JZ_UHCCDR)); 198 #endif 199 200 for (const apbus_dev_t *adv = apbus_devs; adv->name != NULL; adv++) { 201 struct apbus_attach_args aa; 202 aa.aa_name = adv->name; 203 aa.aa_addr = adv->addr; 204 aa.aa_irq = adv->irq; 205 aa.aa_dmat = &apbus_dmat; 206 aa.aa_bst = apbus_memt; 207 aa.aa_pclk = pclk; 208 209 (void) config_found_ia(self, "apbus", &aa, apbus_print); 210 } 211 } 212 213 int 214 apbus_print(void *aux, const char *pnp) 215 { 216 struct apbus_attach_args *aa = aux; 217 218 if (pnp) { 219 aprint_normal("%s at %s", aa->aa_name, pnp); 220 } 221 if (aa->aa_addr != -1) 222 aprint_normal(" addr 0x%" PRIxBUSADDR, aa->aa_addr); 223 if ((pnp == NULL) && (aa->aa_irq != -1)) 224 aprint_normal(" irq %d", aa->aa_irq); 225 return (UNCONF); 226 } 227 228 #define CHIP apbus 229 #define CHIP_MEM /* defined */ 230 #define CHIP_W1_BUS_START(v) 0x10000000UL 231 #define CHIP_W1_BUS_END(v) 0x20000000UL 232 #define CHIP_W1_SYS_START(v) 0x10000000UL 233 #define CHIP_W1_SYS_END(v) 0x20000000UL 234 235 #include <mips/mips/bus_space_alignstride_chipdep.c> 236
Indexes created Wed Oct 22 06:10:02 GMT 2025