ingenic_regs.h revision 1.12
1 /* $NetBSD: ingenic_regs.h,v 1.12 2015/03/25 11:23:26 macallan Exp $ */ 2 3 /*- 4 * Copyright (c) 2014 Michael Lorenz 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 17 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 18 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 19 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 20 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 21 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 22 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 23 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 24 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 25 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 26 * POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 #include <mips/locore.h> 30 31 #ifndef INGENIC_REGS_H 32 #define INGENIC_REGS_H 33 34 /* UARTs, mostly 16550 compatible with 32bit spaced registers */ 35 #define JZ_UART0 0x10030000 36 #define JZ_UART1 0x10031000 37 #define JZ_UART2 0x10032000 38 #define JZ_UART3 0x10033000 39 #define JZ_UART4 0x10034000 40 41 /* watchdog */ 42 #define JZ_WDOG_TDR 0x10002000 /* compare */ 43 #define JZ_WDOG_TCER 0x10002004 44 #define TCER_ENABLE 0x01 /* enable counter */ 45 #define JZ_WDOG_TCNT 0x10002008 /* 16bit up count */ 46 #define JZ_WDOG_TCSR 0x1000200c 47 #define TCSR_PCK_EN 0x01 /* PCLK */ 48 #define TCSR_RTC_EN 0x02 /* RTCCLK - 32.768kHz */ 49 #define TCSR_EXT_EN 0x04 /* EXTCLK - 48MHz */ 50 #define TCSR_PRESCALE_M 0x38 51 #define TCSR_DIV_1 0x00 52 #define TCSR_DIV_4 0x08 53 #define TCSR_DIV_16 0x10 54 #define TCSR_DIV_64 0x18 55 #define TCSR_DIV_256 0x20 56 #define TCSR_DIV_1024 0x28 57 58 /* timers and PWMs */ 59 #define JZ_TC_TER 0x10002010 /* TC enable reg, ro */ 60 #define JZ_TC_TESR 0x10002014 /* TC enable set reg. */ 61 #define TESR_TCST0 0x0001 /* enable counter 0 */ 62 #define TESR_TCST1 0x0002 /* enable counter 1 */ 63 #define TESR_TCST2 0x0004 /* enable counter 2 */ 64 #define TESR_TCST3 0x0008 /* enable counter 3 */ 65 #define TESR_TCST4 0x0010 /* enable counter 4 */ 66 #define TESR_TCST5 0x0020 /* enable counter 5 */ 67 #define TESR_TCST6 0x0040 /* enable counter 6 */ 68 #define TESR_TCST7 0x0080 /* enable counter 7 */ 69 #define TESR_OST 0x8000 /* enable OST */ 70 #define JZ_TC_TECR 0x10002018 /* TC enable clear reg. */ 71 #define JZ_TC_TFR 0x10002020 72 #define TFR_FFLAG0 0x00000001 /* channel 0 */ 73 #define TFR_FFLAG1 0x00000002 /* channel 1 */ 74 #define TFR_FFLAG2 0x00000004 /* channel 2 */ 75 #define TFR_FFLAG3 0x00000008 /* channel 3 */ 76 #define TFR_FFLAG4 0x00000010 /* channel 4 */ 77 #define TFR_FFLAG5 0x00000020 /* channel 5 */ 78 #define TFR_FFLAG6 0x00000040 /* channel 6 */ 79 #define TFR_FFLAG7 0x00000080 /* channel 7 */ 80 #define TFR_OSTFLAG 0x00008000 /* OS timer */ 81 #define JZ_TC_TFSR 0x10002024 /* timer flag set */ 82 #define JZ_TC_TFCR 0x10002028 /* timer flag clear */ 83 #define JZ_TC_TMR 0x10002030 /* timer flag mask */ 84 #define JZ_TC_TMSR 0x10002034 /* timer flag mask set */ 85 #define JZ_TC_TMCR 0x10002038 /* timer flag mask clear*/ 86 87 #define JZ_TC_TDFR(n) (0x10002040 + (n * 0x10)) /* FULL compare */ 88 #define JZ_TC_TDHR(n) (0x10002044 + (n * 0x10)) /* HALF compare */ 89 #define JZ_TC_TCNT(n) (0x10002048 + (n * 0x10)) /* count */ 90 91 #define JZ_TC_TCSR(n) (0x1000204c + (n * 0x10)) 92 /* same bits as in JZ_WDOG_TCSR */ 93 94 /* operating system timer */ 95 #define JZ_OST_DATA 0x100020e0 /* compare */ 96 #define JZ_OST_CNT_LO 0x100020e4 97 #define JZ_OST_CNT_HI 0x100020e8 98 #define JZ_OST_CTRL 0x100020ec 99 #define OSTC_PCK_EN 0x0001 /* use PCLK */ 100 #define OSTC_RTC_EN 0x0002 /* use RTCCLK */ 101 #define OSTC_EXT_EN 0x0004 /* use EXTCLK */ 102 #define OSTC_PRESCALE_M 0x0038 103 #define OSTC_DIV_1 0x0000 104 #define OSTC_DIV_4 0x0008 105 #define OSTC_DIV_16 0x0010 106 #define OSTC_DIV_64 0x0018 107 #define OSTC_DIV_256 0x0020 108 #define OSTC_DIV_1024 0x0028 109 #define OSTC_SHUTDOWN 0x0200 110 #define OSTC_MODE 0x8000 /* 0 - reset to 0 when = OST_DATA */ 111 #define JZ_OST_CNT_U32 0x100020fc /* copy of CNT_HI when reading CNT_LO */ 112 113 static inline void 114 writereg(uint32_t reg, uint32_t val) 115 { 116 *(int32_t *)MIPS_PHYS_TO_KSEG1(reg) = val; 117 wbflush(); 118 } 119 120 static inline uint32_t 121 readreg(uint32_t reg) 122 { 123 wbflush(); 124 return *(int32_t *)MIPS_PHYS_TO_KSEG1(reg); 125 } 126 127 /* extra CP0 registers */ 128 static inline uint32_t 129 MFC0(uint32_t r, uint32_t s) 130 { 131 uint32_t ret = 0x12345678; 132 133 __asm volatile("mfc0 %0, $%1, %2; nop;" : "=r"(ret) : "i"(r), "i"(s)); 134 return ret; 135 } 136 137 #define MTC0(v, r, s) __asm volatile("mtc0 %0, $%1, %2; nop;" :: "r"(v), "i"(r), "i"(s)) 138 139 #define CP0_CORE_CTRL 12 /* select 2 */ 140 #define CC_SW_RST0 1 /* reset core 0 */ 141 #define CC_SW_RST1 2 /* reset core 1 */ 142 #define CC_RPC0 0x100 /* dedicater reset entry core 0 */ 143 #define CC_RPC1 0x200 /* -- || -- core 1 */ 144 #define CC_SLEEP0M 0x10000 /* mask sleep core 0 */ 145 #define CC_SLEEP1M 0x20000 /* mask sleep core 1 */ 146 147 /* cores status, 12 select 3 */ 148 #define CS_MIRQ0_P 0x00001 /* mailbox IRQ for 0 pending */ 149 #define CS_MIRQ1_P 0x00002 /* || core 1 */ 150 #define CS_IRQ0_P 0x00100 /* peripheral IRQ for core 0 */ 151 #define CS_IRQ1_P 0x00200 /* || core 1 */ 152 #define CS_SLEEP0 0x10000 /* core 0 sleeping */ 153 #define CS_SLEEP1 0x20000 /* core 1 sleeping */ 154 155 /* cores reset entry & IRQ masks - 12 select 4 */ 156 #define REIM_MIRQ0_M 0x00001 /* allow mailbox IRQ for core 0 */ 157 #define REIM_MIRQ1_M 0x00002 /* allow mailbox IRQ for core 1 */ 158 #define REIM_IRQ0_M 0x00100 /* allow peripheral IRQ for core 0 */ 159 #define REIM_IRQ1_M 0x00200 /* allow peripheral IRQ for core 1 */ 160 #define REIM_ENTRY_M 0xffff0000 /* reset exception entry if RPCn=1 */ 161 162 #define CP0_CORE_MBOX 20 /* select 0 for core 0, 1 for 1 */ 163 164 /* power management */ 165 #define JZ_CPCCR 0x10000000 /* Clock Control Register */ 166 #define JZ_PDIV_M 0x000f0000 /* PCLK divider mask */ 167 #define JZ_PDIV_S 16 /* PCLK divider shift */ 168 #define JZ_CPMPCR 0x00000014 /* MPLL */ 169 #define JZ_PLLM_S 19 /* PLL multiplier shift */ 170 #define JZ_PLLM_M 0xfff80000 /* PLL multiplier mask */ 171 #define JZ_PLLN_S 13 /* PLL divider shift */ 172 #define JZ_PLLN_M 0x0007e000 /* PLL divider mask */ 173 #define JZ_PLLP_S 9 /* PLL postdivider shift */ 174 #define JZ_PLLP_M 0x00001700 /* PLL postdivider mask */ 175 #define JZ_PLLON 0x00000010 /* PLL is on and stable */ 176 #define JZ_PLLBP 0x00000002 /* PLL bypass */ 177 #define JZ_PLLEN 0x00000001 /* PLL enable */ 178 #define JZ_CLKGR0 0x10000020 /* CLocK Gating Registers */ 179 #define JZ_OPCR 0x10000024 /* Oscillator Power Control Reg. */ 180 #define OPCR_IDLE_DIS 0x80000000 /* don't stop CPU clk on idle */ 181 #define OPCR_GPU_CLK_ST 0x40000000 /* stop GPU clock */ 182 #define OPCR_L2CM_M 0x0c000000 183 #define OPCR_L2CM_ON 0x00000000 /* L2 stays on in sleep */ 184 #define OPCR_L2CM_RET 0x04000000 /* L2 retention mode in sleep */ 185 #define OPCR_L2CM_OFF 0x08000000 /* L2 powers down in sleep */ 186 #define OPCR_SPENDN0 0x00000080 /* OTG port forced down */ 187 #define OPCR_SPENDN1 0x00000040 /* UHC port forced down */ 188 #define OPCR_BUS_MODE 0x00000020 /* 1 - bursts */ 189 #define OPCR_O1SE 0x00000010 /* EXTCLK on in sleep */ 190 #define OPCR_PD 0x00000008 /* P0 down in sleep */ 191 #define OPCR_ERCS 0x00000004 /* 1 RTCCLK, 0 EXTCLK/512 */ 192 #define OPCR_CPU_MODE 0x00000002 /* 1 access 'accelerated' */ 193 #define OPCR_OSE 0x00000001 /* disable EXTCLK */ 194 #define JZ_CLKGR1 0x10000028 /* CLocK Gating Registers */ 195 #define JZ_USBPCR 0x1000003c 196 #define PCR_USB_MODE 0x80000000 /* 1 - otg */ 197 #define PCR_AVLD_REG 0x40000000 198 #define PCR_IDPULLUP_MASK 0x30000000 199 #define PCR_INCR_MASK 0x08000000 200 #define PCR_TCRISETUNE 0x04000000 201 #define PCR_COMMONONN 0x02000000 202 #define PCR_VBUSVLDEXT 0x01000000 203 #define PCR_VBUSVLDEXTSEL 0x00800000 204 #define PCR_POR 0x00400000 205 #define PCR_SIDDQ 0x00200000 206 #define PCR_OTG_DISABLE 0x00100000 207 #define PCR_COMPDISTN_M 0x000e0000 208 #define PCR_OTGTUNE 0x0001c000 209 #define PCR_SQRXTUNE 0x00003800 210 #define PCR_TXFSLSTUNE 0x00000780 211 #define PCR_TXPREEMPHTUNE 0x00000040 212 #define PCR_TXHSXVTUNE 0x00000030 213 #define PCR_TXVREFTUNE 0x0000000f 214 #define JZ_USBRDT 0x10000040 /* Reset Detect Timer Register */ 215 #define JZ_USBPCR1 0x10000048 216 #define PCR_SYNOPSYS 0x10000000 /* Mentor mode otherwise */ 217 #define PCR_REFCLK_CORE 0x0c000000 218 #define PCR_REFCLK_XO25 0x04000000 219 #define PCR_REFCLK_CO 0x00000000 220 #define PCR_CLK_M 0x03000000 /* clock */ 221 #define PCR_CLK_192 0x03000000 /* 19.2MHz */ 222 #define PCR_CLK_48 0x02000000 /* 48MHz */ 223 #define PCR_CLK_24 0x01000000 /* 24MHz */ 224 #define PCR_CLK_12 0x00000000 /* 12MHz */ 225 #define PCR_DMPD1 0x00800000 /* pull down D- on port 1 */ 226 #define PCR_DPPD1 0x00400000 /* pull down D+ on port 1 */ 227 #define PCR_PORT0_RST 0x00200000 /* port 0 reset */ 228 #define PCR_PORT1_RST 0x00100000 /* port 1 reset */ 229 #define PCR_WORD_I_F0 0x00080000 /* 1: 16bit/30M, 8/60 otherw. */ 230 #define PCR_WORD_I_F1 0x00040000 /* same for port 1 */ 231 #define PCR_COMPDISTUNE 0x00038000 /* disconnect threshold */ 232 #define PCR_SQRXTUNE1 0x00007000 /* squelch threshold */ 233 #define PCR_TXFSLSTUNE1 0x00000f00 /* FS/LS impedance adj. */ 234 #define PCR_TXPREEMPH 0x00000080 /* HS transm. pre-emphasis */ 235 #define PCR_TXHSXVTUNE1 0x00000060 /* dp/dm voltage adj. */ 236 #define PCR_TXVREFTUNE1 0x00000017 /* HS DC voltage adj. */ 237 #define PCR_TXRISETUNE1 0x00000001 /* rise/fall wave adj. */ 238 239 #define JZ_UHCCDR 0x1000006c /* UHC Clock Divider Register */ 240 #define JZ_SPCR0 0x100000b8 /* SRAM Power Control Registers */ 241 #define JZ_SPCR1 0x100000bc 242 #define JZ_SRBC 0x100000c4 /* Soft Reset & Bus Control */ 243 244 /* interrupt controller */ 245 #define JZ_ICSR0 0x10001000 /* raw IRQ line status */ 246 #define JZ_ICMR0 0x10001004 /* IRQ mask, 1 masks IRQ */ 247 #define JZ_ICMSR0 0x10001008 /* sets bits in mask register */ 248 #define JZ_ICMCR0 0x1000100c /* clears bits in mask register */ 249 #define JZ_ICPR0 0x10001010 /* line status after masking */ 250 251 #define JZ_ICSR1 0x10001020 /* raw IRQ line status */ 252 #define JZ_ICMR1 0x10001024 /* IRQ mask, 1 masks IRQ */ 253 #define JZ_ICMSR1 0x10001028 /* sets bits in mask register */ 254 #define JZ_ICMCR1 0x1000102c /* clears bits in maks register */ 255 #define JZ_ICPR1 0x10001030 /* line status after masking */ 256 257 #define JZ_DSR0 0x10001034 /* source for PDMA */ 258 #define JZ_DMR0 0x10001038 /* mask for PDMA */ 259 #define JZ_DPR0 0x1000103c /* pending for PDMA */ 260 261 #define JZ_DSR1 0x10001040 /* source for PDMA */ 262 #define JZ_DMR1 0x10001044 /* mask for PDMA */ 263 #define JZ_DPR1 0x10001048 /* pending for PDMA */ 264 265 /* memory controller */ 266 #define JZ_DMMAP0 0x13010024 267 #define JZ_DMMAP1 0x13010028 268 #define DMMAP_BASE 0x0000ff00 /* base PADDR of memory chunk */ 269 #define DMMAP_MASK 0x000000ff /* mask which bits of PADDR are 270 * constant */ 271 /* USB controllers */ 272 #define JZ_EHCI_BASE 0x13490000 273 #define JZ_OHCI_BASE 0x134a0000 274 #define JZ_DWC2_BASE 0x13500000 275 276 /* Ethernet */ 277 #define JZ_DME_BASE 0x16000000 278 #define JZ_DME_IO 0 279 #define JZ_DME_DATA 2 280 281 /* GPIO */ 282 #define JZ_GPIO_A_BASE 0x10010000 283 #define JZ_GPIO_B_BASE 0x10010100 284 #define JZ_GPIO_C_BASE 0x10010200 285 #define JZ_GPIO_D_BASE 0x10010300 286 #define JZ_GPIO_E_BASE 0x10010400 287 #define JZ_GPIO_F_BASE 0x10010500 288 289 /* GPIO registers per port */ 290 #define JZ_GPIO_PIN 0x00000000 /* pin level register */ 291 /* 0 - normal gpio, 1 - interrupt */ 292 #define JZ_GPIO_INT 0x00000010 /* interrupt register */ 293 #define JZ_GPIO_INTS 0x00000014 /* interrupt set register */ 294 #define JZ_GPIO_INTC 0x00000018 /* interrupt clear register */ 295 /* 296 * INT == 1: 1 disables interrupt 297 * INT == 0: device select, see below 298 */ 299 #define JZ_GPIO_MASK 0x00000020 /* port mask register */ 300 #define JZ_GPIO_MASKS 0x00000024 /* port mask set register */ 301 #define JZ_GPIO_MASKC 0x00000028 /* port mask clear register */ 302 /* 303 * INT == 1: 0 - level triggered, 1 - edge triggered 304 * INT == 0: 0 - device select, see below 305 */ 306 #define JZ_GPIO_PAT1 0x00000030 /* pattern 1 register */ 307 #define JZ_GPIO_PAT1S 0x00000034 /* pattern 1 set register */ 308 #define JZ_GPIO_PAT1C 0x00000038 /* pattern 1 clear register */ 309 /* 310 * INT == 1: 311 * PAT1 == 0: 0 - trigger on low, 1 - trigger on high 312 * PAT1 == 1: 0 - trigger on falling edge, 1 - trigger on rising edge 313 * INT == 0: 314 * MASK == 0: 315 * PAT1 == 0: 0 - device 0, 1 - device 1 316 * PAT1 == 1: 0 - device 2, 1 - device 3 317 * MASK == 1: 318 * PAT1 == 0: set gpio output 319 * PAT1 == 1: pin is input 320 */ 321 #define JZ_GPIO_PAT0 0x00000040 /* pattern 0 register */ 322 #define JZ_GPIO_PAT0S 0x00000044 /* pattern 0 set register */ 323 #define JZ_GPIO_PAT0C 0x00000048 /* pattern 0 clear register */ 324 /* 1 - interrupt happened */ 325 #define JZ_GPIO_FLAG 0x00000050 /* flag register */ 326 #define JZ_GPIO_FLAGC 0x00000058 /* flag clear register */ 327 /* 1 - disable pull up/down resistors */ 328 #define JZ_GPIO_DPULL 0x00000070 /* pull disable register */ 329 #define JZ_GPIO_DPULLS 0x00000074 /* pull disable set register */ 330 #define JZ_GPIO_DPULLC 0x00000078 /* pull disable clear register */ 331 /* the following are uncommented in the manual */ 332 #define JZ_GPIO_DRVL 0x00000080 /* drive low register */ 333 #define JZ_GPIO_DRVLS 0x00000084 /* drive low set register */ 334 #define JZ_GPIO_DRVLC 0x00000088 /* drive low clear register */ 335 #define JZ_GPIO_DIR 0x00000090 /* direction register */ 336 #define JZ_GPIO_DIRS 0x00000094 /* direction register */ 337 #define JZ_GPIO_DIRC 0x00000098 /* direction register */ 338 #define JZ_GPIO_DRVH 0x000000a0 /* drive high register */ 339 #define JZ_GPIO_DRVHS 0x000000a4 /* drive high set register */ 340 #define JZ_GPIO_DRVHC 0x000000a8 /* drive high clear register */ 341 342 static inline void 343 gpio_as_output(uint32_t g, int pin) 344 { 345 uint32_t mask = 1 << pin; 346 uint32_t reg = JZ_GPIO_A_BASE + (g << 8); 347 348 writereg(reg + JZ_GPIO_INTC, mask); /* use as gpio */ 349 writereg(reg + JZ_GPIO_MASKS, mask); 350 writereg(reg + JZ_GPIO_PAT1C, mask); /* make output */ 351 } 352 353 static inline void 354 gpio_set(uint32_t g, int pin, int level) 355 { 356 uint32_t mask = 1 << pin; 357 uint32_t reg = JZ_GPIO_A_BASE + (g << 8); 358 359 reg += (level == 0) ? JZ_GPIO_PAT0C : JZ_GPIO_PAT0S; 360 writereg(reg, mask); 361 } 362 363 static inline void 364 gpio_as_dev0(uint32_t g, int pin) 365 { 366 uint32_t mask = 1 << pin; 367 uint32_t reg = JZ_GPIO_A_BASE + (g << 8); 368 369 writereg(reg + JZ_GPIO_INTC, mask); /* use as gpio */ 370 writereg(reg + JZ_GPIO_MASKC, mask); /* device mode */ 371 writereg(reg + JZ_GPIO_PAT1C, mask); /* select 0 */ 372 writereg(reg + JZ_GPIO_PAT0C, mask); 373 } 374 375 static inline void 376 gpio_as_dev1(uint32_t g, int pin) 377 { 378 uint32_t mask = 1 << pin; 379 uint32_t reg = JZ_GPIO_A_BASE + (g << 8); 380 381 writereg(reg + JZ_GPIO_INTC, mask); /* use as gpio */ 382 writereg(reg + JZ_GPIO_MASKC, mask); /* device mode */ 383 writereg(reg + JZ_GPIO_PAT1C, mask); /* select 1 */ 384 writereg(reg + JZ_GPIO_PAT0S, mask); 385 } 386 387 static inline void 388 gpio_as_dev2(uint32_t g, int pin) 389 { 390 uint32_t mask = 1 << pin; 391 uint32_t reg = JZ_GPIO_A_BASE + (g << 8); 392 393 writereg(reg + JZ_GPIO_INTC, mask); /* use as gpio */ 394 writereg(reg + JZ_GPIO_MASKC, mask); /* device mode */ 395 writereg(reg + JZ_GPIO_PAT1S, mask); /* select 2 */ 396 writereg(reg + JZ_GPIO_PAT0C, mask); 397 } 398 399 static inline void 400 gpio_as_dev3(uint32_t g, int pin) 401 { 402 uint32_t mask = 1 << pin; 403 uint32_t reg = JZ_GPIO_A_BASE + (g << 8); 404 405 writereg(reg + JZ_GPIO_INTC, mask); /* use as gpio */ 406 writereg(reg + JZ_GPIO_MASKC, mask); /* device mode */ 407 writereg(reg + JZ_GPIO_PAT1S, mask); /* select 3 */ 408 writereg(reg + JZ_GPIO_PAT0S, mask); 409 } 410 411 static inline void 412 gpio_as_intr_level(uint32_t g, int pin) 413 { 414 uint32_t mask = 1 << pin; 415 uint32_t reg = JZ_GPIO_A_BASE + (g << 8); 416 417 writereg(reg + JZ_GPIO_MASKS, mask); /* mask it */ 418 writereg(reg + JZ_GPIO_INTS, mask); /* use as interrupt */ 419 writereg(reg + JZ_GPIO_PAT1C, mask); /* level trigger */ 420 writereg(reg + JZ_GPIO_PAT0S, mask); /* trigger on high */ 421 writereg(reg + JZ_GPIO_FLAGC, mask); /* clear it */ 422 writereg(reg + JZ_GPIO_MASKC, mask); /* enable it */ 423 } 424 425 /* I2C / SMBus */ 426 #define JZ_SMB0_BASE 0x10050000 427 #define JZ_SMB1_BASE 0x10051000 428 #define JZ_SMB2_BASE 0x10052000 429 #define JZ_SMB3_BASE 0x10053000 430 #define JZ_SMB4_BASE 0x10054000 431 432 /* SMBus register offsets, per port */ 433 #define JZ_SMBCON 0x00 /* SMB control */ 434 #define JZ_STPHLD 0x80 /* Stop Hold Enable bit */ 435 #define JZ_SLVDIS 0x40 /* 1 - slave disabled */ 436 #define JZ_REST 0x20 /* 1 - allow RESTART */ 437 #define JZ_MATP 0x10 /* 1 - enable 10bit addr. for master */ 438 #define JZ_SATP 0x08 /* 1 - enable 10bit addr. for slave */ 439 #define JZ_SPD_M 0x06 /* bus speed control */ 440 #define JZ_SPD_100KB 0x02 /* 100kBit/s mode */ 441 #define JZ_SPD_400KB 0x04 /* 400kBit/s mode */ 442 #define JZ_MD 0x01 /* enable master */ 443 #define JZ_SMBTAR 0x04 /* SMB target address */ 444 #define JZ_SMATP 0x1000 /* enable 10bit master addr */ 445 #define JZ_SPECIAL 0x0800 /* 1 - special command */ 446 #define JZ_START 0x0400 /* 1 - send START */ 447 #define JZ_SMBTAR_M 0x03ff /* target address */ 448 #define JZ_SMBSAR 0x08 /* SMB slave address */ 449 #define JZ_SMBDC 0x10 /* SMB data buffer and command */ 450 #define JZ_CMD 0x100 /* 1 - read, 0 - write */ 451 #define JZ_DATA 0x0ff 452 #define JZ_SMBSHCNT 0x14 /* Standard speed SMB SCL high count */ 453 #define JZ_SMBSLCNT 0x18 /* Standard speed SMB SCL low count */ 454 #define JZ_SMBFHCNT 0x1C /* Fast speed SMB SCL high count */ 455 #define JZ_SMBFLCNT 0x20 /* Fast speed SMB SCL low count */ 456 #define JZ_SMBINTST 0x2C /* SMB Interrupt Status */ 457 #define JZ_ISTT 0x400 /* START or RESTART occured */ 458 #define JZ_ISTP 0x200 /* STOP occured */ 459 #define JZ_TXABT 0x40 /* ABORT occured */ 460 #define JZ_TXEMP 0x10 /* TX FIFO is low */ 461 #define JZ_TXOF 0x08 /* TX FIFO is high */ 462 #define JZ_RXFL 0x04 /* RX FIFO is low */ 463 #define JZ_RXOF 0x02 /* RX FIFO is high */ 464 #define JZ_RXUF 0x01 /* RX FIFO underflow */ 465 #define JZ_SMBINTM 0x30 /* SMB Interrupt Mask */ 466 #define JZ_SMBRXTL 0x38 /* SMB RxFIFO Threshold */ 467 #define JZ_SMBTXTL 0x3C /* SMB TxFIFO Threshold */ 468 #define JZ_SMBCINT 0x40 /* Clear Interrupts */ 469 #define JZ_CLEARALL 0x01 470 #define JZ_SMBCRXUF 0x44 /* Clear RXUF Interrupt */ 471 #define JZ_SMBCRXOF 0x48 /* Clear RX_OVER Interrupt */ 472 #define JZ_SMBCTXOF 0x4C /* Clear TX_OVER Interrupt */ 473 #define JZ_SMBCRXREQ 0x50 /* Clear RDREQ Interrupt */ 474 #define JZ_SMBCTXABT 0x54 /* Clear TX_ABRT Interrupt */ 475 #define JZ_SMBCRXDN 0x58 /* Clear RX_DONE Interrupt */ 476 #define JZ_SMBCACT 0x5c /* Clear ACTIVITY Interrupt */ 477 #define JZ_SMBCSTP 0x60 /* Clear STOP Interrupt */ 478 #define JZ_SMBCSTT 0x64 /* Clear START Interrupt */ 479 #define JZ_SMBCGC 0x68 /* Clear GEN_CALL Interrupt */ 480 #define JZ_SMBENB 0x6C /* SMB Enable */ 481 #define JZ_ENABLE 0x01 482 #define JZ_SMBST 0x70 /* SMB Status register */ 483 #define JZ_SLVACT 0x40 /* slave is active */ 484 #define JZ_MSTACT 0x20 /* master is active */ 485 #define JZ_RFF 0x10 /* RX FIFO is full */ 486 #define JZ_RFNE 0x08 /* RX FIFO not empty */ 487 #define JZ_TFE 0x04 /* TX FIFO is empty */ 488 #define JZ_TFNF 0x02 /* TX FIFO is not full */ 489 #define JZ_ACT 0x01 /* JZ_SLVACT | JZ_MSTACT */ 490 #define JZ_SMBABTSRC 0x80 /* SMB Transmit Abort Status Register */ 491 #define JZ_SMBDMACR 0x88 /* DMA Control Register */ 492 #define JZ_SMBDMATDL 0x8c /* DMA Transmit Data Level */ 493 #define JZ_SMBDMARDL 0x90 /* DMA Receive Data Level */ 494 #define JZ_SMBSDASU 0x94 /* SMB SDA Setup Register */ 495 #define JZ_SMBACKGC 0x98 /* SMB ACK General Call Register */ 496 #define JZ_SMBENBST 0x9C /* SMB Enable Status Register */ 497 #define JZ_SMBSDAHD 0xD0 /* SMB SDA HolD time Register */ 498 #define JZ_HDENB 0x100 /* enable hold time */ 499 500 #endif /* INGENIC_REGS_H */ 501
Indexes created Fri Oct 03 02:09:57 GMT 2025