ingenic_regs.h revision 1.7
1 /* $NetBSD: ingenic_regs.h,v 1.7 2015/03/07 15:36:16 macallan Exp $ */ 2 3 /*- 4 * Copyright (c) 2014 Michael Lorenz 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 17 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 18 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 19 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 20 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 21 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 22 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 23 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 24 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 25 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 26 * POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 #include <mips/locore.h> 30 31 #ifndef INGENIC_REGS_H 32 #define INGENIC_REGS_H 33 34 /* UARTs, mostly 16550 compatible with 32bit spaced registers */ 35 #define JZ_UART0 0x10030000 36 #define JZ_UART1 0x10031000 37 #define JZ_UART2 0x10032000 38 #define JZ_UART3 0x10033000 39 #define JZ_UART4 0x10034000 40 41 /* watchdog */ 42 #define JZ_WDOG_TDR 0x10002000 /* compare */ 43 #define JZ_WDOG_TCER 0x10002004 44 #define TCER_ENABLE 0x01 /* enable counter */ 45 #define JZ_WDOG_TCNT 0x10002008 /* 16bit up count */ 46 #define JZ_WDOG_TCSR 0x1000200c 47 #define TCSR_PCK_EN 0x01 /* PCLK */ 48 #define TCSR_RTC_EN 0x02 /* RTCCLK - 32.768kHz */ 49 #define TCSR_EXT_EN 0x04 /* EXTCLK - 48MHz */ 50 #define TCSR_PRESCALE_M 0x38 51 #define TCSR_DIV_1 0x00 52 #define TCSR_DIV_4 0x08 53 #define TCSR_DIV_16 0x10 54 #define TCSR_DIV_64 0x18 55 #define TCSR_DIV_256 0x20 56 #define TCSR_DIV_1024 0x28 57 58 /* timers and PWMs */ 59 #define JZ_TC_TER 0x10002010 /* TC enable reg, ro */ 60 #define JZ_TC_TESR 0x10002014 /* TC enable set reg. */ 61 #define TESR_TCST0 0x0001 /* enable counter 0 */ 62 #define TESR_TCST1 0x0002 /* enable counter 1 */ 63 #define TESR_TCST2 0x0004 /* enable counter 2 */ 64 #define TESR_TCST3 0x0008 /* enable counter 3 */ 65 #define TESR_TCST4 0x0010 /* enable counter 4 */ 66 #define TESR_TCST5 0x0020 /* enable counter 5 */ 67 #define TESR_TCST6 0x0040 /* enable counter 6 */ 68 #define TESR_TCST7 0x0080 /* enable counter 7 */ 69 #define TESR_OST 0x8000 /* enable OST */ 70 #define JZ_TC_TECR 0x10002018 /* TC enable clear reg. */ 71 #define JZ_TC_TFR 0x10002020 72 #define TFR_FFLAG0 0x00000001 /* channel 0 */ 73 #define TFR_FFLAG1 0x00000002 /* channel 1 */ 74 #define TFR_FFLAG2 0x00000004 /* channel 2 */ 75 #define TFR_FFLAG3 0x00000008 /* channel 3 */ 76 #define TFR_FFLAG4 0x00000010 /* channel 4 */ 77 #define TFR_FFLAG5 0x00000020 /* channel 5 */ 78 #define TFR_FFLAG6 0x00000040 /* channel 6 */ 79 #define TFR_FFLAG7 0x00000080 /* channel 7 */ 80 #define TFR_OSTFLAG 0x00008000 /* OS timer */ 81 #define JZ_TC_TFSR 0x10002024 /* timer flag set */ 82 #define JZ_TC_TFCR 0x10002028 /* timer flag clear */ 83 #define JZ_TC_TMR 0x10002030 /* timer flag mask */ 84 #define JZ_TC_TMSR 0x10002034 /* timer flag mask set */ 85 #define JZ_TC_TMCR 0x10002038 /* timer flag mask clear*/ 86 87 #define JZ_TC_TDFR(n) (0x10002040 + (n * 0x10)) /* FULL compare */ 88 #define JZ_TC_TDHR(n) (0x10002044 + (n * 0x10)) /* HALF compare */ 89 #define JZ_TC_TCNT(n) (0x10002048 + (n * 0x10)) /* count */ 90 91 #define JZ_TC_TCSR(n) (0x1000204c + (n * 0x10)) 92 /* same bits as in JZ_WDOG_TCSR */ 93 94 /* operating system timer */ 95 #define JZ_OST_DATA 0x100020e0 /* compare */ 96 #define JZ_OST_CNT_LO 0x100020e4 97 #define JZ_OST_CNT_HI 0x100020e8 98 #define JZ_OST_CTRL 0x100020ec 99 #define OSTC_PCK_EN 0x0001 /* use PCLK */ 100 #define OSTC_RTC_EN 0x0002 /* use RTCCLK */ 101 #define OSTC_EXT_EN 0x0004 /* use EXTCLK */ 102 #define OSTC_PRESCALE_M 0x0038 103 #define OSTC_DIV_1 0x0000 104 #define OSTC_DIV_4 0x0008 105 #define OSTC_DIV_16 0x0010 106 #define OSTC_DIV_64 0x0018 107 #define OSTC_DIV_256 0x0020 108 #define OSTC_DIV_1024 0x0028 109 #define OSTC_SHUTDOWN 0x0200 110 #define OSTC_MODE 0x8000 /* 0 - reset to 0 when = OST_DATA */ 111 #define JZ_OST_CNT_U32 0x100020fc /* copy of CNT_HI when reading CNT_LO */ 112 113 static inline void 114 writereg(uint32_t reg, uint32_t val) 115 { 116 *(int32_t *)MIPS_PHYS_TO_KSEG1(reg) = val; 117 wbflush(); 118 } 119 120 static inline uint32_t 121 readreg(uint32_t reg) 122 { 123 wbflush(); 124 return *(int32_t *)MIPS_PHYS_TO_KSEG1(reg); 125 } 126 127 /* extra CP0 registers */ 128 static inline uint32_t 129 MFC0(uint32_t r, uint32_t s) 130 { 131 uint32_t ret = 0x12345678; 132 133 __asm volatile("mfc0 %0, $%1, %2; nop;" : "=r"(ret) : "i"(r), "i"(s)); 134 return ret; 135 } 136 137 #define MTC0(v, r, s) __asm volatile("mtc0 %0, $%1, %2; nop;" :: "r"(v), "i"(r), "i"(s)) 138 139 #define CP0_CORE_CTRL 12 /* select 2 */ 140 #define CC_SW_RST0 1 /* reset core 0 */ 141 #define CC_SW_RST1 2 /* reset core 1 */ 142 #define CC_RPC0 0x100 /* dedicater reset entry core 0 */ 143 #define CC_RPC1 0x200 /* -- || -- core 1 */ 144 #define CC_SLEEP0M 0x10000 /* mask sleep core 0 */ 145 #define CC_SLEEP1M 0x20000 /* mask sleep core 1 */ 146 147 /* cores status, 12 select 3 */ 148 #define CS_MIRQ0_P 0x00001 /* mailbox IRQ for 0 pending */ 149 #define CS_MIRQ1_P 0x00002 /* || core 1 */ 150 #define CS_IRQ0_P 0x00100 /* peripheral IRQ for core 0 */ 151 #define CS_IRQ1_P 0x00200 /* || core 1 */ 152 #define CS_SLEEP0 0x10000 /* core 0 sleeping */ 153 #define CS_SLEEP1 0x20000 /* core 1 sleeping */ 154 155 /* cores reset entry & IRQ masks - 12 select 4 */ 156 #define REIM_MIRQ0_M 0x00001 /* allow mailbox IRQ for core 0 */ 157 #define REIM_MIRQ1_M 0x00002 /* allow mailbox IRQ for core 1 */ 158 #define REIM_IRQ0_M 0x00100 /* allow peripheral IRQ for core 0 */ 159 #define REIM_IRQ1_M 0x00200 /* allow peripheral IRQ for core 1 */ 160 #define REIM_ENTRY_M 0xffff0000 /* reset exception entry if RPCn=1 */ 161 162 #define CP0_CORE_MBOX 20 /* select 0 for core 0, 1 for 1 */ 163 164 /* power management */ 165 #define JZ_CLKGR0 0x10000020 /* CLocK Gating Registers */ 166 #define JZ_OPCR 0x10000024 /* Oscillator Power Control Reg. */ 167 #define OPCR_IDLE_DIS 0x80000000 /* don't stop CPU clk on idle */ 168 #define OPCR_GPU_CLK_ST 0x40000000 /* stop GPU clock */ 169 #define OPCR_L2CM_M 0x0c000000 170 #define OPCR_L2CM_ON 0x00000000 /* L2 stays on in sleep */ 171 #define OPCR_L2CM_RET 0x04000000 /* L2 retention mode in sleep */ 172 #define OPCR_L2CM_OFF 0x08000000 /* L2 powers down in sleep */ 173 #define OPCR_SPENDN0 0x00000080 /* OTG port forced down */ 174 #define OPCR_SPENDN1 0x00000040 /* UHC port forced down */ 175 #define OPCR_BUS_MODE 0x00000020 /* 1 - bursts */ 176 #define OPCR_O1SE 0x00000010 /* EXTCLK on in sleep */ 177 #define OPCR_PD 0x00000008 /* P0 down in sleep */ 178 #define OPCR_ERCS 0x00000004 /* 1 RTCCLK, 0 EXTCLK/512 */ 179 #define OPCR_CPU_MODE 0x00000002 /* 1 access 'accelerated' */ 180 #define OPCR_OSE 0x00000001 /* disable EXTCLK */ 181 #define JZ_CLKGR1 0x10000028 /* CLocK Gating Registers */ 182 #define JZ_USBPCR 0x1000003c 183 #define PCR_USB_MODE 0x80000000 /* 1 - otg */ 184 #define PCR_AVLD_REG 0x40000000 185 #define PCR_IDPULLUP_MASK 0x30000000 186 #define PCR_INCR_MASK 0x08000000 187 #define PCR_TCRISETUNE 0x04000000 188 #define PCR_COMMONONN 0x02000000 189 #define PCR_VBUSVLDEXT 0x01000000 190 #define PCR_VBUSVLDEXTSEL 0x00800000 191 #define PCR_POR 0x00400000 192 #define PCR_SIDDQ 0x00200000 193 #define PCR_OTG_DISABLE 0x00100000 194 #define PCR_COMPDISTN_M 0x000e0000 195 #define PCR_OTGTUNE 0x0001c000 196 #define PCR_SQRXTUNE 0x00003800 197 #define PCR_TXFSLSTUNE 0x00000780 198 #define PCR_TXPREEMPHTUNE 0x00000040 199 #define PCR_TXHSXVTUNE 0x00000030 200 #define PCR_TXVREFTUNE 0x0000000f 201 #define JZ_USBRDT 0x10000040 /* Reset Detect Timer Register */ 202 #define JZ_USBPCR1 0x10000048 203 #define PCR_SYNOPSYS 0x10000000 /* Mentor mode otherwise */ 204 #define PCR_REFCLK_CORE 0x0c000000 205 #define PCR_REFCLK_XO25 0x04000000 206 #define PCR_REFCLK_CO 0x00000000 207 #define PCR_CLK_M 0x03000000 /* clock */ 208 #define PCR_CLK_192 0x03000000 /* 19.2MHz */ 209 #define PCR_CLK_48 0x02000000 /* 48MHz */ 210 #define PCR_CLK_24 0x01000000 /* 24MHz */ 211 #define PCR_CLK_12 0x00000000 /* 12MHz */ 212 #define PCR_DMPD1 0x00800000 /* pull down D- on port 1 */ 213 #define PCR_DPPD1 0x00400000 /* pull down D+ on port 1 */ 214 #define PCR_PORT0_RST 0x00200000 /* port 0 reset */ 215 #define PCR_PORT1_RST 0x00100000 /* port 1 reset */ 216 #define PCR_WORD_I_F0 0x00080000 /* 1: 16bit/30M, 8/60 otherw. */ 217 #define PCR_WORD_I_F1 0x00040000 /* same for port 1 */ 218 #define PCR_COMPDISTUNE 0x00038000 /* disconnect threshold */ 219 #define PCR_SQRXTUNE1 0x00007000 /* squelch threshold */ 220 #define PCR_TXFSLSTUNE1 0x00000f00 /* FS/LS impedance adj. */ 221 #define PCR_TXPREEMPH 0x00000080 /* HS transm. pre-emphasis */ 222 #define PCR_TXHSXVTUNE1 0x00000060 /* dp/dm voltage adj. */ 223 #define PCR_TXVREFTUNE1 0x00000017 /* HS DC voltage adj. */ 224 #define PCR_TXRISETUNE1 0x00000001 /* risa/fall wave adj. */ 225 226 #define JZ_UHCCDR 0x1000006c /* UHC Clock Divider Register */ 227 #define JZ_SPCR0 0x100000b8 /* SRAM Power Control Registers */ 228 #define JZ_SPCR1 0x100000bc 229 #define JZ_SRBC 0x100000c4 /* Soft Reset & Bus Control */ 230 231 /* interrupt controller */ 232 #define JZ_ICSR0 0x10001000 /* raw IRQ line status */ 233 #define JZ_ICMR0 0x10001004 /* IRQ mask, 1 masks IRQ */ 234 #define JZ_ICMSR0 0x10001008 /* sets bits in mask register */ 235 #define JZ_ICMCR0 0x1000100c /* clears bits in maks register */ 236 #define JZ_ICPR0 0x10001010 /* line status after masking */ 237 238 #define JZ_ICSR1 0x10001020 /* raw IRQ line status */ 239 #define JZ_ICMR1 0x10001024 /* IRQ mask, 1 masks IRQ */ 240 #define JZ_ICMSR1 0x10001028 /* sets bits in mask register */ 241 #define JZ_ICMCR1 0x1000102c /* clears bits in maks register */ 242 #define JZ_ICPR1 0x10001030 /* line status after masking */ 243 244 #define JZ_DSR0 0x10001034 /* source for PDMA */ 245 #define JZ_DMR0 0x10001038 /* mask for PDMA */ 246 #define JZ_DPR0 0x1000103c /* pending for PDMA */ 247 248 #define JZ_DSR1 0x10001040 /* source for PDMA */ 249 #define JZ_DMR1 0x10001044 /* mask for PDMA */ 250 #define JZ_DPR1 0x10001048 /* pending for PDMA */ 251 252 /* memory controller */ 253 #define JZ_DMMAP0 0x13010024 254 #define JZ_DMMAP1 0x13010028 255 #define DMMAP_BASE 0x0000ff00 /* base PADDR of memory chunk */ 256 #define DMMAP_MASK 0x000000ff /* mask which bits of PADDR are 257 * constant */ 258 259 #endif /* INGENIC_REGS_H */ 260
Indexes created Wed Oct 01 19:09:53 GMT 2025