ralink_eth.c revision 1.19
1 /* $NetBSD: ralink_eth.c,v 1.19 2019/06/03 06:04:20 msaitoh Exp $ */ 2 /*- 3 * Copyright (c) 2011 CradlePoint Technology, Inc. 4 * All rights reserved. 5 * 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY CRADLEPOINT TECHNOLOGY, INC. AND CONTRIBUTORS 17 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 18 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 19 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS 20 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 21 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 22 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 23 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 24 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 25 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 26 * POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 /* ralink_eth.c -- Ralink Ethernet Driver */ 30 31 #include <sys/cdefs.h> 32 __KERNEL_RCSID(0, "$NetBSD: ralink_eth.c,v 1.19 2019/06/03 06:04:20 msaitoh Exp $"); 33 34 #include <sys/param.h> 35 #include <sys/bus.h> 36 #include <sys/callout.h> 37 #include <sys/device.h> 38 #include <sys/endian.h> 39 #include <sys/errno.h> 40 #include <sys/ioctl.h> 41 #include <sys/intr.h> 42 #include <sys/kernel.h> 43 #include <sys/malloc.h> 44 #include <sys/mbuf.h> 45 #include <sys/socket.h> 46 #include <sys/systm.h> 47 48 #include <uvm/uvm_extern.h> 49 50 #include <net/if.h> 51 #include <net/if_dl.h> 52 #include <net/if_media.h> 53 #include <net/if_ether.h> 54 #include <net/if_vlanvar.h> 55 56 #include <net/bpf.h> 57 58 #include <dev/mii/mii.h> 59 #include <dev/mii/miivar.h> 60 #include <dev/mii/mii_bitbang.h> 61 62 #include <mips/ralink/ralink_var.h> 63 #include <mips/ralink/ralink_reg.h> 64 #if 0 65 #define CPDEBUG /* XXX TMP DEBUG FIXME */ 66 #define RALINK_ETH_DEBUG /* XXX TMP DEBUG FIXME */ 67 #define ENABLE_RALINK_DEBUG_ERROR 1 68 #define ENABLE_RALINK_DEBUG_MISC 1 69 #define ENABLE_RALINK_DEBUG_INFO 1 70 #define ENABLE_RALINK_DEBUG_FORCE 1 71 #define ENABLE_RALINK_DEBUG_REG 1 72 #endif 73 #include <mips/ralink/ralink_debug.h> 74 75 76 /* PDMA RX Descriptor Format */ 77 struct ralink_rx_desc { 78 uint32_t data_ptr; 79 uint32_t rxd_info1; 80 #define RXD_LEN1(x) (((x) >> 0) & 0x3fff) 81 #define RXD_LAST1 (1 << 14) 82 #define RXD_LEN0(x) (((x) >> 16) & 0x3fff) 83 #define RXD_LAST0 (1 << 30) 84 #define RXD_DDONE (1 << 31) 85 uint32_t unused; 86 uint32_t rxd_info2; 87 #define RXD_FOE(x) (((x) >> 0) & 0x3fff) 88 #define RXD_FVLD (1 << 14) 89 #define RXD_INFO(x) (((x) >> 16) & 0xff) 90 #define RXD_PORT(x) (((x) >> 24) & 0x7) 91 #define RXD_INFO_CPU (1 << 27) 92 #define RXD_L4_FAIL (1 << 28) 93 #define RXD_IP_FAIL (1 << 29) 94 #define RXD_L4_VLD (1 << 30) 95 #define RXD_IP_VLD (1 << 31) 96 }; 97 98 /* PDMA TX Descriptor Format */ 99 struct ralink_tx_desc { 100 uint32_t data_ptr0; 101 uint32_t txd_info1; 102 #define TXD_LEN1(x) (((x) & 0x3fff) << 0) 103 #define TXD_LAST1 (1 << 14) 104 #define TXD_BURST (1 << 15) 105 #define TXD_LEN0(x) (((x) & 0x3fff) << 16) 106 #define TXD_LAST0 (1 << 30) 107 #define TXD_DDONE (1 << 31) 108 uint32_t data_ptr1; 109 uint32_t txd_info2; 110 #define TXD_VIDX(x) (((x) & 0xf) << 0) 111 #define TXD_VPRI(x) (((x) & 0x7) << 4) 112 #define TXD_VEN (1 << 7) 113 #define TXD_SIDX(x) (((x) & 0xf) << 8) 114 #define TXD_SEN(x) (1 << 13) 115 #define TXD_QN(x) (((x) & 0x7) << 16) 116 #define TXD_PN(x) (((x) & 0x7) << 24) 117 #define TXD_PN_CPU 0 118 #define TXD_PN_GDMA1 1 119 #define TXD_PN_GDMA2 2 120 #define TXD_TCP_EN (1 << 29) 121 #define TXD_UDP_EN (1 << 30) 122 #define TXD_IP_EN (1 << 31) 123 }; 124 125 /* TODO: 126 * try to scale number of descriptors swith size of memory 127 * these numbers may have a significant impact on performance/memory/mbuf usage 128 */ 129 #if RTMEMSIZE >= 64 130 #define RALINK_ETH_NUM_RX_DESC 256 131 #define RALINK_ETH_NUM_TX_DESC 256 132 #else 133 #define RALINK_ETH_NUM_RX_DESC 64 134 #define RALINK_ETH_NUM_TX_DESC 64 135 #endif 136 /* maximum segments per packet */ 137 #define RALINK_ETH_MAX_TX_SEGS 1 138 139 /* define a struct for ease of dma memory allocation */ 140 struct ralink_descs { 141 struct ralink_rx_desc rxdesc[RALINK_ETH_NUM_RX_DESC]; 142 struct ralink_tx_desc txdesc[RALINK_ETH_NUM_TX_DESC]; 143 }; 144 145 /* Software state for transmit jobs. */ 146 struct ralink_eth_txstate { 147 struct mbuf *txs_mbuf; /* head of our mbuf chain */ 148 bus_dmamap_t txs_dmamap; /* our DMA map */ 149 int txs_idx; /* the index in txdesc ring that */ 150 /* this state is tracking */ 151 SIMPLEQ_ENTRY(ralink_eth_txstate) txs_q; 152 }; 153 154 SIMPLEQ_HEAD(ralink_eth_txsq, ralink_eth_txstate); 155 156 /* 157 * Software state for receive jobs. 158 */ 159 struct ralink_eth_rxstate { 160 struct mbuf *rxs_mbuf; /* head of our mbuf chain */ 161 bus_dmamap_t rxs_dmamap; /* our DMA map */ 162 }; 163 164 typedef struct ralink_eth_softc { 165 device_t sc_dev; /* generic device information */ 166 bus_space_tag_t sc_memt; /* bus space tag */ 167 bus_space_handle_t sc_sy_memh; /* handle at SYSCTL_BASE */ 168 bus_space_handle_t sc_fe_memh; /* handle at FRAME_ENGINE_BASE */ 169 bus_space_handle_t sc_sw_memh; /* handle at ETH_SW_BASE */ 170 int sc_sy_size; /* size of Sysctl regs space */ 171 int sc_fe_size; /* size of Frame Engine regs space */ 172 int sc_sw_size; /* size of Ether Switch regs space */ 173 bus_dma_tag_t sc_dmat; /* bus DMA tag */ 174 void *sc_ih; /* interrupt handle */ 175 176 /* tx/rx dma mapping */ 177 bus_dma_segment_t sc_dseg; 178 int sc_ndseg; 179 bus_dmamap_t sc_pdmamap; /* PDMA DMA map */ 180 #define sc_pdma sc_pdmamap->dm_segs[0].ds_addr 181 182 struct ralink_descs *sc_descs; 183 #define sc_rxdesc sc_descs->rxdesc 184 #define sc_txdesc sc_descs->txdesc 185 186 #define RALINK_MIN_BUF 64 187 char ralink_zero_buf[RALINK_MIN_BUF]; 188 189 struct ralink_eth_txstate sc_txstate[RALINK_ETH_NUM_TX_DESC]; 190 struct ralink_eth_rxstate sc_rxstate[RALINK_ETH_NUM_RX_DESC]; 191 192 struct ralink_eth_txsq sc_txfreeq; /* free Tx descsofts */ 193 struct ralink_eth_txsq sc_txdirtyq; /* dirty Tx descsofts */ 194 195 struct ethercom sc_ethercom; /* ethernet common data */ 196 u_int sc_pending_tx; 197 198 /* mii */ 199 struct mii_data sc_mii; 200 struct callout sc_tick_callout; 201 202 struct evcnt sc_evcnt_spurious_intr; 203 struct evcnt sc_evcnt_rxintr; 204 struct evcnt sc_evcnt_rxintr_skip_len; 205 struct evcnt sc_evcnt_rxintr_skip_tag_none; 206 struct evcnt sc_evcnt_rxintr_skip_tag_inval; 207 struct evcnt sc_evcnt_rxintr_skip_inact; 208 struct evcnt sc_evcnt_txintr; 209 struct evcnt sc_evcnt_input; 210 struct evcnt sc_evcnt_output; 211 struct evcnt sc_evcnt_watchdog; 212 struct evcnt sc_evcnt_wd_reactivate; 213 struct evcnt sc_evcnt_wd_tx; 214 struct evcnt sc_evcnt_wd_spurious; 215 struct evcnt sc_evcnt_add_rxbuf_hdr_fail; 216 struct evcnt sc_evcnt_add_rxbuf_mcl_fail; 217 } ralink_eth_softc_t; 218 219 /* alignment so the IP header is aligned */ 220 #define RALINK_ETHER_ALIGN 2 221 222 /* device functions */ 223 static int ralink_eth_match(device_t, cfdata_t, void *); 224 static void ralink_eth_attach(device_t, device_t, void *); 225 static int ralink_eth_detach(device_t, int); 226 static int ralink_eth_activate(device_t, enum devact); 227 228 /* local driver functions */ 229 static void ralink_eth_hw_init(ralink_eth_softc_t *); 230 static int ralink_eth_intr(void *); 231 static void ralink_eth_reset(ralink_eth_softc_t *); 232 static void ralink_eth_rxintr(ralink_eth_softc_t *); 233 static void ralink_eth_txintr(ralink_eth_softc_t *); 234 235 /* partition functions */ 236 static int ralink_eth_enable(ralink_eth_softc_t *); 237 static void ralink_eth_disable(ralink_eth_softc_t *); 238 239 /* ifnet functions */ 240 static int ralink_eth_init(struct ifnet *); 241 static void ralink_eth_rxdrain(ralink_eth_softc_t *); 242 static void ralink_eth_stop(struct ifnet *, int); 243 static int ralink_eth_add_rxbuf(ralink_eth_softc_t *, int); 244 static void ralink_eth_start(struct ifnet *); 245 static void ralink_eth_watchdog(struct ifnet *); 246 static int ralink_eth_ioctl(struct ifnet *, u_long, void *); 247 248 /* mii functions */ 249 #if defined(RT3050) || defined(RT3052) 250 static void ralink_eth_mdio_enable(ralink_eth_softc_t *, bool); 251 #endif 252 static void ralink_eth_mii_statchg(struct ifnet *); 253 static void ralink_eth_mii_tick(void *); 254 static int ralink_eth_mii_read(device_t, int, int, uint16_t *); 255 static int ralink_eth_mii_write(device_t, int, int, uint16_t); 256 257 CFATTACH_DECL_NEW(reth, sizeof(struct ralink_eth_softc), 258 ralink_eth_match, ralink_eth_attach, ralink_eth_detach, 259 ralink_eth_activate); 260 261 static inline uint32_t 262 sy_read(const ralink_eth_softc_t *sc, const bus_size_t off) 263 { 264 return bus_space_read_4(sc->sc_memt, sc->sc_sy_memh, off); 265 } 266 267 static inline void 268 sy_write(const ralink_eth_softc_t *sc, const bus_size_t off, const uint32_t val) 269 { 270 bus_space_write_4(sc->sc_memt, sc->sc_sy_memh, off, val); 271 } 272 273 static inline uint32_t 274 fe_read(const ralink_eth_softc_t *sc, const bus_size_t off) 275 { 276 return bus_space_read_4(sc->sc_memt, sc->sc_fe_memh, off); 277 } 278 279 static inline void 280 fe_write(const ralink_eth_softc_t *sc, const bus_size_t off, const uint32_t val) 281 { 282 bus_space_write_4(sc->sc_memt, sc->sc_fe_memh, off, val); 283 } 284 285 static inline uint32_t 286 sw_read(const ralink_eth_softc_t *sc, const bus_size_t off) 287 { 288 return bus_space_read_4(sc->sc_memt, sc->sc_sw_memh, off); 289 } 290 291 static inline void 292 sw_write(const ralink_eth_softc_t *sc, const bus_size_t off, const uint32_t val) 293 { 294 bus_space_write_4(sc->sc_memt, sc->sc_sw_memh, off, val); 295 } 296 297 /* 298 * ralink_eth_match 299 */ 300 int 301 ralink_eth_match(device_t parent, cfdata_t cf, void *aux) 302 { 303 return 1; 304 } 305 306 /* 307 * ralink_eth_attach 308 */ 309 void 310 ralink_eth_attach(device_t parent, device_t self, void *aux) 311 { 312 ralink_eth_softc_t * const sc = device_private(self); 313 const struct mainbus_attach_args *ma = aux; 314 struct mii_data *mii = &sc->sc_mii; 315 int error; 316 int i; 317 318 aprint_naive(": Ralink Ethernet\n"); 319 aprint_normal(": Ralink Ethernet\n"); 320 321 evcnt_attach_dynamic(&sc->sc_evcnt_spurious_intr, EVCNT_TYPE_INTR, NULL, 322 device_xname(self), "spurious intr"); 323 evcnt_attach_dynamic(&sc->sc_evcnt_rxintr, EVCNT_TYPE_INTR, NULL, 324 device_xname(self), "rxintr"); 325 evcnt_attach_dynamic(&sc->sc_evcnt_rxintr_skip_len, 326 EVCNT_TYPE_INTR, &sc->sc_evcnt_rxintr, 327 device_xname(self), "rxintr skip: no room for VLAN header"); 328 evcnt_attach_dynamic(&sc->sc_evcnt_rxintr_skip_tag_none, 329 EVCNT_TYPE_INTR, &sc->sc_evcnt_rxintr, 330 device_xname(self), "rxintr skip: no VLAN tag"); 331 evcnt_attach_dynamic(&sc->sc_evcnt_rxintr_skip_tag_inval, 332 EVCNT_TYPE_INTR, &sc->sc_evcnt_rxintr, 333 device_xname(self), "rxintr skip: invalid VLAN tag"); 334 evcnt_attach_dynamic(&sc->sc_evcnt_rxintr_skip_inact, 335 EVCNT_TYPE_INTR, &sc->sc_evcnt_rxintr, 336 device_xname(self), "rxintr skip: partition inactive"); 337 evcnt_attach_dynamic(&sc->sc_evcnt_txintr, EVCNT_TYPE_INTR, NULL, 338 device_xname(self), "txintr"); 339 evcnt_attach_dynamic(&sc->sc_evcnt_input, EVCNT_TYPE_INTR, NULL, 340 device_xname(self), "input"); 341 evcnt_attach_dynamic(&sc->sc_evcnt_output, EVCNT_TYPE_INTR, NULL, 342 device_xname(self), "output"); 343 evcnt_attach_dynamic(&sc->sc_evcnt_watchdog, EVCNT_TYPE_INTR, NULL, 344 device_xname(self), "watchdog"); 345 evcnt_attach_dynamic(&sc->sc_evcnt_wd_tx, 346 EVCNT_TYPE_INTR, &sc->sc_evcnt_watchdog, 347 device_xname(self), "watchdog TX timeout"); 348 evcnt_attach_dynamic(&sc->sc_evcnt_wd_spurious, 349 EVCNT_TYPE_INTR, &sc->sc_evcnt_watchdog, 350 device_xname(self), "watchdog spurious"); 351 evcnt_attach_dynamic(&sc->sc_evcnt_wd_reactivate, 352 EVCNT_TYPE_INTR, &sc->sc_evcnt_watchdog, 353 device_xname(self), "watchdog reactivate"); 354 evcnt_attach_dynamic(&sc->sc_evcnt_add_rxbuf_hdr_fail, 355 EVCNT_TYPE_INTR, NULL, 356 device_xname(self), "add rxbuf hdr fail"); 357 evcnt_attach_dynamic(&sc->sc_evcnt_add_rxbuf_mcl_fail, 358 EVCNT_TYPE_INTR, NULL, 359 device_xname(self), "add rxbuf mcl fail"); 360 361 /* 362 * In order to obtain unique initial Ethernet address on a host, 363 * do some randomisation using the current uptime. It's not meant 364 * for anything but avoiding hard-coding an address. 365 */ 366 #ifdef RALINK_ETH_MACADDR 367 uint8_t enaddr[ETHER_ADDR_LEN]; 368 ether_aton_r(enaddr, sizeof(enaddr), ___STRING(RALINK_ETH_MACADDR)); 369 #else 370 uint8_t enaddr[ETHER_ADDR_LEN] = { 0x00, 0x30, 0x44, 0x00, 0x00, 0x00 }; 371 #endif 372 373 sc->sc_dev = self; 374 sc->sc_dmat = ma->ma_dmat; 375 sc->sc_memt = ma->ma_memt; 376 sc->sc_sy_size = 0x10000; 377 sc->sc_fe_size = 0x10000; 378 sc->sc_sw_size = 0x08000; 379 380 /* 381 * map the registers 382 * 383 * we map the Sysctl, Frame Engine and Ether Switch registers 384 * separately so we can use the defined register offsets sanely 385 */ 386 if ((error = bus_space_map(sc->sc_memt, RA_SYSCTL_BASE, 387 sc->sc_sy_size, 0, &sc->sc_sy_memh)) != 0) { 388 aprint_error_dev(self, "unable to map Sysctl registers, " 389 "error=%d\n", error); 390 goto fail_0a; 391 } 392 if ((error = bus_space_map(sc->sc_memt, RA_FRAME_ENGINE_BASE, 393 sc->sc_fe_size, 0, &sc->sc_fe_memh)) != 0) { 394 aprint_error_dev(self, "unable to map Frame Engine registers, " 395 "error=%d\n", error); 396 goto fail_0b; 397 } 398 if ((error = bus_space_map(sc->sc_memt, RA_ETH_SW_BASE, 399 sc->sc_sw_size, 0, &sc->sc_sw_memh)) != 0) { 400 aprint_error_dev(self, "unable to map Ether Switch registers, " 401 "error=%d\n", error); 402 goto fail_0c; 403 } 404 405 /* Allocate desc structures, and create & load the DMA map for them */ 406 if ((error = bus_dmamem_alloc(sc->sc_dmat, sizeof(struct ralink_descs), 407 PAGE_SIZE, 0, &sc->sc_dseg, 1, &sc->sc_ndseg, 0)) != 0) { 408 aprint_error_dev(self, "unable to allocate transmit descs, " 409 "error=%d\n", error); 410 goto fail_1; 411 } 412 413 if ((error = bus_dmamem_map(sc->sc_dmat, &sc->sc_dseg, sc->sc_ndseg, 414 sizeof(struct ralink_descs), (void **)&sc->sc_descs, 415 BUS_DMA_COHERENT)) != 0) { 416 aprint_error_dev(self, "unable to map control data, " 417 "error=%d\n", error); 418 goto fail_2; 419 } 420 421 if ((error = bus_dmamap_create(sc->sc_dmat, sizeof(struct ralink_descs), 422 1, sizeof(struct ralink_descs), 0, 0, &sc->sc_pdmamap)) != 0) { 423 aprint_error_dev(self, "unable to create control data DMA map, " 424 "error=%d\n", error); 425 goto fail_3; 426 } 427 428 if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_pdmamap, sc->sc_descs, 429 sizeof(struct ralink_descs), NULL, 0)) != 0) { 430 aprint_error_dev(self, "unable to load control data DMA map, " 431 "error=%d\n", error); 432 goto fail_4; 433 } 434 435 /* Create the transmit buffer DMA maps. */ 436 for (i = 0; i < RALINK_ETH_NUM_TX_DESC; i++) { 437 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 438 RALINK_ETH_MAX_TX_SEGS, MCLBYTES, 0, 0, 439 &sc->sc_txstate[i].txs_dmamap)) != 0) { 440 aprint_error_dev(self, 441 "unable to create tx DMA map %d, error=%d\n", 442 i, error); 443 goto fail_5; 444 } 445 } 446 447 /* Create the receive buffer DMA maps. */ 448 for (i = 0; i < RALINK_ETH_NUM_RX_DESC; i++) { 449 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, 450 MCLBYTES, 0, 0, &sc->sc_rxstate[i].rxs_dmamap)) != 0) { 451 aprint_error_dev(self, 452 "unable to create rx DMA map %d, error=%d\n", 453 i, error); 454 goto fail_6; 455 } 456 sc->sc_rxstate[i].rxs_mbuf = NULL; 457 } 458 459 /* this is a zero buffer used for zero'ing out short packets */ 460 memset(sc->ralink_zero_buf, 0, RALINK_MIN_BUF); 461 462 /* setup some address in hardware */ 463 fe_write(sc, RA_FE_GDMA1_MAC_LSB, 464 (enaddr[5] | (enaddr[4] << 8) | 465 (enaddr[3] << 16) | (enaddr[2] << 24))); 466 fe_write(sc, RA_FE_GDMA1_MAC_MSB, 467 (enaddr[1] | (enaddr[0] << 8))); 468 469 /* 470 * iterate through ports 471 * slickrock must use specific non-linear sequence 472 * others are linear 473 */ 474 struct ifnet * const ifp = &sc->sc_ethercom.ec_if; 475 476 strlcpy(ifp->if_xname, device_xname(self), IFNAMSIZ); 477 478 /* 479 * Initialize our media structures. 480 * This may probe the PHY, if present. 481 */ 482 mii->mii_ifp = ifp; 483 mii->mii_readreg = ralink_eth_mii_read; 484 mii->mii_writereg = ralink_eth_mii_write; 485 mii->mii_statchg = ralink_eth_mii_statchg; 486 sc->sc_ethercom.ec_mii = mii; 487 ifmedia_init(&mii->mii_media, 0, ether_mediachange, ether_mediastatus); 488 mii_attach(sc->sc_dev, mii, ~0, MII_PHY_ANY, MII_OFFSET_ANY, 489 MIIF_FORCEANEG | MIIF_DOPAUSE | MIIF_NOISOLATE); 490 491 if (LIST_EMPTY(&mii->mii_phys)) { 492 #if 1 493 ifmedia_add(&mii->mii_media, IFM_ETHER | IFM_1000_T | 494 IFM_FDX | IFM_ETH_RXPAUSE | IFM_ETH_TXPAUSE, 0, NULL); 495 ifmedia_set(&mii->mii_media, IFM_ETHER | IFM_1000_T | 496 IFM_FDX | IFM_ETH_RXPAUSE | IFM_ETH_TXPAUSE); 497 #else 498 ifmedia_add(&mii->mii_media, IFM_ETHER | IFM_MANUAL, 0, NULL); 499 ifmedia_set(&mii->mii_media, IFM_ETHER | IFM_MANUAL); 500 #endif 501 } else { 502 /* Ensure we mask ok for the switch multiple phy's */ 503 ifmedia_set(&mii->mii_media, IFM_ETHER | IFM_AUTO); 504 } 505 506 ifp->if_softc = sc; 507 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 508 ifp->if_init = ralink_eth_init; 509 ifp->if_start = ralink_eth_start; 510 ifp->if_ioctl = ralink_eth_ioctl; 511 ifp->if_stop = ralink_eth_stop; 512 ifp->if_watchdog = ralink_eth_watchdog; 513 IFQ_SET_READY(&ifp->if_snd); 514 515 /* We can support 802.1Q VLAN-sized frames. */ 516 sc->sc_ethercom.ec_capabilities |= ETHERCAP_VLAN_MTU; 517 518 /* We support IPV4 CRC Offload */ 519 ifp->if_capabilities |= 520 (IFCAP_CSUM_IPv4_Tx | IFCAP_CSUM_IPv4_Rx | 521 IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_TCPv4_Rx | 522 IFCAP_CSUM_UDPv4_Tx | IFCAP_CSUM_UDPv4_Rx); 523 524 /* Attach the interface. */ 525 if_attach(ifp); 526 if_deferred_start_init(ifp, NULL); 527 ether_ifattach(ifp, enaddr); 528 529 /* init our mii ticker */ 530 callout_init(&sc->sc_tick_callout, 0); 531 callout_reset(&sc->sc_tick_callout, hz, ralink_eth_mii_tick, sc); 532 533 return; 534 535 /* 536 * Free any resources we've allocated during the failed attach 537 * attempt. Do this in reverse order and fall through. 538 */ 539 fail_6: 540 for (i = 0; i < RALINK_ETH_NUM_RX_DESC; i++) { 541 if (sc->sc_rxstate[i].rxs_dmamap != NULL) 542 bus_dmamap_destroy(sc->sc_dmat, 543 sc->sc_rxstate[i].rxs_dmamap); 544 } 545 fail_5: 546 for (i = 0; i < RALINK_ETH_NUM_TX_DESC; i++) { 547 if (sc->sc_txstate[i].txs_dmamap != NULL) 548 bus_dmamap_destroy(sc->sc_dmat, 549 sc->sc_txstate[i].txs_dmamap); 550 } 551 bus_dmamap_unload(sc->sc_dmat, sc->sc_pdmamap); 552 fail_4: 553 bus_dmamap_destroy(sc->sc_dmat, sc->sc_pdmamap); 554 fail_3: 555 bus_dmamem_unmap(sc->sc_dmat, (void *)sc->sc_descs, 556 sizeof(struct ralink_descs)); 557 fail_2: 558 bus_dmamem_free(sc->sc_dmat, &sc->sc_dseg, sc->sc_ndseg); 559 fail_1: 560 bus_space_unmap(sc->sc_memt, sc->sc_sw_memh, sc->sc_sw_size); 561 fail_0c: 562 bus_space_unmap(sc->sc_memt, sc->sc_fe_memh, sc->sc_fe_size); 563 fail_0b: 564 bus_space_unmap(sc->sc_memt, sc->sc_sy_memh, sc->sc_fe_size); 565 fail_0a: 566 return; 567 } 568 569 /* 570 * ralink_eth_activate: 571 * 572 * Handle device activation/deactivation requests. 573 */ 574 int 575 ralink_eth_activate(device_t self, enum devact act) 576 { 577 ralink_eth_softc_t * const sc = device_private(self); 578 int error = 0; 579 int s; 580 581 s = splnet(); 582 switch (act) { 583 case DVACT_DEACTIVATE: 584 if_deactivate(&sc->sc_ethercom.ec_if); 585 break; 586 } 587 splx(s); 588 589 return error; 590 } 591 592 /* 593 * ralink_eth_partition_enable 594 */ 595 static int 596 ralink_eth_enable(ralink_eth_softc_t *sc) 597 { 598 RALINK_DEBUG_FUNC_ENTRY(); 599 600 if (sc->sc_ih != NULL) { 601 RALINK_DEBUG(RALINK_DEBUG_MISC, "%s() already active", 602 __func__); 603 return EALREADY; 604 } 605 606 sc->sc_pending_tx = 0; 607 608 int s = splnet(); 609 ralink_eth_hw_init(sc); 610 sc->sc_ih = ra_intr_establish(RA_IRQ_FENGINE, 611 ralink_eth_intr, sc, 1); 612 splx(s); 613 if (sc->sc_ih == NULL) { 614 RALINK_DEBUG(RALINK_DEBUG_ERROR, 615 "%s: unable to establish interrupt\n", 616 device_xname(sc->sc_dev)); 617 return EIO; 618 } 619 620 return 0; 621 } 622 623 /* 624 * ralink_eth_partition_disable 625 */ 626 static void 627 ralink_eth_disable(ralink_eth_softc_t *sc) 628 { 629 RALINK_DEBUG_FUNC_ENTRY(); 630 631 int s = splnet(); 632 ralink_eth_rxdrain(sc); 633 ra_intr_disestablish(sc->sc_ih); 634 sc->sc_ih = NULL; 635 636 /* stop the mii ticker */ 637 callout_stop(&sc->sc_tick_callout); 638 639 /* quiesce the block */ 640 ralink_eth_reset(sc); 641 splx(s); 642 } 643 644 /* 645 * ralink_eth_detach 646 */ 647 static int 648 ralink_eth_detach(device_t self, int flags) 649 { 650 RALINK_DEBUG_FUNC_ENTRY(); 651 ralink_eth_softc_t * const sc = device_private(self); 652 struct ifnet * const ifp = &sc->sc_ethercom.ec_if; 653 struct ralink_eth_rxstate *rxs; 654 struct ralink_eth_txstate *txs; 655 int i; 656 657 ralink_eth_disable(sc); 658 mii_detach(&sc->sc_mii, MII_PHY_ANY, MII_OFFSET_ANY); 659 ifmedia_delete_instance(&sc->sc_mii.mii_media, IFM_INST_ANY); 660 ether_ifdetach(ifp); 661 if_detach(ifp); 662 663 for (i = 0; i < RALINK_ETH_NUM_RX_DESC; i++) { 664 rxs = &sc->sc_rxstate[i]; 665 if (rxs->rxs_mbuf != NULL) { 666 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 667 m_freem(rxs->rxs_mbuf); 668 rxs->rxs_mbuf = NULL; 669 } 670 bus_dmamap_destroy(sc->sc_dmat, rxs->rxs_dmamap); 671 } 672 673 for (i = 0; i < RALINK_ETH_NUM_TX_DESC; i++) { 674 txs = &sc->sc_txstate[i]; 675 if (txs->txs_mbuf != NULL) { 676 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 677 m_freem(txs->txs_mbuf); 678 txs->txs_mbuf = NULL; 679 } 680 bus_dmamap_destroy(sc->sc_dmat, txs->txs_dmamap); 681 } 682 683 bus_dmamap_unload(sc->sc_dmat, sc->sc_pdmamap); 684 bus_dmamap_destroy(sc->sc_dmat, sc->sc_pdmamap); 685 bus_dmamem_unmap(sc->sc_dmat, (void *)sc->sc_descs, 686 sizeof(struct ralink_descs)); 687 bus_dmamem_free(sc->sc_dmat, &sc->sc_dseg, sc->sc_ndseg); 688 689 bus_space_unmap(sc->sc_memt, sc->sc_sw_memh, sc->sc_sw_size); 690 bus_space_unmap(sc->sc_memt, sc->sc_fe_memh, sc->sc_fe_size); 691 692 return 0; 693 } 694 695 /* 696 * ralink_eth_reset 697 */ 698 static void 699 ralink_eth_reset(ralink_eth_softc_t *sc) 700 { 701 RALINK_DEBUG_FUNC_ENTRY(); 702 uint32_t r; 703 704 /* Reset the frame engine */ 705 r = sy_read(sc, RA_SYSCTL_RST); 706 r |= RST_FE; 707 sy_write(sc, RA_SYSCTL_RST, r); 708 r ^= RST_FE; 709 sy_write(sc, RA_SYSCTL_RST, r); 710 711 /* Wait until the PDMA is quiescent */ 712 for (;;) { 713 r = fe_read(sc, RA_FE_PDMA_GLOBAL_CFG); 714 if (r & FE_PDMA_GLOBAL_CFG_RX_DMA_BUSY) { 715 aprint_normal_dev(sc->sc_dev, "RX DMA BUSY\n"); 716 continue; 717 } 718 if (r & FE_PDMA_GLOBAL_CFG_TX_DMA_BUSY) { 719 aprint_normal_dev(sc->sc_dev, "TX DMA BUSY\n"); 720 continue; 721 } 722 break; 723 } 724 } 725 726 /* 727 * ralink_eth_hw_init 728 */ 729 static void 730 ralink_eth_hw_init(ralink_eth_softc_t *sc) 731 { 732 RALINK_DEBUG_FUNC_ENTRY(); 733 struct ralink_eth_txstate *txs; 734 uint32_t r; 735 int i; 736 737 /* reset to a known good state */ 738 ralink_eth_reset(sc); 739 740 #if defined(RT3050) || defined(RT3052) || defined(MT7628) 741 /* Bring the switch to a sane default state (from linux driver) */ 742 bus_space_write_4(sc->sc_memt, sc->sc_sw_memh, RA_ETH_SW_SGC2, 743 0x00000000); 744 bus_space_write_4(sc->sc_memt, sc->sc_sw_memh, RA_ETH_SW_PFC1, 745 0x00405555); /* check VLAN tag on port forward */ 746 bus_space_write_4(sc->sc_memt, sc->sc_sw_memh, RA_ETH_SW_VLANI0, 747 0x00002001); 748 bus_space_write_4(sc->sc_memt, sc->sc_sw_memh, RA_ETH_SW_PVIDC0, 749 0x00001002); 750 bus_space_write_4(sc->sc_memt, sc->sc_sw_memh, RA_ETH_SW_PVIDC1, 751 0x00001001); 752 bus_space_write_4(sc->sc_memt, sc->sc_sw_memh, RA_ETH_SW_PVIDC2, 753 0x00001001); 754 #if defined(MT7628) 755 bus_space_write_4(sc->sc_memt, sc->sc_sw_memh, RA_ETH_SW_VMSC0, 756 0xffffffff); 757 bus_space_write_4(sc->sc_memt, sc->sc_sw_memh, RA_ETH_SW_POC0, 758 0x10007f7f); 759 bus_space_write_4(sc->sc_memt, sc->sc_sw_memh, RA_ETH_SW_POC2, 760 0x00007f7f); 761 bus_space_write_4(sc->sc_memt, sc->sc_sw_memh, RA_ETH_SW_FTC2, 762 0x0002500c); 763 #else 764 bus_space_write_4(sc->sc_memt, sc->sc_sw_memh, RA_ETH_SW_VMSC0, 765 0xffff417e); 766 bus_space_write_4(sc->sc_memt, sc->sc_sw_memh, RA_ETH_SW_POC0, 767 0x00007f7f); 768 bus_space_write_4(sc->sc_memt, sc->sc_sw_memh, RA_ETH_SW_POC2, 769 0x00007f3f); 770 bus_space_write_4(sc->sc_memt, sc->sc_sw_memh, RA_ETH_SW_FTC2, 771 0x00d6500c); 772 #endif 773 bus_space_write_4(sc->sc_memt, sc->sc_sw_memh, RA_ETH_SW_SWGC, 774 0x0008a301); /* hashing algorithm=XOR48 */ 775 /* aging interval=300sec */ 776 bus_space_write_4(sc->sc_memt, sc->sc_sw_memh, RA_ETH_SW_SOCPC, 777 0x02404040); 778 bus_space_write_4(sc->sc_memt, sc->sc_sw_memh, RA_ETH_SW_FPORT, 779 0x3f502b28); /* Change polling Ext PHY Addr=0x0 */ 780 bus_space_write_4(sc->sc_memt, sc->sc_sw_memh, RA_ETH_SW_FPA, 781 0x00000000); 782 783 /* do some mii magic TODO: define these registers/bits */ 784 /* lower down PHY 10Mbps mode power */ 785 /* select local register */ 786 ralink_eth_mii_write(sc->sc_dev, 0, 31, 0x8000); 787 788 for (i=0; i < 5; i++) { 789 /* set TX10 waveform coefficient */ 790 ralink_eth_mii_write(sc->sc_dev, i, 26, 0x1601); 791 792 /* set TX100/TX10 AD/DA current bias */ 793 ralink_eth_mii_write(sc->sc_dev, i, 29, 0x7058); 794 795 /* set TX100 slew rate control */ 796 ralink_eth_mii_write(sc->sc_dev, i, 30, 0x0018); 797 } 798 799 /* PHY IOT */ 800 801 /* select global register */ 802 ralink_eth_mii_write(sc->sc_dev, 0, 31, 0x0); 803 804 /* tune TP_IDL tail and head waveform */ 805 ralink_eth_mii_write(sc->sc_dev, 0, 22, 0x052f); 806 807 /* set TX10 signal amplitude threshold to minimum */ 808 ralink_eth_mii_write(sc->sc_dev, 0, 17, 0x0fe0); 809 810 /* set squelch amplitude to higher threshold */ 811 ralink_eth_mii_write(sc->sc_dev, 0, 18, 0x40ba); 812 813 /* longer TP_IDL tail length */ 814 ralink_eth_mii_write(sc->sc_dev, 0, 14, 0x65); 815 816 /* select local register */ 817 ralink_eth_mii_write(sc->sc_dev, 0, 31, 0x8000); 818 #else 819 /* GE1 + GigSW */ 820 fe_write(sc, RA_FE_MDIO_CFG1, 821 MDIO_CFG_PHY_ADDR(0x1f) | 822 MDIO_CFG_BP_EN | 823 MDIO_CFG_FORCE_CFG | 824 MDIO_CFG_SPEED(MDIO_CFG_SPEED_1000M) | 825 MDIO_CFG_FULL_DUPLEX | 826 MDIO_CFG_FC_TX | 827 MDIO_CFG_FC_RX | 828 MDIO_CFG_TX_CLK_MODE(MDIO_CFG_TX_CLK_MODE_3COM)); 829 #endif 830 831 /* 832 * TODO: QOS - RT3052 has 4 TX queues for QOS, 833 * forgoing for 1 for simplicity 834 */ 835 836 /* 837 * Allocate DMA accessible memory for TX/RX descriptor rings 838 */ 839 840 /* Initialize the TX queues. */ 841 SIMPLEQ_INIT(&sc->sc_txfreeq); 842 SIMPLEQ_INIT(&sc->sc_txdirtyq); 843 844 /* Initialize the TX descriptor ring. */ 845 memset(sc->sc_txdesc, 0, sizeof(sc->sc_txdesc)); 846 for (i = 0; i < RALINK_ETH_NUM_TX_DESC; i++) { 847 848 sc->sc_txdesc[i].txd_info1 = TXD_LAST0 | TXD_DDONE; 849 850 /* setup the freeq as well */ 851 txs = &sc->sc_txstate[i]; 852 txs->txs_mbuf = NULL; 853 txs->txs_idx = i; 854 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 855 } 856 857 /* 858 * Flush the TX descriptors 859 * - TODO: can we just access descriptors via KSEG1 860 * to avoid the flush? 861 */ 862 bus_dmamap_sync(sc->sc_dmat, sc->sc_pdmamap, 863 (int)&sc->sc_txdesc - (int)sc->sc_descs, sizeof(sc->sc_txdesc), 864 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 865 866 /* Initialize the RX descriptor ring */ 867 memset(sc->sc_rxdesc, 0, sizeof(sc->sc_rxdesc)); 868 for (i = 0; i < RALINK_ETH_NUM_RX_DESC; i++) { 869 if (ralink_eth_add_rxbuf(sc, i)) { 870 panic("Can't allocate rx mbuf\n"); 871 } 872 } 873 874 /* 875 * Flush the RX descriptors 876 * - TODO: can we just access descriptors via KSEG1 877 * to avoid the flush? 878 */ 879 bus_dmamap_sync(sc->sc_dmat, sc->sc_pdmamap, 880 (int)&sc->sc_rxdesc - (int)sc->sc_descs, sizeof(sc->sc_rxdesc), 881 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 882 883 /* Clear the PDMA state */ 884 r = fe_read(sc, RA_FE_PDMA_GLOBAL_CFG); 885 r &= 0xff; 886 fe_write(sc, RA_FE_PDMA_GLOBAL_CFG, r); 887 (void) fe_read(sc, RA_FE_PDMA_GLOBAL_CFG); 888 889 #if !defined(MT7628) 890 /* Setup the PDMA VLAN ID's */ 891 fe_write(sc, RA_FE_VLAN_ID_0001, 0x00010000); 892 fe_write(sc, RA_FE_VLAN_ID_0203, 0x00030002); 893 fe_write(sc, RA_FE_VLAN_ID_0405, 0x00050004); 894 fe_write(sc, RA_FE_VLAN_ID_0607, 0x00070006); 895 fe_write(sc, RA_FE_VLAN_ID_0809, 0x00090008); 896 fe_write(sc, RA_FE_VLAN_ID_1011, 0x000b000a); 897 fe_write(sc, RA_FE_VLAN_ID_1213, 0x000d000c); 898 fe_write(sc, RA_FE_VLAN_ID_1415, 0x000f000e); 899 #endif 900 901 /* Give the TX and TX rings to the chip. */ 902 fe_write(sc, RA_FE_PDMA_TX0_PTR, 903 htole32(MIPS_KSEG0_TO_PHYS(&sc->sc_txdesc))); 904 fe_write(sc, RA_FE_PDMA_TX0_COUNT, htole32(RALINK_ETH_NUM_TX_DESC)); 905 fe_write(sc, RA_FE_PDMA_TX0_CPU_IDX, 0); 906 #if !defined(MT7628) 907 fe_write(sc, RA_FE_PDMA_RESET_IDX, PDMA_RST_TX0); 908 #endif 909 910 fe_write(sc, RA_FE_PDMA_RX0_PTR, 911 htole32(MIPS_KSEG0_TO_PHYS(&sc->sc_rxdesc))); 912 fe_write(sc, RA_FE_PDMA_RX0_COUNT, htole32(RALINK_ETH_NUM_RX_DESC)); 913 fe_write(sc, RA_FE_PDMA_RX0_CPU_IDX, 914 htole32(RALINK_ETH_NUM_RX_DESC - 1)); 915 #if !defined(MT7628) 916 fe_write(sc, RA_FE_PDMA_RESET_IDX, PDMA_RST_RX0); 917 #endif 918 fe_write(sc, RA_FE_PDMA_RX0_CPU_IDX, 919 htole32(RALINK_ETH_NUM_RX_DESC - 1)); 920 921 /* Start PDMA */ 922 fe_write(sc, RA_FE_PDMA_GLOBAL_CFG, 923 FE_PDMA_GLOBAL_CFG_TX_WB_DDONE | 924 FE_PDMA_GLOBAL_CFG_RX_DMA_EN | 925 FE_PDMA_GLOBAL_CFG_TX_DMA_EN | 926 FE_PDMA_GLOBAL_CFG_BURST_SZ_4); 927 928 /* Setup the clock for the Frame Engine */ 929 #if defined(MT7628) 930 fe_write(sc, RA_FE_SDM_CON, 0x8100); 931 #else 932 fe_write(sc, RA_FE_GLOBAL_CFG, 933 FE_GLOBAL_CFG_EXT_VLAN(0x8100) | 934 FE_GLOBAL_CFG_US_CLK(RA_BUS_FREQ / 1000000) | 935 FE_GLOBAL_CFG_L2_SPACE(0x8)); 936 #endif 937 938 /* Turn on all interrupts */ 939 #if defined(MT7628) 940 fe_write(sc, RA_FE_INT_MASK, 941 RA_FE_INT_RX_DONE_INT1 | 942 RA_FE_INT_RX_DONE_INT0 | 943 RA_FE_INT_TX_DONE_INT3 | 944 RA_FE_INT_TX_DONE_INT2 | 945 RA_FE_INT_TX_DONE_INT1 | 946 RA_FE_INT_TX_DONE_INT0); 947 #else 948 fe_write(sc, RA_FE_INT_ENABLE, 949 FE_INT_RX | FE_INT_TX3 | FE_INT_TX2 | FE_INT_TX1 | FE_INT_TX0); 950 #endif 951 952 /* 953 * Configure GDMA forwarding 954 * - default all packets to CPU 955 * - Turn on auto-CRC 956 */ 957 #if 0 958 fe_write(sc, RA_FE_GDMA1_FWD_CFG, 959 (FE_GDMA_FWD_CFG_DIS_TX_CRC | FE_GDMA_FWD_CFG_DIS_TX_PAD)); 960 #endif 961 962 #if !defined(MT7628) 963 fe_write(sc, RA_FE_GDMA1_FWD_CFG, 964 FE_GDMA_FWD_CFG_JUMBO_LEN(MCLBYTES/1024) | 965 FE_GDMA_FWD_CFG_STRIP_RX_CRC | 966 FE_GDMA_FWD_CFG_IP4_CRC_EN | 967 FE_GDMA_FWD_CFG_TCP_CRC_EN | 968 FE_GDMA_FWD_CFG_UDP_CRC_EN); 969 #endif 970 971 /* CDMA also needs CRCs turned on */ 972 #if !defined(MT7628) 973 r = fe_read(sc, RA_FE_CDMA_CSG_CFG); 974 r |= (FE_CDMA_CSG_CFG_IP4_CRC_EN | FE_CDMA_CSG_CFG_UDP_CRC_EN | 975 FE_CDMA_CSG_CFG_TCP_CRC_EN); 976 fe_write(sc, RA_FE_CDMA_CSG_CFG, r); 977 #endif 978 979 /* Configure Flow Control Thresholds */ 980 #if defined(MT7628) 981 sw_write(sc, RA_ETH_SW_FCT0, 982 RA_ETH_SW_FCT0_FC_RLS_TH(0xc8) | 983 RA_ETH_SW_FCT0_FC_SET_TH(0xa0) | 984 RA_ETH_SW_FCT0_DROP_RLS_TH(0x78) | 985 RA_ETH_SW_FCT0_DROP_SET_TH(0x50)); 986 sw_write(sc, RA_ETH_SW_FCT1, 987 RA_ETH_SW_FCT1_PORT_TH(0x14)); 988 #elif defined(RT3883) 989 fe_write(sc, RA_FE_PSE_FQ_CFG, 990 FE_PSE_FQ_MAX_COUNT(0xff) | 991 FE_PSE_FQ_FC_RELEASE(0x90) | 992 FE_PSE_FQ_FC_ASSERT(0x80)); 993 #else 994 fe_write(sc, RA_FE_PSE_FQ_CFG, 995 FE_PSE_FQ_MAX_COUNT(0x80) | 996 FE_PSE_FQ_FC_RELEASE(0x50) | 997 FE_PSE_FQ_FC_ASSERT(0x40)); 998 #endif 999 1000 #ifdef RALINK_ETH_DEBUG 1001 #ifdef RA_FE_MDIO_CFG1 1002 printf("FE_MDIO_CFG1: 0x%08x\n", fe_read(sc, RA_FE_MDIO_CFG1)); 1003 #endif 1004 #ifdef RA_FE_MDIO_CFG2 1005 printf("FE_MDIO_CFG2: 0x%08x\n", fe_read(sc, RA_FE_MDIO_CFG2)); 1006 #endif 1007 printf("FE_PDMA_TX0_PTR: %08x\n", fe_read(sc, RA_FE_PDMA_TX0_PTR)); 1008 printf("FE_PDMA_TX0_COUNT: %08x\n", 1009 fe_read(sc, RA_FE_PDMA_TX0_COUNT)); 1010 printf("FE_PDMA_TX0_CPU_IDX: %08x\n", 1011 fe_read(sc, RA_FE_PDMA_TX0_CPU_IDX)); 1012 printf("FE_PDMA_TX0_DMA_IDX: %08x\n", 1013 fe_read(sc, RA_FE_PDMA_TX0_DMA_IDX)); 1014 printf("FE_PDMA_RX0_PTR: %08x\n", fe_read(sc, RA_FE_PDMA_RX0_PTR)); 1015 printf("FE_PDMA_RX0_COUNT: %08x\n", 1016 fe_read(sc, RA_FE_PDMA_RX0_COUNT)); 1017 printf("FE_PDMA_RX0_CPU_IDX: %08x\n", 1018 fe_read(sc, RA_FE_PDMA_RX0_CPU_IDX)); 1019 printf("FE_PDMA_RX0_DMA_IDX: %08x\n", 1020 fe_read(sc, RA_FE_PDMA_RX0_DMA_IDX)); 1021 printf("FE_PDMA_GLOBAL_CFG: %08x\n", 1022 fe_read(sc, RA_FE_PDMA_GLOBAL_CFG)); 1023 #ifdef RA_FE_GLOBAL_CFG 1024 printf("FE_GLOBAL_CFG: %08x\n", fe_read(sc, RA_FE_GLOBAL_CFG)); 1025 #endif 1026 #ifdef RA_FE_GDMA1_FWD_CFG 1027 printf("FE_GDMA1_FWD_CFG: %08x\n", 1028 fe_read(sc, RA_FE_GDMA1_FWD_CFG)); 1029 #endif 1030 #ifdef RA_FE_CDMA_CSG_CFG 1031 printf("FE_CDMA_CSG_CFG: %08x\n", fe_read(sc, RA_FE_CDMA_CSG_CFG)); 1032 #endif 1033 #ifdef RA_FE_PSE_FQ_CFG 1034 printf("FE_PSE_FQ_CFG: %08x\n", fe_read(sc, RA_FE_PSE_FQ_CFG)); 1035 #endif 1036 #endif 1037 1038 /* Force PSE Reset to get everything finalized */ 1039 #if defined(MT7628) 1040 #else 1041 fe_write(sc, RA_FE_GLOBAL_RESET, FE_GLOBAL_RESET_PSE); 1042 fe_write(sc, RA_FE_GLOBAL_RESET, 0); 1043 #endif 1044 } 1045 1046 /* 1047 * ralink_eth_init 1048 */ 1049 static int 1050 ralink_eth_init(struct ifnet *ifp) 1051 { 1052 RALINK_DEBUG_FUNC_ENTRY(); 1053 ralink_eth_softc_t * const sc = ifp->if_softc; 1054 int error; 1055 1056 error = ralink_eth_enable(sc); 1057 if (!error) { 1058 /* Note that the interface is now running. */ 1059 ifp->if_flags |= IFF_RUNNING; 1060 ifp->if_flags &= ~IFF_OACTIVE; 1061 } 1062 1063 return error; 1064 } 1065 1066 /* 1067 * ralink_eth_rxdrain 1068 * 1069 * Drain the receive queue. 1070 */ 1071 static void 1072 ralink_eth_rxdrain(ralink_eth_softc_t *sc) 1073 { 1074 RALINK_DEBUG_FUNC_ENTRY(); 1075 1076 for (int i = 0; i < RALINK_ETH_NUM_RX_DESC; i++) { 1077 struct ralink_eth_rxstate *rxs = &sc->sc_rxstate[i]; 1078 if (rxs->rxs_mbuf != NULL) { 1079 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 1080 m_freem(rxs->rxs_mbuf); 1081 rxs->rxs_mbuf = NULL; 1082 } 1083 } 1084 } 1085 1086 /* 1087 * ralink_eth_stop 1088 */ 1089 static void 1090 ralink_eth_stop(struct ifnet *ifp, int disable) 1091 { 1092 RALINK_DEBUG_FUNC_ENTRY(); 1093 ralink_eth_softc_t * const sc = ifp->if_softc; 1094 1095 ralink_eth_disable(sc); 1096 1097 /* Mark the interface down and cancel the watchdog timer. */ 1098 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1099 ifp->if_timer = 0; 1100 } 1101 1102 /* 1103 * ralink_eth_add_rxbuf 1104 */ 1105 static int 1106 ralink_eth_add_rxbuf(ralink_eth_softc_t *sc, int idx) 1107 { 1108 RALINK_DEBUG_FUNC_ENTRY(); 1109 struct ralink_eth_rxstate * const rxs = &sc->sc_rxstate[idx]; 1110 struct mbuf *m; 1111 int error; 1112 1113 MGETHDR(m, M_DONTWAIT, MT_DATA); 1114 if (m == NULL) { 1115 printf("MGETHDR failed\n"); 1116 sc->sc_evcnt_add_rxbuf_hdr_fail.ev_count++; 1117 return ENOBUFS; 1118 } 1119 1120 MCLGET(m, M_DONTWAIT); 1121 if ((m->m_flags & M_EXT) == 0) { 1122 m_freem(m); 1123 printf("MCLGET failed\n"); 1124 sc->sc_evcnt_add_rxbuf_mcl_fail.ev_count++; 1125 return ENOBUFS; 1126 } 1127 1128 m->m_data = m->m_ext.ext_buf; 1129 rxs->rxs_mbuf = m; 1130 1131 error = bus_dmamap_load(sc->sc_dmat, rxs->rxs_dmamap, m->m_ext.ext_buf, 1132 m->m_ext.ext_size, NULL, BUS_DMA_READ | BUS_DMA_NOWAIT); 1133 if (error) { 1134 aprint_error_dev(sc->sc_dev, "can't load rx DMA map %d, " 1135 "error=%d\n", idx, error); 1136 panic(__func__); /* XXX */ 1137 } 1138 1139 sc->sc_rxdesc[idx].data_ptr = MIPS_KSEG0_TO_PHYS( 1140 rxs->rxs_dmamap->dm_segs[0].ds_addr + RALINK_ETHER_ALIGN); 1141 sc->sc_rxdesc[idx].rxd_info1 = RXD_LAST0; 1142 1143 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 1144 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 1145 1146 return 0; 1147 } 1148 1149 1150 /* 1151 * ralink_eth_start 1152 */ 1153 static void 1154 ralink_eth_start(struct ifnet *ifp) 1155 { 1156 RALINK_DEBUG_FUNC_ENTRY(); 1157 ralink_eth_softc_t * const sc = ifp->if_softc; 1158 struct mbuf *m0, *m = NULL; 1159 struct ralink_eth_txstate *txs; 1160 bus_dmamap_t dmamap; 1161 int tx_cpu_idx; 1162 int error; 1163 int s; 1164 1165 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) 1166 return; 1167 1168 s = splnet(); 1169 1170 tx_cpu_idx = fe_read(sc, RA_FE_PDMA_TX0_CPU_IDX); 1171 1172 /* 1173 * Loop through the send queue, setting up transmit descriptors 1174 * until we drain the queue, or use up all available 1175 * transmit descriptors. 1176 */ 1177 while ((txs = SIMPLEQ_FIRST(&sc->sc_txfreeq)) != NULL) { 1178 /* Grab a packet off the queue. */ 1179 IFQ_POLL(&ifp->if_snd, m0); 1180 if (m0 == NULL) 1181 break; 1182 1183 dmamap = txs->txs_dmamap; 1184 1185 if (m0->m_pkthdr.len < RALINK_MIN_BUF) { 1186 int padlen = 64 - m0->m_pkthdr.len; 1187 m_copyback(m0, m0->m_pkthdr.len, padlen, 1188 sc->ralink_zero_buf); 1189 /* TODO : need some checking here */ 1190 } 1191 1192 /* 1193 * Do we need to align the buffer 1194 * or does the DMA map load fail? 1195 */ 1196 if (bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, m0, 1197 BUS_DMA_WRITE | BUS_DMA_NOWAIT) != 0) { 1198 1199 /* Allocate a new mbuf for re-alignment */ 1200 MGETHDR(m, M_DONTWAIT, MT_DATA); 1201 if (m == NULL) { 1202 aprint_error_dev(sc->sc_dev, 1203 "unable to allocate aligned Tx mbuf\n"); 1204 break; 1205 } 1206 MCLAIM(m, &sc->sc_ethercom.ec_tx_mowner); 1207 if (m0->m_pkthdr.len > MHLEN) { 1208 MCLGET(m, M_DONTWAIT); 1209 if ((m->m_flags & M_EXT) == 0) { 1210 aprint_error_dev(sc->sc_dev, 1211 "unable to allocate Tx cluster\n"); 1212 m_freem(m); 1213 break; 1214 } 1215 } 1216 m_copydata(m0, 0, m0->m_pkthdr.len, mtod(m, void *)); 1217 m->m_pkthdr.len = m->m_len = m0->m_pkthdr.len; 1218 error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, m, 1219 BUS_DMA_WRITE | BUS_DMA_NOWAIT); 1220 if (error) { 1221 aprint_error_dev(sc->sc_dev, 1222 "unable to load Tx buffer error=%d\n", 1223 error); 1224 m_freem(m); 1225 break; 1226 } 1227 } 1228 1229 IFQ_DEQUEUE(&ifp->if_snd, m0); 1230 /* did we copy the buffer out already? */ 1231 if (m != NULL) { 1232 m_freem(m0); 1233 m0 = m; 1234 } 1235 1236 /* Sync the DMA map. */ 1237 bus_dmamap_sync(sc->sc_dmat, dmamap, 0, dmamap->dm_mapsize, 1238 BUS_DMASYNC_PREWRITE); 1239 1240 /* Initialize the transmit descriptor */ 1241 sc->sc_txdesc[tx_cpu_idx].data_ptr0 = 1242 MIPS_KSEG0_TO_PHYS(dmamap->dm_segs[0].ds_addr); 1243 sc->sc_txdesc[tx_cpu_idx].txd_info1 = 1244 TXD_LEN0(dmamap->dm_segs[0].ds_len) | TXD_LAST0; 1245 sc->sc_txdesc[tx_cpu_idx].txd_info2 = 1246 TXD_QN(3) | TXD_PN(TXD_PN_GDMA1); 1247 sc->sc_txdesc[tx_cpu_idx].txd_info2 = TXD_QN(3) | 1248 TXD_PN(TXD_PN_GDMA1) | TXD_VEN | 1249 // TXD_VIDX(pt->vlan_id) | 1250 TXD_TCP_EN | TXD_UDP_EN | TXD_IP_EN; 1251 1252 RALINK_DEBUG(RALINK_DEBUG_REG,"+tx(%d) 0x%08x: 0x%08x\n", 1253 tx_cpu_idx, (int)&sc->sc_txdesc[tx_cpu_idx].data_ptr0, 1254 sc->sc_txdesc[tx_cpu_idx].data_ptr0); 1255 RALINK_DEBUG(RALINK_DEBUG_REG,"+tx(%d) 0x%08x: 0x%08x\n", 1256 tx_cpu_idx, (int)&sc->sc_txdesc[tx_cpu_idx].txd_info1, 1257 sc->sc_txdesc[tx_cpu_idx].txd_info1); 1258 RALINK_DEBUG(RALINK_DEBUG_REG,"+tx(%d) 0x%08x: 0x%08x\n", 1259 tx_cpu_idx, (int)&sc->sc_txdesc[tx_cpu_idx].data_ptr1, 1260 sc->sc_txdesc[tx_cpu_idx].data_ptr1); 1261 RALINK_DEBUG(RALINK_DEBUG_REG,"+tx(%d) 0x%08x: 0x%08x\n", 1262 tx_cpu_idx, (int)&sc->sc_txdesc[tx_cpu_idx].txd_info2, 1263 sc->sc_txdesc[tx_cpu_idx].txd_info2); 1264 1265 /* sync the descriptor we're using. */ 1266 bus_dmamap_sync(sc->sc_dmat, sc->sc_pdmamap, 1267 (int)&sc->sc_txdesc[tx_cpu_idx] - (int)sc->sc_descs, 1268 sizeof(struct ralink_tx_desc), 1269 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1270 1271 /* 1272 * Store a pointer to the packet so we can free it later, 1273 * and remember what txdirty will be once the packet is 1274 * done. 1275 */ 1276 txs->txs_mbuf = m0; 1277 sc->sc_pending_tx++; 1278 if (txs->txs_idx != tx_cpu_idx) { 1279 panic("txs_idx doesn't match %d != %d\n", 1280 txs->txs_idx, tx_cpu_idx); 1281 } 1282 1283 SIMPLEQ_REMOVE_HEAD(&sc->sc_txfreeq, txs_q); 1284 SIMPLEQ_INSERT_TAIL(&sc->sc_txdirtyq, txs, txs_q); 1285 1286 /* Pass the packet to any BPF listeners. */ 1287 bpf_mtap(ifp, m0, BPF_D_OUT); 1288 1289 /* Set a watchdog timer in case the chip flakes out. */ 1290 ifp->if_timer = 5; 1291 1292 tx_cpu_idx = (tx_cpu_idx + 1) % RALINK_ETH_NUM_TX_DESC; 1293 1294 /* Write back the tx_cpu_idx */ 1295 fe_write(sc, RA_FE_PDMA_TX0_CPU_IDX, tx_cpu_idx); 1296 } 1297 1298 if (txs == NULL) { 1299 /* No more slots left; notify upper layer. */ 1300 ifp->if_flags |= IFF_OACTIVE; 1301 } 1302 1303 splx(s); 1304 } 1305 1306 /* 1307 * ralink_eth_watchdog 1308 * 1309 * Watchdog timer handler. 1310 */ 1311 static void 1312 ralink_eth_watchdog(struct ifnet *ifp) 1313 { 1314 RALINK_DEBUG_FUNC_ENTRY(); 1315 ralink_eth_softc_t * const sc = ifp->if_softc; 1316 bool doing_transmit; 1317 1318 sc->sc_evcnt_watchdog.ev_count++; 1319 doing_transmit = !SIMPLEQ_EMPTY(&sc->sc_txdirtyq); 1320 1321 if (doing_transmit) { 1322 RALINK_DEBUG(RALINK_DEBUG_ERROR, "%s: transmit timeout\n", 1323 ifp->if_xname); 1324 ifp->if_oerrors++; 1325 sc->sc_evcnt_wd_tx.ev_count++; 1326 } else { 1327 RALINK_DEBUG(RALINK_DEBUG_ERROR, 1328 "%s: spurious watchog timeout\n", ifp->if_xname); 1329 sc->sc_evcnt_wd_spurious.ev_count++; 1330 return; 1331 } 1332 1333 sc->sc_evcnt_wd_reactivate.ev_count++; 1334 const int s = splnet(); 1335 /* deactive the active partitions, retaining the active information */ 1336 ralink_eth_disable(sc); 1337 ralink_eth_enable(sc); 1338 splx(s); 1339 1340 /* Try to get more packets going. */ 1341 ralink_eth_start(ifp); 1342 } 1343 1344 /* 1345 * ralink_eth_ioctl 1346 * 1347 * Handle control requests from the operator. 1348 */ 1349 static int 1350 ralink_eth_ioctl(struct ifnet *ifp, u_long cmd, void *data) 1351 { 1352 RALINK_DEBUG_FUNC_ENTRY(); 1353 struct ifdrv * const ifd = (struct ifdrv *) data; 1354 ralink_eth_softc_t * const sc = ifp->if_softc; 1355 int s, error = 0; 1356 1357 RALINK_DEBUG(RALINK_DEBUG_INFO, "ifp: %p cmd: %lu data: %p\n", 1358 ifp, cmd, data); 1359 1360 s = splnet(); 1361 1362 switch (cmd) { 1363 case SIOCSDRVSPEC: 1364 switch (ifd->ifd_cmd) { 1365 #if 0 1366 case ETH_SWITCH_CMD_PORT_MODE: 1367 /* len parameter is the mode */ 1368 pt->mode = (int) ifd->ifd_len; 1369 ralink_eth_configure_switch(pt->sc_reth); 1370 break; 1371 #endif 1372 default: 1373 error = EINVAL; 1374 } 1375 break; 1376 default: 1377 error = ether_ioctl(ifp, cmd, data); 1378 if (error == ENETRESET) { 1379 if (ifp->if_flags & IFF_RUNNING) { 1380 /* 1381 * Multicast list has changed. Set the 1382 * hardware filter accordingly. 1383 */ 1384 RALINK_DEBUG(RALINK_DEBUG_INFO, "TODO!!!"); 1385 #if 0 1386 ralink_eth_filter_setup(sc); 1387 #endif 1388 } 1389 error = 0; 1390 } 1391 break; 1392 } 1393 1394 splx(s); 1395 1396 /* Try to get more packets going. */ 1397 if (sc->sc_ih != NULL) 1398 ralink_eth_start(ifp); 1399 1400 return error; 1401 } 1402 1403 /* 1404 * ralink_eth_intr 1405 * 1406 */ 1407 static int 1408 ralink_eth_intr(void *arg) 1409 { 1410 RALINK_DEBUG_FUNC_ENTRY(); 1411 ralink_eth_softc_t * const sc = arg; 1412 1413 for (u_int n = 0;; n = 1) { 1414 u_int32_t status = fe_read(sc, RA_FE_INT_STATUS); 1415 fe_write(sc, RA_FE_INT_STATUS, ~0); 1416 RALINK_DEBUG(RALINK_DEBUG_REG,"%s() status: 0x%08x\n", 1417 __func__, status); 1418 #if defined(MT7628) 1419 if ((status & (RA_FE_INT_RX_DONE_INT1 | RA_FE_INT_RX_DONE_INT0 | 1420 RA_FE_INT_TX_DONE_INT3 | RA_FE_INT_TX_DONE_INT2 | 1421 RA_FE_INT_TX_DONE_INT1 | RA_FE_INT_TX_DONE_INT0)) == 0) { 1422 if (n == 0) 1423 sc->sc_evcnt_spurious_intr.ev_count++; 1424 return (n != 0); 1425 } 1426 1427 if (status & (RA_FE_INT_RX_DONE_INT1 | RA_FE_INT_RX_DONE_INT0)) 1428 ralink_eth_rxintr(sc); 1429 1430 if (status & (RA_FE_INT_TX_DONE_INT3 | RA_FE_INT_TX_DONE_INT2 | 1431 RA_FE_INT_TX_DONE_INT1 | RA_FE_INT_TX_DONE_INT0)) 1432 ralink_eth_txintr(sc); 1433 #else 1434 if ((status & (FE_INT_RX | FE_INT_TX0)) == 0) { 1435 if (n == 0) 1436 sc->sc_evcnt_spurious_intr.ev_count++; 1437 return (n != 0); 1438 } 1439 1440 if (status & FE_INT_RX) 1441 ralink_eth_rxintr(sc); 1442 1443 if (status & FE_INT_TX0) 1444 ralink_eth_txintr(sc); 1445 #endif 1446 } 1447 1448 /* Try to get more packets going. */ 1449 if_schedule_deferred_start(&sc->sc_ethercom.ec_if); 1450 1451 return 1; 1452 } 1453 1454 /* 1455 * ralink_eth_rxintr 1456 */ 1457 static void 1458 ralink_eth_rxintr(ralink_eth_softc_t *sc) 1459 { 1460 RALINK_DEBUG_FUNC_ENTRY(); 1461 struct ifnet * const ifp = &sc->sc_ethercom.ec_if; 1462 struct ralink_eth_rxstate *rxs; 1463 struct mbuf *m; 1464 int len; 1465 int rx_cpu_idx; 1466 1467 KASSERT(curcpu()->ci_cpl >= IPL_NET); 1468 sc->sc_evcnt_rxintr.ev_count++; 1469 rx_cpu_idx = fe_read(sc, RA_FE_PDMA_RX0_CPU_IDX); 1470 1471 for (;;) { 1472 rx_cpu_idx = (rx_cpu_idx + 1) % RALINK_ETH_NUM_RX_DESC; 1473 1474 rxs = &sc->sc_rxstate[rx_cpu_idx]; 1475 1476 bus_dmamap_sync(sc->sc_dmat, sc->sc_pdmamap, 1477 (int)&sc->sc_rxdesc[rx_cpu_idx] - (int)sc->sc_descs, 1478 sizeof(struct ralink_rx_desc), 1479 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1480 1481 RALINK_DEBUG(RALINK_DEBUG_REG,"rx(%d) 0x%08x: 0x%08x\n", 1482 rx_cpu_idx, (int)&sc->sc_rxdesc[rx_cpu_idx].data_ptr, 1483 sc->sc_rxdesc[rx_cpu_idx].data_ptr); 1484 RALINK_DEBUG(RALINK_DEBUG_REG,"rx(%d) 0x%08x: 0x%08x\n", 1485 rx_cpu_idx, (int)&sc->sc_rxdesc[rx_cpu_idx].rxd_info1, 1486 sc->sc_rxdesc[rx_cpu_idx].rxd_info1); 1487 RALINK_DEBUG(RALINK_DEBUG_REG,"rx(%d) 0x%08x: 0x%08x\n", 1488 rx_cpu_idx, (int)&sc->sc_rxdesc[rx_cpu_idx].unused, 1489 sc->sc_rxdesc[rx_cpu_idx].unused); 1490 RALINK_DEBUG(RALINK_DEBUG_REG,"rx(%d) 0x%08x: 0x%08x\n", 1491 rx_cpu_idx, (int)&sc->sc_rxdesc[rx_cpu_idx].rxd_info2, 1492 sc->sc_rxdesc[rx_cpu_idx].rxd_info2); 1493 1494 if (!(sc->sc_rxdesc[rx_cpu_idx].rxd_info1 & RXD_DDONE)) 1495 break; 1496 1497 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 1498 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 1499 1500 /* 1501 * No errors; receive the packet. 1502 * Note the chip includes the CRC with every packet. 1503 */ 1504 len = RXD_LEN0(sc->sc_rxdesc[rx_cpu_idx].rxd_info1); 1505 1506 RALINK_DEBUG(RALINK_DEBUG_REG,"rx(%d) packet rx %d bytes\n", 1507 rx_cpu_idx, len); 1508 1509 /* 1510 * Allocate a new mbuf cluster. If that fails, we are 1511 * out of memory, and must drop the packet and recycle 1512 * the buffer that's already attached to this descriptor. 1513 */ 1514 m = rxs->rxs_mbuf; 1515 if (ralink_eth_add_rxbuf(sc, rx_cpu_idx) != 0) 1516 break; 1517 m->m_data += RALINK_ETHER_ALIGN; 1518 m->m_pkthdr.len = m->m_len = len; 1519 1520 #ifdef RALINK_ETH_DEBUG 1521 { 1522 struct ether_header *eh = mtod(m, struct ether_header *); 1523 printf("rx: eth_dst: %s ", ether_sprintf(eh->ether_dhost)); 1524 printf("rx: eth_src: %s type: 0x%04x \n", 1525 ether_sprintf(eh->ether_shost), ntohs(eh->ether_type)); 1526 printf("0x14: %08x\n", *(volatile unsigned int *)(0xb0110014)); 1527 printf("0x98: %08x\n", *(volatile unsigned int *)(0xb0110098)); 1528 1529 unsigned char * s = mtod(m, unsigned char *); 1530 for (int j = 0; j < 32; j++) 1531 printf("%02x%c", *(s + j), 1532 (j == 15 || j == 31) ? '\n' : ' '); 1533 } 1534 #endif 1535 1536 /* 1537 * claim the buffer here since we can't do it at 1538 * allocation time due to the SW partitions 1539 */ 1540 MCLAIM(m, &sc->sc_ethercom.ec_rx_mowner); 1541 1542 /* push it up the inteface */ 1543 m_set_rcvif(m, ifp); 1544 1545 #ifdef RALINK_ETH_DEBUG 1546 { 1547 struct ether_header *eh = mtod(m, struct ether_header *); 1548 printf("rx: eth_dst: %s ", ether_sprintf(eh->ether_dhost)); 1549 printf("rx: eth_src: %s type: 0x%04x\n", 1550 ether_sprintf(eh->ether_shost), ntohs(eh->ether_type)); 1551 printf("0x14: %08x\n", *(volatile unsigned int *)(0xb0110014)); 1552 printf("0x98: %08x\n", *(volatile unsigned int *)(0xb0110098)); 1553 1554 unsigned char * s = mtod(m, unsigned char *); 1555 for (int j = 0; j < 32; j++) 1556 printf("%02x%c", *(s + j), 1557 (j == 15 || j == 31) ? '\n' : ' '); 1558 } 1559 #endif 1560 1561 /* 1562 * XXX: M_CSUM_TCPv4 and M_CSUM_UDPv4 do not currently work when 1563 * using PF's ROUTETO option for load balancing. 1564 */ 1565 m->m_pkthdr.csum_flags |= M_CSUM_IPv4; 1566 1567 /* Pass it on. */ 1568 sc->sc_evcnt_input.ev_count++; 1569 if_percpuq_enqueue(ifp->if_percpuq, m); 1570 1571 fe_write(sc, RA_FE_PDMA_RX0_CPU_IDX, rx_cpu_idx); 1572 } 1573 } 1574 1575 /* 1576 * ralink_eth_txintr 1577 */ 1578 static void 1579 ralink_eth_txintr(ralink_eth_softc_t *sc) 1580 { 1581 RALINK_DEBUG_FUNC_ENTRY(); 1582 struct ralink_eth_txstate *txs; 1583 1584 KASSERT(curcpu()->ci_cpl >= IPL_NET); 1585 sc->sc_evcnt_txintr.ev_count++; 1586 1587 /* 1588 * Go through our Tx list and free mbufs for those 1589 * frames that have been transmitted. 1590 */ 1591 while ((txs = SIMPLEQ_FIRST(&sc->sc_txdirtyq)) != NULL) { 1592 bus_dmamap_sync(sc->sc_dmat, sc->sc_pdmamap, 1593 (int)&sc->sc_txdesc[txs->txs_idx] - (int)sc->sc_descs, 1594 sizeof(struct ralink_tx_desc), 1595 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1596 1597 RALINK_DEBUG(RALINK_DEBUG_REG,"-tx(%d) 0x%08x: 0x%08x\n", 1598 txs->txs_idx, (int)&sc->sc_txdesc[txs->txs_idx].data_ptr0, 1599 sc->sc_txdesc[txs->txs_idx].data_ptr0); 1600 RALINK_DEBUG(RALINK_DEBUG_REG,"-tx(%d) 0x%08x: 0x%08x\n", 1601 txs->txs_idx, (int)&sc->sc_txdesc[txs->txs_idx].txd_info1, 1602 sc->sc_txdesc[txs->txs_idx].txd_info1); 1603 RALINK_DEBUG(RALINK_DEBUG_REG,"-tx(%d) 0x%08x: 0x%08x\n", 1604 txs->txs_idx, (int)&sc->sc_txdesc[txs->txs_idx].data_ptr1, 1605 sc->sc_txdesc[txs->txs_idx].data_ptr1); 1606 RALINK_DEBUG(RALINK_DEBUG_REG,"-tx(%d) 0x%08x: 0x%08x\n", 1607 txs->txs_idx, (int)&sc->sc_txdesc[txs->txs_idx].txd_info2, 1608 sc->sc_txdesc[txs->txs_idx].txd_info2); 1609 1610 /* we're finished if the current tx isn't done */ 1611 if (!(sc->sc_txdesc[txs->txs_idx].txd_info1 & TXD_DDONE)) 1612 break; 1613 1614 RALINK_DEBUG(RALINK_DEBUG_REG,"-tx(%d) transmitted\n", 1615 txs->txs_idx); 1616 1617 SIMPLEQ_REMOVE_HEAD(&sc->sc_txdirtyq, txs_q); 1618 1619 bus_dmamap_sync(sc->sc_dmat, txs->txs_dmamap, 0, 1620 txs->txs_dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1621 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 1622 m_freem(txs->txs_mbuf); 1623 txs->txs_mbuf = NULL; 1624 1625 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 1626 1627 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1628 ifp->if_flags &= ~IFF_OACTIVE; 1629 ifp->if_opackets++; 1630 sc->sc_evcnt_output.ev_count++; 1631 1632 if (--sc->sc_pending_tx == 0) 1633 ifp->if_timer = 0; 1634 } 1635 } 1636 1637 /* 1638 * ralink_eth_mdio_enable 1639 */ 1640 #if defined(RT3050) || defined(RT3052) 1641 static void 1642 ralink_eth_mdio_enable(ralink_eth_softc_t *sc, bool enable) 1643 { 1644 uint32_t data = sy_read(sc, RA_SYSCTL_GPIOMODE); 1645 1646 if (enable) 1647 data &= ~GPIOMODE_MDIO; 1648 else 1649 data |= GPIOMODE_MDIO; 1650 1651 sy_write(sc, RA_SYSCTL_GPIOMODE, data); 1652 } 1653 #else 1654 #define ralink_eth_mdio_enable(sc, enable) 1655 #endif 1656 1657 /* 1658 * ralink_eth_mii_statchg 1659 */ 1660 static void 1661 ralink_eth_mii_statchg(struct ifnet *ifp) 1662 { 1663 #if 0 1664 ralink_eth_softc_t * const sc = ifp->if_softc; 1665 1666 #endif 1667 } 1668 1669 /* 1670 * ralink_eth_mii_tick 1671 * 1672 * One second timer, used to tick the MIIs. 1673 */ 1674 static void 1675 ralink_eth_mii_tick(void *arg) 1676 { 1677 ralink_eth_softc_t * const sc = arg; 1678 1679 const int s = splnet(); 1680 mii_tick(&sc->sc_mii); 1681 splx(s); 1682 1683 callout_reset(&sc->sc_tick_callout, hz, ralink_eth_mii_tick, sc); 1684 } 1685 1686 /* 1687 * ralink_eth_mii_read 1688 */ 1689 static int 1690 ralink_eth_mii_read(device_t self, int phy_addr, int phy_reg, uint16_t *val) 1691 { 1692 ralink_eth_softc_t *sc = device_private(self); 1693 KASSERT(sc != NULL); 1694 #if 0 1695 printf("%s() phy_addr: %d phy_reg: %d\n", __func__, phy_addr, phy_reg); 1696 #endif 1697 #if defined(RT3050) || defined(RT3052) || defined(MT7628) 1698 if (phy_addr > 5) 1699 return -1; 1700 #endif 1701 1702 /* We enable mdio gpio purpose register, and disable it when exit. */ 1703 ralink_eth_mdio_enable(sc, true); 1704 1705 /* 1706 * make sure previous read operation is complete 1707 * TODO: timeout (linux uses jiffies to measure 5 seconds) 1708 */ 1709 for (;;) { 1710 /* rd_rdy: read operation is complete */ 1711 #if defined(RT3050) || defined(RT3052) || defined(MT7628) 1712 if ((sw_read(sc, RA_ETH_SW_PCTL1) & PCTL1_RD_DONE) == 0) 1713 break; 1714 #else 1715 if ((fe_read(sc, RA_FE_MDIO_ACCESS) & MDIO_ACCESS_TRG) == 0) 1716 break; 1717 #endif 1718 } 1719 1720 #if defined(RT3050) || defined(RT3052) || defined(MT7628) 1721 sw_write(sc, RA_ETH_SW_PCTL0, 1722 PCTL0_RD_CMD | PCTL0_REG(phy_reg) | PCTL0_ADDR(phy_addr)); 1723 #else 1724 fe_write(sc, RA_FE_MDIO_ACCESS, 1725 MDIO_ACCESS_PHY_ADDR(phy_addr) | MDIO_ACCESS_REG(phy_reg)); 1726 fe_write(sc, RA_FE_MDIO_ACCESS, 1727 MDIO_ACCESS_PHY_ADDR(phy_addr) | MDIO_ACCESS_REG(phy_reg) | 1728 MDIO_ACCESS_TRG); 1729 #endif 1730 1731 /* 1732 * make sure read operation is complete 1733 * TODO: timeout (linux uses jiffies to measure 5 seconds) 1734 */ 1735 for (;;) { 1736 #if defined(RT3050) || defined(RT3052) || defined(MT7628) 1737 if ((sw_read(sc, RA_ETH_SW_PCTL1) & PCTL1_RD_DONE) != 0) { 1738 *val = PCTL1_RD_VAL( 1739 sw_read(sc, RA_ETH_SW_PCTL1)); 1740 ralink_eth_mdio_enable(sc, false); 1741 return 0; 1742 } 1743 #else 1744 if ((fe_read(sc, RA_FE_MDIO_ACCESS) & MDIO_ACCESS_TRG) == 0) { 1745 *val = MDIO_ACCESS_DATA( 1746 fe_read(sc, RA_FE_MDIO_ACCESS)); 1747 ralink_eth_mdio_enable(sc, false); 1748 return 0; 1749 } 1750 #endif 1751 } 1752 } 1753 1754 /* 1755 * ralink_eth_mii_write 1756 */ 1757 static int 1758 ralink_eth_mii_write(device_t self, int phy_addr, int phy_reg, uint16_t val) 1759 { 1760 ralink_eth_softc_t *sc = device_private(self); 1761 KASSERT(sc != NULL); 1762 #if 0 1763 printf("%s() phy_addr: %d phy_reg: %d val: 0x%04x\n", 1764 __func__, phy_addr, phy_reg, val); 1765 #endif 1766 ralink_eth_mdio_enable(sc, true); 1767 1768 /* 1769 * make sure previous write operation is complete 1770 * TODO: timeout (linux uses jiffies to measure 5 seconds) 1771 */ 1772 for (;;) { 1773 #if defined(RT3050) || defined(RT3052) || defined(MT7628) 1774 if ((sw_read(sc, RA_ETH_SW_PCTL1) & PCTL1_RD_DONE) == 0) 1775 break; 1776 #else 1777 if ((fe_read(sc, RA_FE_MDIO_ACCESS) & MDIO_ACCESS_TRG) == 0) 1778 break; 1779 #endif 1780 } 1781 1782 #if defined(RT3050) || defined(RT3052) || defined(MT7628) 1783 sw_write(sc, RA_ETH_SW_PCTL0, 1784 PCTL0_WR_CMD | PCTL0_WR_VAL(val) | PCTL0_REG(phy_reg) | 1785 PCTL0_ADDR(phy_addr)); 1786 #else 1787 fe_write(sc, RA_FE_MDIO_ACCESS, 1788 MDIO_ACCESS_WR | MDIO_ACCESS_PHY_ADDR(phy_addr) | 1789 MDIO_ACCESS_REG(phy_reg) | MDIO_ACCESS_DATA(val)); 1790 fe_write(sc, RA_FE_MDIO_ACCESS, 1791 MDIO_ACCESS_WR | MDIO_ACCESS_PHY_ADDR(phy_addr) | 1792 MDIO_ACCESS_REG(phy_reg) | MDIO_ACCESS_DATA(val) | 1793 MDIO_ACCESS_TRG); 1794 #endif 1795 1796 1797 /* make sure write operation is complete */ 1798 for (;;) { 1799 #if defined(RT3050) || defined(RT3052) || defined(MT7628) 1800 if ((sw_read(sc, RA_ETH_SW_PCTL1) & PCTL1_WR_DONE) != 0) { 1801 ralink_eth_mdio_enable(sc, false); 1802 return 0; 1803 } 1804 #else 1805 if ((fe_read(sc, RA_FE_MDIO_ACCESS) & MDIO_ACCESS_TRG) == 0) { 1806 ralink_eth_mdio_enable(sc, false); 1807 return 0; 1808 } 1809 #endif 1810 } 1811 } 1812
Indexes created Thu Oct 02 14:10:14 GMT 2025