1 1.8 riastrad /* $NetBSD: ralink_ohci.c,v 1.8 2025/03/31 14:46:42 riastradh Exp $ */ 2 1.2 matt /*- 3 1.2 matt * Copyright (c) 2011 CradlePoint Technology, Inc. 4 1.2 matt * All rights reserved. 5 1.2 matt * 6 1.2 matt * 7 1.2 matt * Redistribution and use in source and binary forms, with or without 8 1.2 matt * modification, are permitted provided that the following conditions 9 1.2 matt * are met: 10 1.2 matt * 1. Redistributions of source code must retain the above copyright 11 1.2 matt * notice, this list of conditions and the following disclaimer. 12 1.2 matt * 2. Redistributions in binary form must reproduce the above copyright 13 1.2 matt * notice, this list of conditions and the following disclaimer in the 14 1.2 matt * documentation and/or other materials provided with the distribution. 15 1.2 matt * 16 1.2 matt * THIS SOFTWARE IS PROVIDED BY CRADLEPOINT TECHNOLOGY, INC. AND CONTRIBUTORS 17 1.2 matt * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 18 1.2 matt * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 19 1.2 matt * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS 20 1.2 matt * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 21 1.2 matt * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 22 1.2 matt * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 23 1.2 matt * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 24 1.2 matt * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 25 1.2 matt * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 26 1.2 matt * POSSIBILITY OF SUCH DAMAGE. 27 1.2 matt */ 28 1.2 matt 29 1.2 matt /* ralink_ohci.c -- Ralink OHCI USB Driver */ 30 1.2 matt 31 1.2 matt #include "ehci.h" 32 1.2 matt 33 1.2 matt #include <sys/cdefs.h> 34 1.8 riastrad __KERNEL_RCSID(0, "$NetBSD: ralink_ohci.c,v 1.8 2025/03/31 14:46:42 riastradh Exp $"); 35 1.2 matt 36 1.2 matt #include <sys/param.h> 37 1.2 matt #include <sys/bus.h> 38 1.2 matt 39 1.2 matt #include <dev/usb/usb.h> 40 1.2 matt #include <dev/usb/usbdi.h> 41 1.2 matt #include <dev/usb/usbdivar.h> 42 1.2 matt #include <dev/usb/usb_mem.h> 43 1.2 matt 44 1.2 matt #include <dev/usb/ohcireg.h> 45 1.2 matt #include <dev/usb/ohcivar.h> 46 1.2 matt 47 1.2 matt #include <mips/ralink/ralink_var.h> 48 1.2 matt #include <mips/ralink/ralink_reg.h> 49 1.2 matt #include <mips/ralink/ralink_usbhcvar.h> 50 1.2 matt 51 1.2 matt #define OREAD4(sc, a) bus_space_read_4((sc)->iot, (sc)->ioh, (a)) 52 1.2 matt #define OWRITE4(sc, a, x) bus_space_write_4((sc)->iot, (sc)->ioh, (a), (x)) 53 1.2 matt 54 1.2 matt struct ralink_ohci_softc { 55 1.2 matt struct ohci_softc sc_ohci; 56 1.2 matt #if NEHCI > 0 57 1.2 matt struct ralink_usb_hc sc_hc; 58 1.2 matt #endif 59 1.2 matt void *sc_ih; 60 1.2 matt }; 61 1.2 matt 62 1.2 matt static int ralink_ohci_match(device_t, cfdata_t, void *); 63 1.2 matt static void ralink_ohci_attach(device_t, device_t, void *); 64 1.2 matt static int ralink_ohci_detach(device_t, int); 65 1.2 matt 66 1.2 matt CFATTACH_DECL2_NEW(ralink_ohci, sizeof(struct ralink_ohci_softc), 67 1.2 matt ralink_ohci_match, ralink_ohci_attach, ralink_ohci_detach, 68 1.2 matt ohci_activate, NULL, ohci_childdet); 69 1.2 matt 70 1.2 matt /* 71 1.2 matt * ralink_ohci_match 72 1.2 matt */ 73 1.2 matt static int 74 1.2 matt ralink_ohci_match(device_t parent, cfdata_t cf, void *aux) 75 1.2 matt { 76 1.2 matt return 1; 77 1.2 matt } 78 1.2 matt 79 1.2 matt /* 80 1.2 matt * ralink_ohci_attach 81 1.2 matt */ 82 1.2 matt static void 83 1.2 matt ralink_ohci_attach(device_t parent, device_t self, void *aux) 84 1.2 matt { 85 1.2 matt struct ralink_ohci_softc * const sc = device_private(self); 86 1.3 matt const struct mainbus_attach_args * const ma = aux; 87 1.2 matt int error; 88 1.2 matt #ifdef RALINK_OHCI_DEBUG 89 1.2 matt const char * const devname = device_xname(self); 90 1.2 matt #endif 91 1.2 matt 92 1.2 matt aprint_naive(": OHCI USB controller\n"); 93 1.2 matt aprint_normal(": OHCI USB controller\n"); 94 1.2 matt 95 1.2 matt sc->sc_ohci.sc_dev = self; 96 1.4 skrll sc->sc_ohci.sc_bus.ub_hcpriv = sc; 97 1.2 matt sc->sc_ohci.iot = ma->ma_memt; 98 1.4 skrll sc->sc_ohci.sc_bus.ub_dmatag = ma->ma_dmat; 99 1.2 matt 100 1.2 matt /* Map I/O registers */ 101 1.3 matt if ((error = bus_space_map(sc->sc_ohci.iot, RA_USB_OHCI_BASE, 102 1.3 matt RA_USB_BLOCK_SIZE, 0, &sc->sc_ohci.ioh)) != 0) { 103 1.2 matt aprint_error_dev(self, "can't map OHCI registers, " 104 1.2 matt "error=%d\n", error); 105 1.2 matt return; 106 1.2 matt } 107 1.4 skrll 108 1.3 matt sc->sc_ohci.sc_size = RA_USB_BLOCK_SIZE; 109 1.2 matt 110 1.2 matt #ifdef RALINK_OHCI_DEBUG 111 1.2 matt printf("%s sc: %p ma: %p\n", devname, sc, ma); 112 1.2 matt printf("%s memt: %p dmat: %p\n", devname, ma->ma_memt, ma->ma_dmat); 113 1.2 matt 114 1.2 matt printf("%s: OHCI HcRevision=0x%x\n", devname, 115 1.2 matt OREAD4(&sc->sc_ohci, OHCI_REVISION)); 116 1.2 matt printf("%s: OHCI HcControl=0x%x\n", devname, 117 1.2 matt OREAD4(&sc->sc_ohci, OHCI_CONTROL)); 118 1.2 matt printf("%s: OHCI HcCommandStatus=0x%x\n", devname, 119 1.2 matt OREAD4(&sc->sc_ohci, OHCI_COMMAND_STATUS)); 120 1.2 matt printf("%s: OHCI HcInterruptStatus=0x%x\n", devname, 121 1.2 matt OREAD4(&sc->sc_ohci, OHCI_INTERRUPT_STATUS)); 122 1.2 matt #endif 123 1.2 matt 124 1.2 matt /* Disable OHCI interrupts. */ 125 1.2 matt OWRITE4(&sc->sc_ohci, OHCI_INTERRUPT_DISABLE, OHCI_ALL_INTRS); 126 1.2 matt 127 1.2 matt /* establish the MIPS level interrupt */ 128 1.2 matt sc->sc_ih = ra_intr_establish(RA_IRQ_USB, ohci_intr, sc, 0); 129 1.2 matt if (sc->sc_ih == NULL) { 130 1.2 matt aprint_error_dev(self, "unable to establish irq %d\n", 131 1.2 matt RA_IRQ_USB); 132 1.2 matt goto fail_0; 133 1.2 matt } 134 1.2 matt 135 1.2 matt /* Initialize OHCI */ 136 1.4 skrll error = ohci_init(&sc->sc_ohci); 137 1.4 skrll if (error) { 138 1.4 skrll aprint_error_dev(self, "init failed, error=%d\n", error); 139 1.2 matt goto fail_0; 140 1.2 matt } 141 1.2 matt 142 1.2 matt #if NEHCI > 0 143 1.2 matt ralink_usb_hc_add(&sc->sc_hc, self); 144 1.2 matt #endif 145 1.2 matt 146 1.2 matt if (!pmf_device_register1(self, ohci_suspend, ohci_resume, 147 1.2 matt ohci_shutdown)) 148 1.2 matt aprint_error_dev(self, "couldn't establish power handler\n"); 149 1.2 matt 150 1.2 matt /* Attach usb device. */ 151 1.2 matt sc->sc_ohci.sc_child = config_found(self, &sc->sc_ohci.sc_bus, 152 1.7 thorpej usbctlprint, CFARGS_NONE); 153 1.2 matt 154 1.2 matt return; 155 1.2 matt 156 1.2 matt fail_0: 157 1.2 matt bus_space_unmap(sc->sc_ohci.iot, sc->sc_ohci.ioh, sc->sc_ohci.sc_size); 158 1.2 matt sc->sc_ohci.sc_size = 0; 159 1.2 matt } 160 1.2 matt 161 1.2 matt static int 162 1.2 matt ralink_ohci_detach(device_t self, int flags) 163 1.2 matt { 164 1.2 matt struct ralink_ohci_softc *sc = device_private(self); 165 1.8 riastrad int error; 166 1.8 riastrad 167 1.8 riastrad /* 168 1.8 riastrad * Detach the USB child first. Disconnects all USB devices and 169 1.8 riastrad * prevents connecting new ones. 170 1.8 riastrad */ 171 1.8 riastrad error = config_detach_children(self, flags); 172 1.8 riastrad if (error) 173 1.8 riastrad return error; 174 1.8 riastrad 175 1.8 riastrad /* 176 1.8 riastrad * Stop listing this as a possible companion controller for 177 1.8 riastrad * ehci(4). 178 1.8 riastrad */ 179 1.8 riastrad #if NEHCI > 0 180 1.8 riastrad ralink_usb_hc_rem(&sc->sc_hc); 181 1.8 riastrad #endif 182 1.2 matt 183 1.8 riastrad /* 184 1.8 riastrad * Shut down the controller and block interrupts at the device 185 1.8 riastrad * level. Once we have shut down the controller, the shutdown 186 1.8 riastrad * handler no longer needed -- deregister it from PMF. 187 1.8 riastrad * (Harmless to call ohci_shutdown more than once, so no 188 1.8 riastrad * synchronization needed.) 189 1.8 riastrad */ 190 1.8 riastrad ohci_shutdown(self, 0); 191 1.2 matt pmf_device_deregister(self); 192 1.2 matt 193 1.8 riastrad /* 194 1.8 riastrad * Interrupts are blocked at the device level by ohci_shutdown. 195 1.8 riastrad * Disestablish the interrupt handler. This waits for it to 196 1.8 riastrad * complete on all CPUs. 197 1.8 riastrad */ 198 1.2 matt if (sc->sc_ih != NULL) { 199 1.2 matt ra_intr_disestablish(sc->sc_ih); 200 1.2 matt sc->sc_ih = NULL; 201 1.2 matt } 202 1.2 matt 203 1.8 riastrad /* 204 1.8 riastrad * Free the bus-independent ohci(4) state now that the 205 1.8 riastrad * interrupt handler has ceased to run on all CPUs. 206 1.8 riastrad */ 207 1.8 riastrad ohci_detach(&sc->sc_ohci); 208 1.8 riastrad 209 1.8 riastrad /* 210 1.8 riastrad * Unmap the registers now that we're all done with them. 211 1.8 riastrad */ 212 1.8 riastrad if (sc->sc_ohci.sc_size) { 213 1.2 matt bus_space_unmap(sc->sc_ohci.iot, sc->sc_ohci.ioh, 214 1.8 riastrad sc->sc_ohci.sc_size); 215 1.2 matt sc->sc_ohci.sc_size = 0; 216 1.2 matt } 217 1.2 matt 218 1.2 matt return 0; 219 1.2 matt } 220