ralink_reg.h revision 1.1.2.1
1 /* $NetBSD: ralink_reg.h,v 1.1.2.1 2011/07/01 05:45:45 matt Exp $ */ 2 /*- 3 * Copyright (c) 2011 CradlePoint Technology, Inc. 4 * All rights reserved. 5 * 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY CRADLEPOINT TECHNOLOGY, INC. AND CONTRIBUTORS 17 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 18 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 19 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS 20 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 21 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 22 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 23 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 24 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 25 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 26 * POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 /* 30 * This file contains the configuration parameters for the RT3052 board. 31 */ 32 33 #ifndef _RALINK_REG_H_ 34 #define _RALINK_REG_H_ 35 36 #include <mips/cpuregs.h> 37 38 #if defined(RT3050) 39 #define RA_CLOCK_RATE 320000000 40 #define RA_BUS_FREQ (RA_CLOCK_RATE / 3) 41 #define RA_UART_FREQ RA_BUS_FREQ 42 #elif defined(RT3052) 43 #define RA_CLOCK_RATE 384000000 44 #define RA_BUS_FREQ (RA_CLOCK_RATE / 3) 45 #define RA_UART_FREQ RA_BUS_FREQ 46 #elif defined(RT3883) 47 #if 0 48 #define RA_CLOCK_RATE 480000000 49 #else 50 #define RA_CLOCK_RATE 500000000 51 #endif 52 #define RA_BUS_FREQ 166000000 /* DDR speed */ 53 #define RA_UART_FREQ 40000000 54 #else 55 /* Ralink dev board */ 56 #define RA_CLOCK_RATE 384000000 57 #define RA_BUS_FREQ (RA_CLOCK_RATE / 3) 58 #define RA_UART_FREQ RA_BUS_FREQ 59 #endif 60 61 #define RA_BAUDRATE CONSPEED 62 #define RA_SERIAL_CLKDIV 16 63 64 #define RA_SRAM_BASE 0x00000000 65 #define RA_SRAM_END 0x0FFFFFFF 66 #define RA_SYSCTL_BASE 0x10000000 67 #define RA_TIMER_BASE 0x10000100 68 #define RA_INTCTL_BASE 0x10000200 69 #define RA_MEMCTL_BASE 0x10000300 70 #if defined(RT3052) || defined(RT3050) 71 #define RA_PCM_BASE 0x10000400 72 #endif 73 #define RA_UART_BASE 0x10000500 74 #define RA_PIO_BASE 0x10000600 75 #if defined(RT3052) || defined(RT3050) 76 #define RA_GDMA_BASE 0x10000700 77 #elif defined(RT3883) 78 #define RA_FLASHCTL_BASE 0x10000700 79 #endif 80 #define RA_NANDCTL_BASE 0x10000800 81 #define RA_I2C_BASE 0x10000900 82 #define RA_I2S_BASE 0x10000A00 83 #define RA_SPI_BASE 0x10000B00 84 #define RA_UART_LITE_BASE 0x10000C00 85 #if defined(RT3883) 86 #define RA_PCM_BASE 0x10002000 87 #define RA_GDMA_BASE 0x10002800 88 #define RA_CODEC1_BASE 0x10003000 89 #define RA_CODEC2_BASE 0x10003800 90 #endif 91 #define RA_FRAME_ENGINE_BASE 0x10100000 92 #define RA_ETH_SW_BASE 0x10110000 93 #define RA_ROM_BASE 0x10118000 94 #if defined(RT3883) 95 #define RA_USB_DEVICE_BASE 0x10120000 96 #define RA_PCI_BASE 0x10140000 97 #endif 98 #define RA_11N_MAC_BASE 0x10180000 99 #define RA_USB_OTG_BASE 0x101C0000 100 #if defined(RT3883) 101 #define RA_USB_HOST_BASE 0x101C0000 102 #endif 103 #if defined(RT3052) || defined(RT3050) 104 #define RA_FLASH_BASE 0x1F000000 105 #define RA_FLASH_END 0x1F7FFFFF 106 #elif defined(RT3883) 107 #define RA_FLASH_BASE 0x1C000000 108 #define RA_FLASH_END 0x1DFFFFFF 109 #endif 110 111 #define RA_IOREG_VADDR(base, offset) \ 112 (volatile uint32_t *)MIPS_PHYS_TO_KSEG1((base) + (offset)) 113 114 #define FLD_GET(val,pos,mask) (((val) >> (pos)) & (mask)) 115 #define FLD_SET(val,pos,mask) (((val) & (mask)) << (pos)) 116 117 /* 118 * System Control Registers 119 */ 120 #define RA_SYSCTL_ID0 0x00 121 #define RA_SYSCTL_ID1 0x04 122 #define RA_SYSCTL_CFG0 0x10 123 #define RA_SYSCTL_CFG1 0x14 124 #define RA_SYSCTL_CLKCFG0 0x2C 125 #define RA_SYSCTL_CLKCFG1 0x30 126 #define RA_SYSCTL_RST 0x34 127 #define RA_SYSCTL_RSTSTAT 0x38 128 #define RA_SYSCTL_GPIOMODE 0x60 129 130 #if defined(RT3883) 131 /* 3883 doesn't have memo regs, use teststat instead */ 132 #define RA_SYSCTL_MEMO0 0x18 133 #define RA_SYSCTL_MEMO1 0x1C 134 #else 135 #define RA_SYSCTL_MEMO0 0x68 136 #define RA_SYSCTL_MEMO1 0x6C 137 #endif 138 139 #define RST_SW (1 << 23) 140 #define RST_OTG (1 << 22) 141 #define RST_FE (1 << 21) 142 #define RST_WLAN (1 << 20) 143 #define RST_UARTL (1 << 19) 144 #define RST_SPI (1 << 18) 145 #define RST_I2S (1 << 17) 146 #define RST_I2C (1 << 16) 147 #define RST_NAND (1 << 15) 148 #define RST_DMA (1 << 14) 149 #define RST_PIO (1 << 13) 150 #define RST_UART (1 << 12) 151 #define RST_PCM (1 << 11) 152 #define RST_MC (1 << 10) 153 #define RST_INTC (1 << 9) 154 #define RST_TIMER (1 << 8) 155 #define RST_SYS (1 << 0) 156 #define GPIOMODE_RGMII (1 << 9) 157 #define GPIOMODE_SDRAM (1 << 8) 158 #define GPIOMODE_MDIO (1 << 7) 159 #define GPIOMODE_JTAG (1 << 6) 160 #define GPIOMODE_UARTL (1 << 5) 161 #define GPIOMODE_UARTF2 (1 << 4) 162 #define GPIOMODE_UARTF1 (1 << 3) 163 #define GPIOMODE_UARTF0 (1 << 2) 164 #define GPIOMODE_UARTF_0_2 \ 165 (GPIOMODE_UARTF0|GPIOMODE_UARTF1|GPIOMODE_UARTF2) 166 #define GPIOMODE_SPI (1 << 1) 167 #define GPIOMODE_I2C (1 << 0) 168 169 /* 170 * Timer Registers 171 */ 172 #define RA_TIMER_STAT 0x00 173 #define RA_TIMER_0_LOAD 0x10 174 #define RA_TIMER_0_VALUE 0x14 175 #define RA_TIMER_0_CNTRL 0x18 176 #define RA_TIMER_1_LOAD 0x20 177 #define RA_TIMER_1_VALUE 0x24 178 #define RA_TIMER_1_CNTRL 0x28 179 180 #define TIMER_1_RESET (1 << 5) 181 #define TIMER_0_RESET (1 << 4) 182 #define TIMER_1_INT_STATUS (1 << 1) 183 #define TIMER_0_INT_STATUS (1 << 0) 184 #define TIMER_TEST_EN (1 << 15) 185 #define TIMER_EN (1 << 7) 186 #define TIMER_MODE(x) (((x) & 0x3) << 4) 187 #define TIMER_MODE_FREE 0 188 #define TIMER_MODE_PERIODIC 1 189 #define TIMER_MODE_TIMEOUT 2 190 #define TIMER_MODE_WDOG 3 /* only valid for TIMER_1 */ 191 #define TIMER_PRESCALE(x) (((x) & 0xf) << 0) 192 #define TIMER_PRESCALE_DIV_1 0 193 #define TIMER_PRESCALE_DIV_4 1 194 #define TIMER_PRESCALE_DIV_8 2 195 #define TIMER_PRESCALE_DIV_16 3 196 #define TIMER_PRESCALE_DIV_32 4 197 #define TIMER_PRESCALE_DIV_64 5 198 #define TIMER_PRESCALE_DIV_128 6 199 #define TIMER_PRESCALE_DIV_256 7 200 #define TIMER_PRESCALE_DIV_512 8 201 #define TIMER_PRESCALE_DIV_1024 9 202 #define TIMER_PRESCALE_DIV_2048 10 203 #define TIMER_PRESCALE_DIV_4096 11 204 #define TIMER_PRESCALE_DIV_8192 12 205 #define TIMER_PRESCALE_DIV_16384 13 206 #define TIMER_PRESCALE_DIV_32768 14 207 #define TIMER_PRESCALE_DIV_65536 15 208 209 /* 210 * Interrupt Controller Registers 211 */ 212 #define RA_INTCTL_IRQ0STAT 0x00 213 #define RA_INTCTL_IRQ1STAT 0x04 214 #define RA_INTCTL_TYPE 0x20 215 #define RA_INTCTL_RAW 0x30 216 #define RA_INTCTL_ENABLE 0x34 217 #define RA_INTCTL_DISABLE 0x38 218 219 220 #define INT_GLOBAL (1 << 31) 221 #define INT_USB (1 << 18) 222 #define INT_ETHSW (1 << 17) 223 #define INT_UARTL (1 << 12) 224 #define INT_I2S (1 << 10) 225 #define INT_PERF (1 << 9) 226 #define INT_NAND (1 << 8) 227 #define INT_DMA (1 << 7) 228 #define INT_PIO (1 << 6) 229 #define INT_UARTF (1 << 5) 230 #define INT_PCM (1 << 4) 231 #define INT_ILLACC (1 << 3) 232 #define INT_WDOG (1 << 2) 233 #define INT_TIMER0 (1 << 1) 234 #define INT_SYSCTL (1 << 0) 235 236 /* 237 * Ralink Linear CPU Interrupt Mapping For Lists 238 */ 239 #define RA_IRQ_LOW 0 240 #define RA_IRQ_HIGH 1 241 #define RA_IRQ_PCI 2 242 #define RA_IRQ_FENGINE 3 243 #define RA_IRQ_WLAN 4 244 #define RA_IRQ_TIMER 5 245 #define RA_IRQ_SYSCTL 6 246 #define RA_IRQ_TIMER0 7 247 #define RA_IRQ_WDOG 8 248 #define RA_IRQ_ILLACC 9 249 #define RA_IRQ_PCM 10 250 #define RA_IRQ_UARTF 11 251 #define RA_IRQ_PIO 12 252 #define RA_IRQ_DMA 13 253 #define RA_IRQ_NAND 14 254 #define RA_IRQ_PERF 15 255 #define RA_IRQ_I2S 16 256 #define RA_IRQ_UARTL 17 257 #define RA_IRQ_ETHSW 18 258 #define RA_IRQ_USB 19 259 #define RA_IRQ_MAX 20 260 261 /* 262 * General Purpose I/O 263 */ 264 #define RA_PIO_00_23_INT 0x00 265 #define RA_PIO_00_23_EDGE_INT 0x04 266 #define RA_PIO_00_23_INT_RISE_EN 0x08 267 #define RA_PIO_00_23_INT_FALL_EN 0x0C 268 #define RA_PIO_00_23_DATA 0x20 269 #define RA_PIO_00_23_DIR 0x24 270 #define RA_PIO_00_23_POLARITY 0x28 271 #define RA_PIO_00_23_SET_BIT 0x2C 272 #define RA_PIO_00_23_CLR_BIT 0x30 273 #define RA_PIO_00_23_TGL_BIT 0x34 274 #define RA_PIO_24_39_INT 0x38 275 #define RA_PIO_24_39_EDGE_INT 0x3C 276 #define RA_PIO_24_39_INT_RISE_EN 0x40 277 #define RA_PIO_24_39_INT_FALL_EN 0x44 278 #define RA_PIO_24_39_DATA 0x48 279 #define RA_PIO_24_39_DIR 0x4C 280 #define RA_PIO_24_39_POLARITY 0x50 281 #define RA_PIO_24_39_SET_BIT 0x54 282 #define RA_PIO_24_39_CLR_BIT 0x58 283 #define RA_PIO_24_39_TGL_BIT 0x5C 284 #define RA_PIO_40_51_INT 0x60 285 #define RA_PIO_40_51_EDGE_INT 0x64 286 #define RA_PIO_40_51_INT_RISE_EN 0x68 287 #define RA_PIO_40_51_INT_FALL_EN 0x6C 288 #define RA_PIO_40_51_DATA 0x70 289 #define RA_PIO_40_51_DIR 0x74 290 #define RA_PIO_40_51_POLARITY 0x78 291 #define RA_PIO_40_51_SET_BIT 0x7C 292 #define RA_PIO_40_51_CLR_BIT 0x80 293 #define RA_PIO_40_51_TGL_BIT 0x84 294 #define RA_PIO_72_95_INT 0x88 295 #define RA_PIO_72_95_EDGE_INT 0x8c 296 #define RA_PIO_72_95_INT_RISE_EN 0x90 297 #define RA_PIO_72_95_INT_FALL_EN 0x94 298 #define RA_PIO_72_95_DATA 0x98 299 #define RA_PIO_72_95_DIR 0x9c 300 #define RA_PIO_72_95_POLARITY 0xa0 301 #define RA_PIO_72_95_SET_BIT 0xa4 302 #define RA_PIO_72_95_CLR_BIT 0xa8 303 #define RA_PIO_72_95_TGL_BIT 0xac 304 305 306 /* 307 * UART registers 308 */ 309 310 #define RA_UART_RBR 0x00 311 #define RA_UART_TBR 0x04 312 #define RA_UART_IER 0x08 313 #define RA_UART_IIR 0x0C 314 #define RA_UART_FCR 0x10 315 #define RA_UART_LCR 0x14 316 #define RA_UART_MCR 0x18 317 #define RA_UART_LSR 0x1C 318 #define RA_UART_MSR 0x20 319 #define RA_UART_DLL 0x28 320 321 322 #define UART_IER_ELSI (1 << 2) 323 /* Receiver Line Status Interrupt Enable */ 324 #define UART_IER_ETBEI (1 << 1) 325 /* Transmit Buffer Empty Interrupt Enable */ 326 #define UART_IER_ERBFI (1 << 0) 327 /* Data Ready or Character Time-Out Interrupt Enable */ 328 329 #define UART_IIR_FIFOES1 (1 << 7) /* FIFO Mode Enable Status */ 330 #define UART_IIR_FIFOES0 (1 << 6) /* FIFO Mode Enable Status */ 331 #define UART_IIR_IID3 (1 << 3) /* Interrupt Source Encoded */ 332 #define UART_IIR_IID2 (1 << 2) /* Interrupt Source Encoded */ 333 #define UART_IIR_IID1 (1 << 1) /* Interrupt Source Encoded */ 334 #define UART_IIR_IP (1 << 0) /* Interrupt Pending (active low) */ 335 336 #define UART_FCR_RXTRIG1 (1 << 7) /* Receiver Interrupt Trigger Level */ 337 #define UART_FCR_RXTRIG0 (1 << 6) /* Receiver Interrupt Trigger Level */ 338 #define UART_FCR_TXTRIG1 (1 << 5) /* Transmitter Interrupt Trigger Level */ 339 #define UART_FCR_TXTRIG0 (1 << 4) /* Transmitter Interrupt Trigger Level */ 340 #define UART_FCR_DMAMODE (1 << 3) /* Enable DMA transfers */ 341 #define UART_FCR_TXRST (1 << 2) /* Reset Transmitter FIFO */ 342 #define UART_FCR_RXRST (1 << 1) /* Reset Receiver FIFO */ 343 #define UART_FCR_FIFOE (1 << 0) /* Transmit and Receive FIFO Enable */ 344 345 #define UART_LCR_DLAB (1 << 7) /* Divisor Latch Access Bit */ 346 #define UART_LCR_SB (1 << 6) /* Set Break */ 347 #define UART_LCR_STKYP (1 << 5) /* Sticky Parity */ 348 #define UART_LCR_EPS (1 << 4) /* Even Parity Select */ 349 #define UART_LCR_PEN (1 << 3) /* Parity Enable */ 350 #define UART_LCR_STB (1 << 2) /* Stop Bit */ 351 #define UART_LCR_WLS1 (1 << 1) /* Word Length Select */ 352 #define UART_LCR_WLS0 (1 << 0) /* Word Length Select */ 353 354 #define UART_MCR_LOOP (1 << 4) /* Loop-back Mode Enable */ 355 356 #define UART_MSR_DCD (1 << 7) /* Data Carrier Detect */ 357 #define UART_MSR_RI (1 << 6) /* Ring Indicator */ 358 #define UART_MSR_DSR (1 << 5) /* Data Set Ready */ 359 #define UART_MSR_CTS (1 << 4) /* Clear To Send */ 360 #define UART_MSR_DDCD (1 << 3) /* Delta Data Carrier Detect */ 361 #define UART_MSR_TERI (1 << 2) /* Trailing Edge Ring Indicator */ 362 #define UART_MSR_DDSR (1 << 1) /* Delta Data Set Ready */ 363 #define UART_MSR_DCTS (1 << 0) /* Delta Clear To Send */ 364 365 #define UART_LSR_FIFOE (1 << 7) /* FIFO Error Status */ 366 #define UART_LSR_TEMT (1 << 6) /* Transmitter Empty */ 367 #define UART_LSR_TDRQ (1 << 5) /* Transmit Data Request */ 368 #define UART_LSR_BI (1 << 4) /* Break Interrupt */ 369 #define UART_LSR_FE (1 << 3) /* Framing Error */ 370 #define UART_LSR_PE (1 << 2) /* Parity Error */ 371 #define UART_LSR_OE (1 << 1) /* Overrun Error */ 372 #define UART_LSR_DR (1 << 0) /* Data Ready */ 373 374 /* 375 * I2C registers 376 */ 377 #define RA_I2C_CONFIG 0x00 378 #define RA_I2C_CLKDIV 0x04 379 #define RA_I2C_DEVADDR 0x08 380 #define RA_I2C_ADDR 0x0C 381 #define RA_I2C_DATAOUT 0x10 382 #define RA_I2C_DATAIN 0x14 383 #define RA_I2C_STATUS 0x18 384 #define RA_I2C_STARTXFR 0x1C 385 #define RA_I2C_BYTECNT 0x20 386 387 #define I2C_CONFIG_ADDRLEN(x) (((x) & 0x7) << 5) 388 #define I2C_CONFIG_ADDRLEN_7 6 389 #define I2C_CONFIG_ADDRLEN_8 7 390 #define I2C_CONFIG_DEVADLEN(x) (((x) & 0x7) << 2) 391 #define I2C_CONFIG_DEVADLEN_6 5 392 #define I2C_CONFIG_DEVADLEN_7 6 393 #define I2C_CONFIG_ADDRDIS (1 << 1) 394 #define I2C_CONFIG_DEVDIS (1 << 0) 395 #define I2C_STATUS_STARTERR (1 << 4) 396 #define I2C_STATUS_ACKERR (1 << 3) 397 #define I2C_STATUS_DATARDY (1 << 2) 398 #define I2C_STATUS_SDOEMPTY (1 << 1) 399 #define I2C_STATUS_BUSY (1 << 0) 400 401 /* 402 * SPI registers 403 */ 404 #define RA_SPI_STATUS 0x00 405 #define RA_SPI_CONFIG 0x10 406 #define RA_SPI_CONTROL 0x14 407 #define RA_SPI_DATA 0x20 408 409 #define SPI_STATUS_BUSY (1 << 0) 410 #define SPI_CONFIG_MSBFIRST (1 << 8) 411 #define SPI_CONFIG_CLK (1 << 6) 412 #define SPI_CONFIG_RXCLKEDGE_FALL (1 << 5) 413 #define SPI_CONFIG_TXCLKEDGE_FALL (1 << 4) 414 #define SPI_CONFIG_TRISTATE (1 << 3) 415 #define SPI_CONFIG_RATE(x) ((x) & 0x7) 416 #define SPI_CONFIG_RATE_DIV_2 0 417 #define SPI_CONFIG_RATE_DIV_4 1 418 #define SPI_CONFIG_RATE_DIV_8 2 419 #define SPI_CONFIG_RATE_DIV_16 3 420 #define SPI_CONFIG_RATE_DIV_32 4 421 #define SPI_CONFIG_RATE_DIV_64 5 422 #define SPI_CONFIG_RATE_DIV_128 6 423 #define SPI_CONFIG_RATE_DIV_NONE 7 424 #define SPI_CONTROL_TRISTATE (1 << 3) 425 #define SPI_CONTROL_STARTWR (1 << 2) 426 #define SPI_CONTROL_STARTRD (1 << 1) 427 #define SPI_CONTROL_ENABLE_LOW (0 << 0) 428 #define SPI_CONTROL_ENABLE_HIGH (1 << 0) 429 #define SPI_DATA_VAL(x) ((x) & 0xff) 430 431 /* 432 * Frame Engine registers 433 */ 434 #define RA_FE_MDIO_ACCESS 0x000 435 #define RA_FE_MDIO_CFG1 0x004 436 #define RA_FE_GLOBAL_CFG 0x008 437 #define RA_FE_GLOBAL_RESET 0x00C 438 #define RA_FE_INT_STATUS 0x010 439 #define RA_FE_INT_ENABLE 0x014 440 #define RA_FE_MDIO_CFG2 0x018 441 #define RA_FE_TIME_STAMP 0x01C 442 #define RA_FE_GDMA1_FWD_CFG 0x020 443 #define RA_FE_GDMA1_SCHED_CFG 0x024 444 #define RA_FE_GDMA1_SHAPE_CFG 0x028 445 #define RA_FE_GDMA1_MAC_LSB 0x02C 446 #define RA_FE_GDMA1_MAC_MSB 0x030 447 #define RA_FE_PSE_FQ_CFG 0x040 448 #define RA_FE_CDMA_FC_CFG 0x044 449 #define RA_FE_GDMA1_FC_CFG 0x048 450 #define RA_FE_GDMA2_FC_CFG 0x04C 451 #define RA_FE_CDMA_OQ_STA 0x050 452 #define RA_FE_GDMA1_OQ_STA 0x054 453 #define RA_FE_GDMA2_OQ_STA 0x058 454 #define RA_FE_PSE_IQ_STA 0x05C 455 #define RA_FE_GDMA2_FWD_CFG 0x060 456 #define RA_FE_GDMA2_SCHED_CFG 0x064 457 #define RA_FE_GDMA2_SHAPE_CFG 0x068 458 #define RA_FE_GDMA2_MAC_LSB 0x06C 459 #define RA_FE_GDMA2_MAC_MSB 0x070 460 #define RA_FE_CDMA_CSG_CFG 0x080 461 #define RA_FE_CDMA_SCHED_CFG 0x084 462 #define RA_FE_PPPOE_SID_0001 0x088 463 #define RA_FE_PPPOE_SID_0203 0x08C 464 #define RA_FE_PPPOE_SID_0405 0x090 465 #define RA_FE_PPPOE_SID_0607 0x094 466 #define RA_FE_PPPOE_SID_0809 0x098 467 #define RA_FE_PPPOE_SID_1011 0x09C 468 #define RA_FE_PPPOE_SID_1213 0x0A0 469 #define RA_FE_PPPOE_SID_1415 0x0A4 470 #define RA_FE_VLAN_ID_0001 0x0A8 471 #define RA_FE_VLAN_ID_0203 0x0AC 472 #define RA_FE_VLAN_ID_0405 0x0B0 473 #define RA_FE_VLAN_ID_0607 0x0B4 474 #define RA_FE_VLAN_ID_0809 0x0B8 475 #define RA_FE_VLAN_ID_1011 0x0BC 476 #define RA_FE_VLAN_ID_1213 0x0C0 477 #define RA_FE_VLAN_ID_1415 0x0C4 478 #define RA_FE_PDMA_GLOBAL_CFG 0x100 479 #define RA_FE_PDMA_RESET_IDX 0x104 480 #define RA_FE_PDMA_SCHED_CFG 0x108 481 #define RA_FE_PDMA_DLY_INT_CFG 0x10C 482 #define RA_FE_PDMA_TX0_PTR 0x110 483 #define RA_FE_PDMA_TX0_COUNT 0x114 484 #define RA_FE_PDMA_TX0_CPU_IDX 0x118 485 #define RA_FE_PDMA_TX0_DMA_IDX 0x11C 486 #define RA_FE_PDMA_TX1_PTR 0x120 487 #define RA_FE_PDMA_TX1_COUNT 0x124 488 #define RA_FE_PDMA_TX1_CPU_IDX 0x128 489 #define RA_FE_PDMA_TX1_DMA_IDX 0x12C 490 #define RA_FE_PDMA_RX0_PTR 0x130 491 #define RA_FE_PDMA_RX0_COUNT 0x134 492 #define RA_FE_PDMA_RX0_CPU_IDX 0x138 493 #define RA_FE_PDMA_RX0_DMA_IDX 0x13C 494 #define RA_FE_PDMA_TX2_PTR 0x140 495 #define RA_FE_PDMA_TX2_COUNT 0x144 496 #define RA_FE_PDMA_TX2_CPU_IDX 0x148 497 #define RA_FE_PDMA_TX2_DMA_IDX 0x14C 498 #define RA_FE_PDMA_TX3_PTR 0x150 499 #define RA_FE_PDMA_TX3_COUNT 0x154 500 #define RA_FE_PDMA_TX3_CPU_IDX 0x158 501 #define RA_FE_PDMA_TX3_DMA_IDX 0x15C 502 #define RA_FE_PDMA_FC_CFG 0x1F0 503 /* TODO: FE_COUNTERS */ 504 505 #define MDIO_ACCESS_TRG (1 << 31) 506 #define MDIO_ACCESS_WR (1 << 30) 507 #define MDIO_ACCESS_PHY_ADDR(x) (((x) & 0x1f) << 24) 508 #define MDIO_ACCESS_REG(x) (((x) & 0x1f) << 16) 509 #define MDIO_ACCESS_DATA(x) ((x) & 0xffff) 510 #define MDIO_CFG_AUTO_POLL (1 << 29) 511 #define MDIO_CFG_PHY_ADDR(x) (((x) & 0x1f) << 24) 512 #define MDIO_CFG_BP_EN (1 << 16) 513 #define MDIO_CFG_FORCE_CFG (1 << 15) 514 #define MDIO_CFG_SPEED(x) (((x) & 0x3) << 13) 515 #define MDIO_CFG_SPEED_1000M 2 516 #define MDIO_CFG_SPEED_100M 1 517 #define MDIO_CFG_SPEED_10M 0 518 #define MDIO_CFG_FULL_DUPLEX (1 << 12) 519 #define MDIO_CFG_FC_TX (1 << 11) 520 #define MDIO_CFG_FC_RX (1 << 10) 521 #define MDIO_CFG_LINK_DOWN (1 << 9) 522 #define MDIO_CFG_AUTO_DONE (1 << 8) 523 #define MDIO_CFG_MDC_CLKDIV(x) (((x) & 0x3) << 6) 524 #define MDIO_CFG_MDC_512KHZ 3 525 #define MDIO_CFG_MDC_1MHZ 2 526 #define MDIO_CFG_MDC_2MHZ 1 527 #define MDIO_CFG_MDC_4MHZ 0 528 #define MDIO_CFG_TURBO_50MHZ (1 << 5) 529 #define MDIO_CFG_TURBO_EN (1 << 4) 530 #define MDIO_CFG_RX_CLK_SKEW (((x) & 0x3) << 2) 531 #define MDIO_CFG_RX_SKEW_INV 3 532 #define MDIO_CFG_RX_SKEW_400PS 2 533 #define MDIO_CFG_RX_SKEW_200PS 1 534 #define MDIO_CFG_RX_SKEW_ZERO 0 535 #define MDIO_CFG_TX_CLK_MODE(x) (((x) & 0x1) << 0) 536 #define MDIO_CFG_TX_CLK_MODE_3COM 1 537 #define MDIO_CFG_TX_CLK_MODE_HP 0 538 #define FE_GLOBAL_CFG_EXT_VLAN(x) (((x) & 0xffff) << 16) 539 #define FE_GLOBAL_CFG_US_CLK(x) (((x) & 0xff) << 8) 540 #define FE_GLOBAL_CFG_L2_SPACE(x) (((x) & 0xf) << 4) 541 #define FE_GLOBAL_RESET_PSE (1 << 0) 542 #define FE_INT_PPE_COUNT_HIGH (1 << 31) 543 #define FE_INT_DMA_COUNT_HIGH (1 << 29) 544 #define FE_INT_PSE_P2_FC_ASSERT (1 << 26) 545 #define FE_INT_PSE_FC_DROP (1 << 24) 546 #define FE_INT_GDMA_DROP_OTHER (1 << 23) 547 #define FE_INT_PSE_P1_FC_ASSERT (1 << 22) 548 #define FE_INT_PSE_P0_FC_ASSERT (1 << 21) 549 #define FE_INT_PSE_FQ_EMPTY (1 << 20) 550 #define FE_INT_TX_COHERENT (1 << 17) 551 #define FE_INT_RX_COHERENT (1 << 16) 552 #define FE_INT_TX3 (1 << 11) 553 #define FE_INT_TX2 (1 << 10) 554 #define FE_INT_TX1 (1 << 9) 555 #define FE_INT_TX0 (1 << 8) 556 #define FE_INT_RX (1 << 2) 557 #define FE_INT_TX_DELAY (1 << 1) 558 #define FE_INT_RX_DELAY (1 << 0) 559 #define FE_GDMA_FWD_CFG_JUMBO_LEN(x) (((x) & 0xf) << 28) 560 #define FE_GDMA_FWD_CFG_DROP_256B (1 << 23) 561 #define FE_GDMA_FWD_CFG_IP4_CRC_EN (1 << 22) 562 #define FE_GDMA_FWD_CFG_TCP_CRC_EN (1 << 21) 563 #define FE_GDMA_FWD_CFG_UDP_CRC_EN (1 << 20) 564 #define FE_GDMA_FWD_CFG_JUMBO_EN (1 << 19) 565 #define FE_GDMA_FWD_CFG_DIS_TX_PAD (1 << 18) 566 #define FE_GDMA_FWD_CFG_DIS_TX_CRC (1 << 17) 567 #define FE_GDMA_FWD_CFG_STRIP_RX_CRC (1 << 16) 568 #define FE_GDMA_FWD_CFG_UNICA_PORT(x) (((x) & 0x3) << 12) 569 #define FE_GDMA_FWD_CFG_BROAD_PORT(x) (((x) & 0x3) << 8) 570 #define FE_GDMA_FWD_CFG_MULTI_PORT(x) (((x) & 0x3) << 6) 571 #define FE_GDMA_FWD_CFG_OTHER_PORT(x) (((x) & 0x3) << 0) 572 #define FE_GDMA_FWD_CFG_PORT_DROP 7 573 #define FE_GDMA_FWD_CFG_PORT_PPE 6 574 #define FE_GDMA_FWD_CFG_PORT_GDMA2 2 575 #define FE_GDMA_FWD_CFG_PORT_GDMA1 1 576 #define FE_GDMA_FWD_CFG_PORT_CPU 0 577 #define FE_PSE_FQ_MAX_COUNT(x) (((x) & 0xff) << 24) 578 #define FE_PSE_FQ_FC_RELEASE(x) (((x) & 0xff) << 16) 579 #define FE_PSE_FQ_FC_ASSERT(x) (((x) & 0xff) << 8) 580 #define FE_PSE_FQ_FC_DROP(x) (((x) & 0xff) << 0) 581 #define FE_CDMA_CSG_CFG_VLAN_TAG(x) (((x) & 0xffff) << 16) 582 #define FE_CDMA_CSG_CFG_IP4_CRC_EN (1 << 2) 583 #define FE_CDMA_CSG_CFG_UDP_CRC_EN (1 << 1) 584 #define FE_CDMA_CSG_CFG_TCP_CRC_EN (1 << 0) 585 #define FE_PDMA_GLOBAL_CFG_HDR_SEG_LEN (1 << 16) 586 #define FE_PDMA_GLOBAL_CFG_TX_WB_DDONE (1 << 6) 587 #define FE_PDMA_GLOBAL_CFG_BURST_SZ(x) (((x) & 0x3) << 4) 588 #define FE_PDMA_GLOBAL_CFG_BURST_SZ_4 (0 << 4) 589 #define FE_PDMA_GLOBAL_CFG_BURST_SZ_8 (1 << 4) 590 #define FE_PDMA_GLOBAL_CFG_BURST_SZ_16 (2 << 4) 591 #define FE_PDMA_GLOBAL_CFG_RX_DMA_BUSY (1 << 3) 592 #define FE_PDMA_GLOBAL_CFG_RX_DMA_EN (1 << 2) 593 #define FE_PDMA_GLOBAL_CFG_TX_DMA_BUSY (1 << 1) 594 #define FE_PDMA_GLOBAL_CFG_TX_DMA_EN (1 << 0) 595 #define PDMA_RST_RX0 (1 << 16) 596 #define PDMA_RST_TX3 (1 << 3) 597 #define PDMA_RST_TX2 (1 << 2) 598 #define PDMA_RST_TX1 (1 << 1) 599 #define PDMA_RST_TX0 (1 << 0) 600 601 /* 602 * 10/100 Switch registers 603 */ 604 605 #define RA_ETH_SW_ISR 0x00 606 #define RA_ETH_SW_IMR 0x04 607 #define RA_ETH_SW_FCT0 0x08 608 #define RA_ETH_SW_FCT1 0x0C 609 #define RA_ETH_SW_PFC0 0x10 610 #define RA_ETH_SW_PFC1 0x14 611 #define RA_ETH_SW_PFC2 0x18 612 #define RA_ETH_SW_QCS0 0x1C 613 #define RA_ETH_SW_QCS1 0x20 614 #define RA_ETH_SW_ATS 0x24 615 #define RA_ETH_SW_ATS0 0x28 616 #define RA_ETH_SW_ATS1 0x2C 617 #define RA_ETH_SW_ATS2 0x30 618 #define RA_ETH_SW_WMAD0 0x34 619 #define RA_ETH_SW_WMAD1 0x38 620 #define RA_ETH_SW_WMAD2 0x3C 621 #define RA_ETH_SW_PVIDC0 0x40 622 #define RA_ETH_SW_PVIDC1 0x44 623 #define RA_ETH_SW_PVIDC2 0x48 624 #define RA_ETH_SW_PVIDC3 0x4C 625 #define RA_ETH_SW_VLANI0 0x50 626 #define RA_ETH_SW_VLANI1 0x54 627 #define RA_ETH_SW_VLANI2 0x58 628 #define RA_ETH_SW_VLANI3 0x5C 629 #define RA_ETH_SW_VLANI4 0x60 630 #define RA_ETH_SW_VLANI5 0x64 631 #define RA_ETH_SW_VLANI6 0x68 632 #define RA_ETH_SW_VLANI7 0x6C 633 #define RA_ETH_SW_VMSC0 0x70 634 #define RA_ETH_SW_VMSC1 0x74 635 #define RA_ETH_SW_VMSC2 0x78 636 #define RA_ETH_SW_VMSC3 0x7C 637 #define RA_ETH_SW_POA 0x80 638 #define RA_ETH_SW_FPA 0x84 639 #define RA_ETH_SW_PTS 0x88 640 #define RA_ETH_SW_SOCPC 0x8C 641 #define RA_ETH_SW_POC0 0x90 642 #define RA_ETH_SW_POC1 0x94 643 #define RA_ETH_SW_POC2 0x98 644 #define RA_ETH_SW_SWGC 0x9C 645 #define RA_ETH_SW_RST 0xA0 646 #define RA_ETH_SW_LEDP0 0xA4 647 #define RA_ETH_SW_LEDP1 0xA8 648 #define RA_ETH_SW_LEDP2 0xAC 649 #define RA_ETH_SW_LEDP3 0xB0 650 #define RA_ETH_SW_LEDP4 0xB4 651 #define RA_ETH_SW_WDOG 0xB8 652 #define RA_ETH_SW_DBG 0xBC 653 #define RA_ETH_SW_PCTL0 0xC0 654 #define RA_ETH_SW_PCTL1 0xC4 655 #define RA_ETH_SW_FPORT 0xC8 656 #define RA_ETH_SW_FTC2 0xCC 657 #define RA_ETH_SW_QSS0 0xD0 658 #define RA_ETH_SW_QSS1 0xD4 659 #define RA_ETH_SW_DBGC 0xD8 660 #define RA_ETH_SW_MTI1 0xDC 661 #define RA_ETH_SW_PPC 0xE0 662 #define RA_ETH_SW_SGC2 0xE4 663 #define RA_ETH_SW_PCNT0 0xE8 664 #define RA_ETH_SW_PCNT1 0xEC 665 #define RA_ETH_SW_PCNT2 0xF0 666 #define RA_ETH_SW_PCNT3 0xF4 667 #define RA_ETH_SW_PCNT4 0xF8 668 #define RA_ETH_SW_PCNT5 0xFC 669 670 #define ISR_WDOG1_EXPIRED (1 << 29) 671 #define ISR_WDOG0_EXPIRED (1 << 28) 672 #define ISR_HAS_INTRUDER (1 << 27) 673 #define ISR_PORT_STS_CHNG (1 << 26) 674 #define ISR_BRDCAST_STORM (1 << 25) 675 #define ISR_MUST_DROP_LAN (1 << 24) 676 #define ISR_GLOB_QUE_FULL (1 << 23) 677 #define ISR_LAN_QUE6_FULL (1 << 20) 678 #define ISR_LAN_QUE5_FULL (1 << 19) 679 #define ISR_LAN_QUE4_FULL (1 << 18) 680 #define ISR_LAN_QUE3_FULL (1 << 17) 681 #define ISR_LAN_QUE2_FULL (1 << 16) 682 #define ISR_LAN_QUE1_FULL (1 << 15) 683 #define ISR_LAN_QUE0_FULL (1 << 14) 684 #define FTC0_REL_THR 24 685 #define FTC0_SET_THR 16 686 #define FTC0_DROP_REL_THR 8 687 #define FTC0_DROP_SET_THR 0 688 #define FTC1_PER_PORT_THR 0 689 #define PCTL0_WR_VAL(x) (((x) & 0xffff) << 16) 690 #define PCTL0_RD_CMD (1 << 14) 691 #define PCTL0_WR_CMD (1 << 13) 692 #define PCTL0_REG(x) (((x) & 0x1f) << 8) 693 #define PCTL0_ADDR(x) (((x) & 0x1f) << 0) 694 #define PCTL1_RD_VAL(x) (((x) >> 16) & 0xffff) 695 #define PCTL1_RD_DONE (1 << 1) /* read clear */ 696 #define PCTL1_WR_DONE (1 << 0) /* read clear */ 697 #define SGC2_WL_FC_EN (1 << 30) 698 #define SGC2_PORT5_IS_LAN (1 << 29) 699 #define SGC2_PORT4_IS_LAN (1 << 28) 700 #define SGC2_PORT3_IS_LAN (1 << 27) 701 #define SGC2_PORT2_IS_LAN (1 << 26) 702 #define SGC2_PORT1_IS_LAN (1 << 25) 703 #define SGC2_PORT0_IS_LAN (1 << 24) 704 #define SGC2_TX_CPU_TPID(x) ((x) << 16) 705 #define SGC2_ARBITER_LAN_EN (1 << 11) 706 #define SGC2_CPU_TPID_EN (1 << 10) 707 #define SGC2_DBL_TAG_EN5 (1 << 5) 708 #define SGC2_DBL_TAG_EN4 (1 << 4) 709 #define SGC2_DBL_TAG_EN3 (1 << 3) 710 #define SGC2_DBL_TAG_EN2 (1 << 2) 711 #define SGC2_DBL_TAG_EN1 (1 << 1) 712 #define SGC2_DBL_TAG_EN0 (1 << 0) 713 714 715 #define FTC_THR_MSK 0xff 716 717 #define PFC0_MTCC_LIMIT 24 718 #define PFC0_TURN_OFF_CF 16 719 #define PFC0_TURN_OFF_CF_MSK 0xff 720 #define PFC0_VO_NUM 12 721 #define PFC0_CL_NUM 8 722 #define PFC0_BE_NUM 4 723 #define PFC0_BK_NUM 0 724 #define PFC0_NUM_MSK 0xf 725 726 #define PFC1_P6_Q1_EN (1 << 31) 727 #define PFC1_P6_TOS_EN (1 << 30) 728 #define PFC1_P5_TOS_EN (1 << 29) 729 #define PFC1_P4_TOS_EN (1 << 28) 730 #define PFC1_P3_TOS_EN (1 << 27) 731 732 #define PFC1_P1_TOS_EN (1 << 25) 733 #define PFC1_P0_TOS_EN (1 << 24) 734 #define PFC1_PORT_PRI6 12 735 #define PFC1_PORT_PRI5 10 736 #define PFC1_PORT_PRI4 8 737 #define PFC1_PORT_PRI3 6 738 #define PFC1_PORT_PRI2 4 739 #define PFC1_PORT_PRI1 2 740 #define PFC1_PORT_PRI0 0 741 #define PFC1_PORT_MSK 0x3 742 743 #define PFC2_PRI_THR_VO 24 744 #define PFC2_PRI_THR_CL 16 745 #define PFC2_PRI_THR_BE 8 746 #define PFC2_PRI_THR_BK 0 747 #define PFC2_PRI_THR_MSK 0xff 748 749 #define GQC0_EMPTY_BLOCKS 0 750 #define GQC0_EMPTY_BLOCKS_MSK 0xff 751 752 /* 753 * USB OTG Registers 754 */ 755 #define RA_USB_OTG_OTG_CNTRL 0x000 756 #define RA_USB_OTG_OTG_INT 0x004 757 #define RA_USB_OTG_AHB_CFG 0x008 758 #define RA_USB_OTG_CFG 0x00C 759 #define RA_USB_OTG_RESET 0x010 760 #define RA_USB_OTG_INT 0x014 761 #define RA_USB_OTG_INT_MASK 0x018 762 #define RA_USB_OTG_RX_STAT 0x01C 763 #define RA_USB_OTG_RX_POP_STAT 0x020 764 #define RA_USB_OTG_RX_FIFO_SZ 0x024 765 #define RA_USB_OTG_TX_FIFO_SZ 0x028 766 #define RA_USB_OTG_TX_FIFO_STAT 0x02C 767 #define RA_USB_OTG_I2C_ACCESS 0x030 768 #define RA_USB_OTG_PHY_CTL 0x034 769 #define RA_USB_OTG_GPIO 0x038 770 #define RA_USB_OTG_GUID 0x03C 771 #define RA_USB_OTG_SNPSID 0x040 772 #define RA_USB_OTG_HWCFG1 0x044 773 #define RA_USB_OTG_HWCFG2 0x048 774 #define RA_USB_OTG_HWCFG3 0x04C 775 #define RA_USB_OTG_HWCFG4 0x050 776 #define RA_USB_OTG_HC_TX_FIFO_SZ 0x100 777 #define RA_USB_OTG_DV_TX_FIFO_SZ 0x104 778 #define RA_USB_OTG_HC_CFG 0x400 779 #define RA_USB_OTG_HC_FRM_INTRVL 0x404 780 #define RA_USB_OTG_HC_FRM_NUM 0x408 781 #define RA_USB_OTG_HC_TX_STAT 0x410 782 #define RA_USB_OTG_HC_INT 0x414 783 #define RA_USB_OTG_HC_INT_MASK 0x418 784 #define RA_USB_OTG_HC_PORT 0x440 785 #define RA_USB_OTG_HC_CH_CFG 0x500 786 #define RA_USB_OTG_HC_CH_SPLT 0x504 787 #define RA_USB_OTG_HC_CH_INT 0x508 788 #define RA_USB_OTG_HC_CH_INT_MASK 0x50C 789 #define RA_USB_OTG_HC_CH_XFER 0x510 790 #define RA_USB_OTG_HC_CH_DMA_ADDR 0x514 791 #define RA_USB_OTG_DV_CFG 0x800 792 #define RA_USB_OTG_DV_CTL 0x804 793 #define RA_USB_OTG_DV_STAT 0x808 794 #define RA_USB_OTG_DV_IN_INT_MASK 0x810 795 #define RA_USB_OTG_DV_OUT_INT_MASK 0x814 796 #define RA_USB_OTG_DV_ALL_INT 0x818 797 #define RA_USB_OTG_DV_EP_INT_MASK 0x81c 798 #define RA_USB_OTG_DV_IN_SEQ_RQ1 0x820 799 #define RA_USB_OTG_DV_IN_SEQ_RQ2 0x824 800 #define RA_USB_OTG_DV_IN_SEQ_RQ3 0x830 801 #define RA_USB_OTG_DV_IN_SEQ_RQ4 0x834 802 #define RA_USB_OTG_DV_VBUS_DISCH 0x828 803 #define RA_USB_OTG_DV_VBUS_PULSE 0x82c 804 #define RA_USB_OTG_DV_THRESH_CTL 0x830 805 #define RA_USB_OTG_DV_IN_FIFO_INT 0x834 806 #define RA_USB_OTG_DV_IN0_CTL 0x900 807 808 #define OTG_OTG_CNTRL_B_SESS_VALID (1 << 19) 809 #define OTG_OTG_CNTRL_A_SESS_VALID (1 << 18) 810 #define OTG_OTG_CNTRL_DEBOUNCE_SHORT (1 << 17) 811 #define OTG_OTG_CNTRL_CONNID_STATUS (1 << 16) 812 #define OTG_OTG_CNTRL_DV_HNP_EN (1 << 11) 813 #define OTG_OTG_CNTRL_HC_SET_HNP_EN (1 << 10) 814 #define OTG_OTG_CNTRL_HNP_REQ (1 << 9) 815 #define OTG_OTG_CNTRL_HNP_SUCCESS (1 << 8) 816 #define OTG_OTG_CNTRL_SESS_REQ (1 << 1) 817 #define OTG_OTG_CNTRL_SESS_REQ_SUCCESS (1 << 0) 818 #define OTG_OTG_INT_DEBOUNCE_DONE (1 << 19) 819 #define OTG_OTG_INT_ADEV_TIMEOUT (1 << 18) 820 #define OTG_OTG_INT_HOST_NEG_DETECT (1 << 17) 821 #define OTG_OTG_INT_HOST_NEG_STATUS (1 << 9) 822 #define OTG_OTG_INT_SESSION_REQ_STATUS (1 << 8) 823 #define OTG_OTG_INT_SESSION_END_STATUS (1 << 2) 824 #define OTG_AHB_CFG_TX_PFIFO_EMPTY_INT_EN (1 << 8) 825 #define OTG_AHB_CFG_TX_NPFIFO_EMPTY_INT_EN (1 << 7) 826 #define OTG_AHB_CFG_DMA_EN (1 << 5) 827 #define OTG_AHB_CFG_BURST(x) (((x) & 0xf) << 1) 828 #define OTG_AHB_CFG_BURST_SINGLE 0 829 #define OTG_AHB_CFG_BURST_INCR 1 830 #define OTG_AHB_CFG_BURST_INCR4 3 831 #define OTG_AHB_CFG_BURST_INCR8 5 832 #define OTG_AHB_CFG_BURST_INCR16 7 833 #define OTG_AHB_CFG_GLOBAL_INT_EN (1 << 0) 834 #define OTG_CFG_CORRUPT_TX (1 << 31) 835 #define OTG_CFG_FORCE_DEVICE (1 << 30) 836 #define OTG_CFG_FORCE_HOST (1 << 29) 837 #define OTG_CFG_ULPI_EXT_VBUS_IND_SEL (1 << 22) 838 #define OTG_CFG_ULPI_EXT_VBUS_IND (1 << 21) 839 #define OTG_CFG_ULPI_EXT_VBUS_DRV (1 << 20) 840 #define OTG_CFG_ULPI_CLOCK_SUSPEND (1 << 19) 841 #define OTG_CFG_ULPI_AUTO_RESUME (1 << 18) 842 #define OTG_CFG_ULPI_FS_LS_SEL (1 << 17) 843 #define OTG_CFG_UTMI_I2C_SEL (1 << 16) 844 #define OTG_CFG_TURNAROUND_TIME(x) (((x) & 0xf) << 10) 845 #define OTG_CFG_HNP_CAP (1 << 9) 846 #define OTG_CFG_SRP_CAP (1 << 8) 847 #define OTG_CFG_ULPI_DDR_SEL (1 << 7) 848 #define OTG_CFG_HS_PHY_SEL (1 << 6) 849 #define OTG_CFG_FS_IF_SEL (1 << 5) 850 #define OTG_CFG_ULPI_UTMI_SEL (1 << 4) 851 #define OTG_CFG_PHY_IF (1 << 3) 852 #define OTG_CFG_TIMEOUT(x) (((x) & 0x7) << 0) 853 #define OTG_RST_AHB_IDLE (1 << 31) 854 #define OTG_RST_DMA_ACTIVE (1 << 30) 855 #define OTG_RST_TXQ_TO_FLUSH(x) (((x) & 0x1f) << 6) 856 #define OTG_RST_TXQ_FLUSH_ALL 0x10 857 #define OTG_RST_TXQ_FLUSH (1 << 5) 858 #define OTG_RST_RXQ_FLUSH (1 << 4) 859 #define OTG_RST_INQ_FLUSH (1 << 3) 860 #define OTG_RST_HC_FRAME (1 << 2) 861 #define OTG_RST_AHB (1 << 1) 862 #define OTG_RST_CORE (1 << 0) 863 #define OTG_INT_RESUME (1 << 31) 864 #define OTG_INT_SESSION_REQ (1 << 30) 865 #define OTG_INT_DISCONNECT (1 << 29) 866 #define OTG_INT_CONNID_STATUS (1 << 28) 867 #define OTG_INT_PTX_EMPTY (1 << 26) 868 #define OTG_INT_HOST_CHANNEL (1 << 25) 869 #define OTG_INT_PORT_STATUS (1 << 24) 870 #define OTG_INT_DMA_FETCH_SUSPEND (1 << 22) 871 #define OTG_INT_INCOMPLETE_PERIODIC (1 << 21) 872 #define OTG_INT_INCOMPLETE_ISOC (1 << 20) 873 #define OTG_INT_DV_OUT_EP (1 << 19) 874 #define OTG_INT_DV_IN_EP (1 << 18) 875 #define OTG_INT_DV_EP_MISMATCH (1 << 17) 876 #define OTG_INT_DV_PERIODIC_END (1 << 15) 877 #define OTG_INT_DV_ISOC_OUT_DROP (1 << 14) 878 #define OTG_INT_DV_ENUM_COMPLETE (1 << 13) 879 #define OTG_INT_DV_USB_RESET (1 << 12) 880 #define OTG_INT_DV_USB_SUSPEND (1 << 11) 881 #define OTG_INT_DV_USB_EARLY_SUSPEND (1 << 10) 882 #define OTG_INT_I2C (1 << 9) 883 #define OTG_INT_ULPI_CARKIT (1 << 8) 884 #define OTG_INT_DV_OUT_NAK_EFFECTIVE (1 << 7) 885 #define OTG_INT_DV_IN_NAK_EFFECTIVE (1 << 6) 886 #define OTG_INT_NPTX_EMPTY (1 << 5) 887 #define OTG_INT_RX_FIFO (1 << 4) 888 #define OTG_INT_SOF (1 << 3) 889 #define OTG_INT_OTG (1 << 2) 890 #define OTG_INT_MODE_MISMATCH (1 << 1) 891 #define OTG_INT_MODE (1 << 0) 892 #define USB_OTG_SNPSID_CORE_REV_2_00 0x4F542000 893 #define OTG_HC_CFG_FORCE_NO_HS (1 << 2) 894 #define OTG_HC_CFG_FSLS_CLK_SEL(x) (((x) & 0x3) << 0) 895 #define OTG_HC_CFG_FS_CLK_3060 0 896 #define OTG_HC_CFG_FS_CLK_48 1 897 #define OTG_HC_CFG_LS_CLK_3060 0 898 #define OTG_HC_CFG_LS_CLK_48 1 899 #define OTG_HC_CFG_LS_CLK_6 2 900 #define USB_OTG_HC_FRM_NUM(x) (x & 0x3fff) 901 #define USB_OTG_HC_FRM_REM(x) (x >> 16) 902 #define USB_OTG_HC_PORT_SPEED(x) (((x) >> 17) & 0x3) 903 #define USB_OTG_HC_PORT_SPEED_HS 0 904 #define USB_OTG_HC_PORT_SPEED_FS 1 905 #define USB_OTG_HC_PORT_SPEED_LS 2 906 #define USB_OTG_HC_PORT_TEST(x) (((x) & 0xf) << 13) 907 #define USB_OTG_HC_PORT_TEST_DISABLED 0 908 #define USB_OTG_HC_PORT_TEST_J_MODE 1 909 #define USB_OTG_HC_PORT_TEST_K_MODE 2 910 #define USB_OTG_HC_PORT_TEST_NAK_MODE 3 911 #define USB_OTG_HC_PORT_TEST_PKT_MODE 4 912 #define USB_OTG_HC_PORT_TEST_FORCE_MODE 5 913 #define USB_OTG_HC_PORT_POWER (1 << 12) 914 #define USB_OTG_HC_PORT_LINE_STAT (((x) >> 10) & 0x3) 915 #define USB_OTG_HC_PORT_LINE_STAT_DP 1 916 #define USB_OTG_HC_PORT_LINE_STAT_DM 3 917 #define USB_OTG_HC_PORT_RESET (1 << 8) 918 #define USB_OTG_HC_PORT_SUSPEND (1 << 7) 919 #define USB_OTG_HC_PORT_RESUME (1 << 6) 920 #define USB_OTG_HC_PORT_OVCURR_CHANGE (1 << 5) 921 #define USB_OTG_HC_PORT_OVCURR (1 << 4) 922 #define USB_OTG_HC_PORT_ENABLE_CHANGE (1 << 3) 923 #define USB_OTG_HC_PORT_ENABLE (1 << 2) 924 #define USB_OTG_HC_PORT_CONNECT_CHANGE (1 << 1) 925 #define USB_OTG_HC_PORT_STATUS (1 << 0) 926 #define USB_OTG_HC_CH_CFG_ENABLE (1 << 31) 927 #define USB_OTG_HC_CH_CFG_DISABLE (1 << 30) 928 #define USB_OTG_HC_CH_CFG_ODD_FRAME (1 << 29) 929 #define USB_OTG_HC_CH_CFG_DEV_ADDR(x) (((x) & 0x7f) << 22) 930 #define USB_OTG_HC_CH_CFG_MULTI_CNT(x) (((x) & 0x3) << 20) 931 #define USB_OTG_HC_CH_CFG_EP_TYPE(x) (((x) & 0x3) << 18) 932 #define USB_OTG_HC_CH_CFG_EP_TYPE_CTRL 0 933 #define USB_OTG_HC_CH_CFG_EP_TYPE_ISOC 1 934 #define USB_OTG_HC_CH_CFG_EP_TYPE_BULK 2 935 #define USB_OTG_HC_CH_CFG_EP_TYPE_INTR 3 936 #define USB_OTG_HC_CH_CFG_LS (1 << 17) 937 #define USB_OTG_HC_CH_CFG_EP_DIR(x) (((x) & 0x1) << 15) 938 #define USB_OTG_HC_CH_CFG_EP_DIR_OUT 0 939 #define USB_OTG_HC_CH_CFG_EP_DIR_IN 1 940 #define USB_OTG_HC_CH_CFG_EP_NUM(x) (((x) & 0xf) << 11) 941 #define USB_OTG_HC_CH_CFG_MAX_PKT_SZ(x) (((x) & 0x7ff) << 0) 942 #define USB_OTG_HC_CH_SPLT_EN (1 << 31) 943 #define USB_OTG_HC_CH_SPLT_COMPLETE (1 << 16) 944 #define USB_OTG_HC_CH_SPLT_POS(x) (((x) & 0x3) << 14) 945 #define USB_OTG_HC_CH_SPLT_POS_MID 0 946 #define USB_OTG_HC_CH_SPLT_POS_END 1 947 #define USB_OTG_HC_CH_SPLT_POS_BEGIN 2 948 #define USB_OTG_HC_CH_SPLT_POS_ALL 3 949 #define USB_OTG_HC_CH_SPLT_HUB_ADDR(x) (((x) & 0x7f) << 7) 950 #define USB_OTG_HC_CH_SPLT_PORT_ADDR(x) (((x) & 0x7f) << 0) 951 #define USB_OTG_HC_CH_INT_ALL 0x7ff 952 #define USB_OTG_HC_CH_INT_TOGGLE_ERROR (1 << 10) 953 #define USB_OTG_HC_CH_INT_FRAME_OVERRUN (1 << 9) 954 #define USB_OTG_HC_CH_INT_BABBLE_ERROR (1 << 8) 955 #define USB_OTG_HC_CH_INT_XACT_ERROR (1 << 7) 956 #define USB_OTG_HC_CH_INT_NYET (1 << 6) 957 #define USB_OTG_HC_CH_INT_ACK (1 << 5) 958 #define USB_OTG_HC_CH_INT_NAK (1 << 4) 959 #define USB_OTG_HC_CH_INT_STALL (1 << 3) 960 #define USB_OTG_HC_CH_INT_DMA_ERROR (1 << 2) 961 #define USB_OTG_HC_CH_INT_HALTED (1 << 1) 962 #define USB_OTG_HC_CH_INT_XFER_COMPLETE (1 << 0) 963 #define USB_OTG_HC_CH_XFER_DO_PING (1 << 31) 964 #define USB_OTG_HC_CH_WR_XFER_PID(x) (((x) & 0x3) << 29) 965 #define USB_OTG_HC_CH_RD_XFER_PID(x) (((x) >> 29) & 0x3) 966 #define USB_OTG_HC_CH_XFER_PID_DATA0 0 967 #define USB_OTG_HC_CH_XFER_PID_DATA2 1 968 #define USB_OTG_HC_CH_XFER_PID_DATA1 2 969 #define USB_OTG_HC_CH_XFER_PID_SETUP 3 970 #define USB_OTG_HC_CH_XFER_PID_MDATA 3 971 #define USB_OTG_HC_CH_XFER_SET_PKT_CNT(x) (((x) & 0x3ff) << 19) 972 #define USB_OTG_HC_CH_XFER_SET_BYTES(x) ((x) & 0x7ffff) 973 #define USB_OTG_HC_CH_XFER_GET_PKT_CNT(x) (((x) >> 19) & 0x3ff) 974 #define USB_OTG_HC_CH_XFER_GET_BYTES(x) ((x) & 0x7ffff) 975 976 #endif /* _RALINK_REG_H_ */ 977
Indexes created Sat Oct 25 07:10:08 GMT 2025