ralink_reg.h revision 1.10
1 /* $NetBSD: ralink_reg.h,v 1.10 2021/08/13 20:47:55 andvar Exp $ */ 2 /*- 3 * Copyright (c) 2011 CradlePoint Technology, Inc. 4 * All rights reserved. 5 * 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY CRADLEPOINT TECHNOLOGY, INC. AND CONTRIBUTORS 17 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 18 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 19 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS 20 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 21 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 22 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 23 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 24 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 25 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 26 * POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 /* 30 * This file contains the configuration parameters for the RT3052 board. 31 */ 32 33 #ifndef _RALINK_REG_H_ 34 #define _RALINK_REG_H_ 35 36 #ifdef _KERNEL_OPT 37 #include "opt_rasoc.h" 38 #endif 39 40 #include <mips/cpuregs.h> 41 42 #if defined(RT3050) 43 #define RA_CLOCK_RATE 320000000 44 #define RA_BUS_FREQ (RA_CLOCK_RATE / 3) 45 #define RA_UART_FREQ RA_BUS_FREQ 46 #elif defined(RT3052) 47 #define RA_CLOCK_RATE 384000000 48 #define RA_BUS_FREQ (RA_CLOCK_RATE / 3) 49 #define RA_UART_FREQ RA_BUS_FREQ 50 #elif defined(RT3883) 51 #if 0 52 #define RA_CLOCK_RATE 480000000 53 #else 54 #define RA_CLOCK_RATE 500000000 55 #endif 56 #define RA_BUS_FREQ 166000000 /* DDR speed */ 57 #define RA_UART_FREQ 40000000 58 #elif defined(MT7620) || defined(MT7628) 59 #define RA_CLOCK_RATE 580000000 60 #define RA_BUS_FREQ (RA_CLOCK_RATE / 3) 61 #define RA_UART_FREQ 40000000 62 #else 63 /* Ralink dev board */ 64 #define RA_CLOCK_RATE 384000000 65 #define RA_BUS_FREQ (RA_CLOCK_RATE / 3) 66 #define RA_UART_FREQ RA_BUS_FREQ 67 #endif 68 69 #define RA_BAUDRATE CONSPEED 70 #define RA_SERIAL_CLKDIV 16 71 72 #define RA_SRAM_BASE 0x00000000 73 #define RA_SRAM_END 0x0FFFFFFF 74 #define RA_SYSCTL_BASE 0x10000000 75 #define RA_TIMER_BASE 0x10000100 76 #define RA_INTCTL_BASE 0x10000200 77 #define RA_MEMCTL_BASE 0x10000300 78 #if defined(RT3052) || defined(RT3050) 79 #define RA_PCM_BASE 0x10000400 80 #endif 81 #if !defined(MT7628) 82 #define RA_UART_BASE 0x10000500 83 #endif 84 #define RA_PIO_BASE 0x10000600 85 #if defined(RT3052) || defined(RT3050) 86 #define RA_GDMA_BASE 0x10000700 87 #elif defined(RT3883) 88 #define RA_FLASHCTL_BASE 0x10000700 89 #endif 90 #define RA_NANDCTL_BASE 0x10000800 91 #define RA_I2C_BASE 0x10000900 92 #define RA_I2S_BASE 0x10000A00 93 #define RA_SPI_BASE 0x10000B00 94 #define RA_UART_LITE_BASE 0x10000C00 95 #if defined(MT7628) 96 #define RA_UART1_BASE 0x10000D00 97 #define RA_UART2_BASE 0x10000E00 98 #endif 99 #define RA_UART_SIZE 0x00000100 100 #if defined(RT3883) 101 #define RA_PCM_BASE 0x10002000 102 #define RA_GDMA_BASE 0x10002800 103 #define RA_CODEC1_BASE 0x10003000 104 #define RA_CODEC2_BASE 0x10003800 105 #endif 106 #define RA_FRAME_ENGINE_BASE 0x10100000 107 #define RA_ETH_SW_BASE 0x10110000 108 #define RA_ROM_BASE 0x10118000 109 #if defined(RT3883) || defined(MT7620) || defined(MT7628) 110 #define RA_USB_DEVICE_BASE 0x10120000 111 #if defined(MT7620) || defined(MT7628) 112 #define RA_SDHC_BASE 0x10130000 113 #endif 114 #define RA_PCI_BASE 0x10140000 115 #define RA_PCIWIN_BASE 0x10150000 116 #endif 117 #define RA_11N_MAC_BASE 0x10180000 118 #define RA_USB_OTG_BASE 0x101C0000 119 #if defined(RT3883) || defined(MT7620) || defined(MT7628) 120 #define RA_USB_HOST_BASE 0x101C0000 121 #define RA_USB_BLOCK_SIZE 0x1000 122 #define RA_USB_EHCI_BASE (RA_USB_HOST_BASE + 0x0000) 123 #define RA_USB_OHCI_BASE (RA_USB_EHCI_BASE + RA_USB_BLOCK_SIZE) 124 #endif 125 #if defined(RT3052) || defined(RT3050) 126 #define RA_FLASH_BASE 0x1F000000 127 #define RA_FLASH_END 0x1F7FFFFF 128 #elif defined(RT3883) || defined(MT7620) || defined(MT7628) 129 #define RA_FLASH_BASE 0x1C000000 130 #define RA_FLASH_END 0x1DFFFFFF 131 #endif 132 133 #define RA_IOREG_VADDR(base, offset) \ 134 (volatile uint32_t *)MIPS_PHYS_TO_KSEG1((base) + (offset)) 135 136 #define FLD_GET(val,pos,mask) (((val) >> (pos)) & (mask)) 137 #define FLD_SET(val,pos,mask) (((val) & (mask)) << (pos)) 138 139 /* 140 * System Control Registers 141 */ 142 #define RA_SYSCTL_ID0 0x00 143 #define RA_SYSCTL_ID1 0x04 144 #define RA_SYSCTL_REVID 0x0c 145 #define RA_SYSCTL_CFG0 0x10 146 #define RA_SYSCTL_CFG1 0x14 147 #define RA_SYSCTL_CLKCFG0 0x2C 148 #define RA_SYSCTL_CLKCFG1 0x30 149 #define RA_SYSCTL_RST 0x34 150 #define RA_SYSCTL_RSTSTAT 0x38 151 152 #if defined(MT7628) 153 #define RA_SYSCTL_GPIO1MODE 0x60 154 #define RA_SYSCTL_GPIOMODE RA_SYSCTL_GPIO1MODE 155 #define RA_SYSCTL_GPIO2MODE 0x64 156 #else 157 #define RA_SYSCTL_GPIOMODE 0x60 158 #endif 159 160 #if defined(RT3050) || defined(RT3052) 161 #define SYSCTL_CFG0_INIC_EE_SDRAM __BIT(29) 162 #define SYSCTL_CFG0_INIC_8MB_SDRAM __BIT(28) 163 #define SYSCTL_CFG0_GE0_MODE __BITS(24,25) 164 #define SYSCTL_CFG0_BYPASS_PLL __BIT(21) 165 #define SYSCTL_CFG0_BE __BIT(20) 166 #define SYSCTL_CFG0_CPU_CLK_SEL __BIT(18) 167 #define SYSCTL_CFG0_BOOT_FROM __BITS(16,17) 168 #define SYSCTL_CFG0_TEST_CODE __BITS(8,15) 169 #define SYSCTL_CFG0_SRAM_CS_MODE __BITS(2,3) 170 #define SYSCTL_CFG0_SDRAM_CLK_DRV __BIT(0) 171 #elif defined(RT3883) 172 #define SYSCTL_CFG0_BE __BIT(19) 173 #define SYSCTL_CFG0_DRAM_SIZE __BITS(12,14) 174 #define SYSCTL_CFG0_DRAM_2MB 0 175 #define SYSCTL_CFG0_DRAM_8MB 1 176 #define SYSCTL_CFG0_DRAM_16MB 2 177 #define SYSCTL_CFG0_DRAM_32MB 3 178 #define SYSCTL_CFG0_DRAM_64MB 4 179 #define SYSCTL_CFG0_DRAM_128MB 5 180 #define SYSCTL_CFG0_DRAM_256MB 6 181 #elif defined(MT7620) 182 #define SYSCTL_CFG0_TEST_CODE __BITS(31,24) 183 #define SYSCTL_CFG0_BS_SHADOW __BITS(22,12) 184 #define SYSCTL_CFG0_DRAM_FROM_EE __BIT(8) 185 #define SYSCTL_CFG0_DBG_JTAG_MODE __BIT(7) 186 #define SYSCTL_CFG0_XTAL_FREQ_SEL __BIT(6) 187 #define SYSCTL_CFG0_DRAM_TYPE __BITS(5,4) 188 #define SYSCTL_CFG0_CHIP_MODE __BITS(3,0) 189 #elif defined(MT7628) 190 #define SYSCTL_CFG0_TEST_CODE __BITS(31,24) 191 #define SYSCTL_CFG0_BS_SHADOW __BITS(20,12) 192 #define SYSCTL_CFG0_DBG_JTAG_MODE __BIT(8) 193 #define SYSCTL_CFG0_TEST_MODE_1 __BIT(7) 194 #define SYSCTL_CFG0_XTAL_FREQ_SEL __BIT(6) 195 #define SYSCTL_CFG0_EXT_BG __BIT(5) 196 #define SYSCTL_CFG0_TEST_MODE_0 __BIT(4) 197 #define SYSCTL_CFG0_CHIP_MODE __BITS(3,1) 198 #define SYSCTL_CFG0_DRAM_TYPE __BIT(0) 199 #endif 200 201 #if defined(RT3883) || defined(MT7620) 202 #define SYSCTL_CFG1_GE2_MODE __BITS(15,14) 203 #define SYSCTL_CFG1_GE1_MODE __BITS(13,12) 204 #define GE_MODE_RGMII 0 // RGMII mode (10/100/1000) 205 #define GE_MODE_MII 1 // MII mode (10/100) 206 #define GE_MODE_RMII 2 // Reverse MMI (10/100) 207 #define SYSCTL_CFG1_USB0_HOST_MODE __BIT(10) 208 #define SYSCTL_CFG1_PCIE_RC_MODE __BIT(8) 209 #endif 210 #if defined(RT3883) 211 #define SYSCTL_CFG1_PCI_HOST_MODE __BIT(7) 212 #define SYSCTL_CFG1_PCI_66M_MODE __BIT(6) 213 #endif 214 215 #if defined(RT3883) || defined(MT7620) || defined(MT7628) 216 #define SYSCTL_CLKCFG0_REFCLK0_RATE __BITS(11,9) 217 #endif 218 #if defined(RT3883) 219 #define SYSCTL_CLKCFG0_OSC_1US_DIV_3883 __BITS(21,16) 220 #define SYSCTL_CLKCFG0_REFCLK1_RATE __BITS(15,13) 221 #define SYSCTL_CLKCFG0_REFCLK0_IS_OUT __BIT(8) 222 #define SYSCTL_CLKCFG0_CPU_FREQ_ADJ __BITS(3,0) 223 #endif 224 #if defined(MT7620) || defined(MT7628) 225 #define SYSCTL_CLKCFG0_OSC_1US_DIV_7620 __BITS(29,24) 226 #define SYSCTL_CLKCFG0_INT_CLK_FDIV __BITS(22,18) 227 #define SYSCTL_CLKCFG0_INT_CLK_FFRAC __BITS(16,12) 228 #define SYSCTL_CLKCFG0_PERI_CLK_SEL __BIT(4) 229 #endif 230 #if defined(MT7620) 231 #define SYSCTL_CLKCFG0_EPHY_USE_25M __BIT(3) 232 #endif 233 234 #if defined(RT3883) 235 #define SYSCTL_CLKCFG1_PBUS_DIV2 __BIT(30) 236 #define SYSCTL_CLKCFG1_SYS_TCK_EN __BIT(29) 237 #define SYSCTL_CLKCFG1_FE_GDMA_PCLK_EN __BIT(22) 238 #define SYSCTL_CLKCFG1_PCIE_CLK_EN_3883 __BIT(21) 239 #define SYSCTL_CLKCFG1_UPHY1_CLK_EN __BIT(20) 240 #define SYSCTL_CLKCFG1_PCI_CLK_EN __BIT(19) 241 #define SYSCTL_CLKCFG1_UPHY0_CLK_EN_3883 __BIT(18) 242 #define SYSCTL_CLKCFG1_GE2_CLK_EN_3883 __BIT(17) 243 #define SYSCTL_CLKCFG1_GE1_CLK_EN_3883 __BIT(16) 244 #endif 245 #if defined(MT7628) 246 #define SYSCTL_CLKCFG1_PWM_CLK_EN_7628 __BIT(31) 247 #define SYSCTL_CLKCFG1_AUX_SYS_TCK_EN_7628 __BIT(29) 248 #define SYSCTL_CLKCFG1_MIPSC_CLK_EN_7628 __BIT(28) 249 #define SYSCTL_CLKCFG1_UPHY0_CLK_EN_7628 __BIT(22) 250 #define SYSCTL_CLKCFG1_UART2_CLK_EN_7628 __BIT(20) 251 #define SYSCTL_CLKCFG1_UART1_CLK_EN_7628 __BIT(19) 252 #define SYSCTL_CLKCFG1_UART0_CLK_EN_7628 __BIT(12) 253 #endif 254 #if defined(MT7620) 255 #define SYSCTL_CLKCFG1_AUX_SYS_TCK_EN __BIT(28) 256 #define SYSCTL_CLKCFG1_FE_CLK_EN __BIT(21) 257 #define SYSCTL_CLKCFG1_UARTL_CLK_EN __BIT(19) 258 #define SYSCTL_CLKCFG1_GE2_CLK_EN_7620 __BIT(7) 259 #define SYSCTL_CLKCFG1_GE1_CLK_EN_7620 __BIT(6) 260 #define SYSCTL_CLKCFG1_GE2_CLK_EN_7620 __BIT(7) 261 #define SYSCTL_CLKCFG1_GE1_CLK_EN_7620 __BIT(6) 262 #endif 263 #if defined(MT7620) || defined(MT7628) 264 #define SYSCTL_CLKCFG1_SDHC_CLK_EN __BIT(30) 265 #define SYSCTL_CLKCFG1_PCIE_CLK_EN_7620 __BIT(26) 266 #define SYSCTL_CLKCFG1_UPHY0_CLK_EN_7620 __BIT(25) 267 #define SYSCTL_CLKCFG1_ESW_CLK_EN __BIT(23) 268 #define SYSCTL_CLKCFG1_SPI_CLK_EN __BIT(18) 269 #define SYSCTL_CLKCFG1_I2S_CLK_EN __BIT(17) 270 #define SYSCTL_CLKCFG1_I2C_CLK_EN __BIT(16) 271 #define SYSCTL_CLKCFG1_NAND_CLK_EN __BIT(15) 272 #define SYSCTL_CLKCFG1_GDMA_CLK_EN __BIT(14) 273 #define SYSCTL_CLKCFG1_GPIO_CLK_EN __BIT(13) 274 #define SYSCTL_CLKCFG1_UART_CLK_EN __BIT(12) 275 #define SYSCTL_CLKCFG1_PCM_CLK_EN __BIT(11) 276 #define SYSCTL_CLKCFG1_MC_CLK_EN __BIT(10) 277 #define SYSCTL_CLKCFG1_INTC_CLK_EN __BIT(9) 278 #define SYSCTL_CLKCFG1_TIMER_CLK_EN __BIT(8) 279 #endif 280 281 #if defined(RT3883) || defined(MT7620) 282 /* 3883 doesn't have memo regs, use teststat instead */ 283 #define RA_SYSCTL_MEMO0 0x18 284 #define RA_SYSCTL_MEMO1 0x1C 285 #else 286 #define RA_SYSCTL_MEMO0 0x68 287 #define RA_SYSCTL_MEMO1 0x6C 288 #endif 289 290 #define RST_PPE_7620 __BIT(31) 291 #define RST_PWM_7628 __BIT(31) 292 #define RST_SDHC_7620 __BIT(30) 293 #define RST_CRYPTO_7628 __BIT(29) 294 #define RST_MIPS_CNT_7620 __BIT(28) 295 #define RST_PCIPCIE_3883 __BIT(27) 296 #define RST_FLASH_3883 __BIT(26) 297 #define RST_PCIE0_7620 __BIT(26) 298 #define RST_UDEV_3883 __BIT(25) 299 #define RST_UHST0_7620 __BIT(25) 300 #define RST_PCI_3883 __BIT(24) 301 #define RST_EPHY_7620 __BIT(24) 302 #define RST_PCIE_3883 __BIT(23) 303 #define RST_ESW_7620 __BIT(23) 304 #define RST_UHST __BIT(22) 305 #define RST_FE __BIT(21) 306 #define RST_WLAN __BIT(20) 307 #define RST_UART2_7628 __BIT(20) 308 #define RST_UARTL __BIT(19) 309 #define RST_UART1_7628 __BIT(19) 310 #define RST_SPI __BIT(18) 311 #define RST_I2S __BIT(17) 312 #define RST_I2C __BIT(16) 313 #define RST_NAND __BIT(15) 314 #define RST_DMA __BIT(14) 315 #define RST_PIO __BIT(13) 316 #define RST_UART __BIT(12) 317 #define RST_UART0_7628 __BIT(12) 318 #define RST_PCM __BIT(11) 319 #define RST_MC __BIT(10) 320 #define RST_INTC __BIT(9) 321 #define RST_TIMER __BIT(8) 322 #define RST_GE2 __BIT(7) 323 #define RST_GE1 __BIT(6) 324 #define RST_HIF_7628 __BIT(5) 325 #define RST_WIFI_7628 __BIT(4) 326 #define RST_SPIS_7628 __BIT(3) 327 #define RST_SYS __BIT(0) 328 329 #if defined(MT7628) 330 #define GPIO1MODE_PWM1 __BITS(31,30) 331 #define GPIO1MODE_PWM0 __BITS(29,18) 332 #define GPIO1MODE_UART2 __BITS(27,26) 333 #define GPIO1MODE_UART1 __BITS(25,24) 334 #define GPIO1MODE_I2C __BITS(21,20) 335 #define GPIOMODE_I2C GPIO1MODE_I2C 336 #define GPIO1MODE_REFCLK __BIT(18) 337 #define GPIO1MODE_PERST __BIT(16) 338 #define GPIO1MODE_ESD __BIT(15) 339 #define GPIO1MODE_WDT __BIT(14) 340 #define GPIO1MODE_SPI __BIT(12) 341 #define GPIO1MODE_SD __BITS(11,10) 342 #define GPIO1MODE_UART0 __BITS(9,8) 343 #define GPIO1MODE_I2S __BITS(7,6) 344 #define GPIO1MODE_SPI_CS1 __BITS(5,4) 345 #define GPIO1MODE_SPIS __BITS(3,2) 346 #define GPIO1MODE_GPIO __BITS(1,0) 347 #define GPIO2MODE_P4_LED_KN __BITS(27,26) 348 #define GPIO2MODE_P3_LED_KN __BITS(25,24) 349 #define GPIO2MODE_P2_LED_KN __BITS(23,22) 350 #define GPIO2MODE_P1_LED_KN __BITS(21,10) 351 #define GPIO2MODE_P0_LED_KN __BITS(19,18) 352 #define GPIO2MODE_WLED_KN __BITS(17,16) 353 #define GPIO2MODE_P4_LED_AN __BITS(11,10) 354 #define GPIO2MODE_P3_LED_AN __BITS(9,8) 355 #define GPIO2MODE_P2_LED_AN __BITS(7,6) 356 #define GPIO2MODE_P1_LED_AN __BITS(5,4) 357 #define GPIO2MODE_P0_LED_AN __BITS(3,2) 358 #define GPIO2MODE_WLED_AN __BITS(1,0) 359 #else 360 #define GPIOMODE_RGMII __BIT(9) 361 #define GPIOMODE_SDRAM __BIT(8) 362 #define GPIOMODE_MDIO __BIT(7) 363 #define GPIOMODE_JTAG __BIT(6) 364 #define GPIOMODE_UARTL __BIT(5) 365 #define GPIOMODE_UARTF2 __BIT(4) 366 #define GPIOMODE_UARTF1 __BIT(3) 367 #define GPIOMODE_UARTF0 __BIT(2) 368 #define GPIOMODE_UARTF_0_2 \ 369 (GPIOMODE_UARTF0|GPIOMODE_UARTF1|GPIOMODE_UARTF2) 370 #define GPIOMODE_SPI __BIT(1) 371 #define GPIOMODE_I2C __BIT(0) 372 #endif 373 374 /* 375 * Timer Registers 376 */ 377 #define RA_TIMER_STAT 0x00 378 #define RA_TIMER_0_LOAD 0x10 379 #define RA_TIMER_0_VALUE 0x14 380 #define RA_TIMER_0_CNTRL 0x18 381 #define RA_TIMER_1_LOAD 0x20 382 #define RA_TIMER_1_VALUE 0x24 383 #define RA_TIMER_1_CNTRL 0x28 384 385 #define TIMER_1_RESET __BIT(5) 386 #define TIMER_0_RESET __BIT(4) 387 #define TIMER_1_INT_STATUS __BIT(1) 388 #define TIMER_0_INT_STATUS __BIT(0) 389 #define TIMER_TEST_EN __BIT(15) 390 #define TIMER_EN __BIT(7) 391 #define TIMER_MODE(x) (((x) & 0x3) << 4) 392 #define TIMER_MODE_FREE 0 393 #define TIMER_MODE_PERIODIC 1 394 #define TIMER_MODE_TIMEOUT 2 395 #define TIMER_MODE_WDOG 3 /* only valid for TIMER_1 */ 396 #define TIMER_PRESCALE(x) (((x) & 0xf) << 0) 397 #define TIMER_PRESCALE_DIV_1 0 398 #define TIMER_PRESCALE_DIV_4 1 399 #define TIMER_PRESCALE_DIV_8 2 400 #define TIMER_PRESCALE_DIV_16 3 401 #define TIMER_PRESCALE_DIV_32 4 402 #define TIMER_PRESCALE_DIV_64 5 403 #define TIMER_PRESCALE_DIV_128 6 404 #define TIMER_PRESCALE_DIV_256 7 405 #define TIMER_PRESCALE_DIV_512 8 406 #define TIMER_PRESCALE_DIV_1024 9 407 #define TIMER_PRESCALE_DIV_2048 10 408 #define TIMER_PRESCALE_DIV_4096 11 409 #define TIMER_PRESCALE_DIV_8192 12 410 #define TIMER_PRESCALE_DIV_16384 13 411 #define TIMER_PRESCALE_DIV_32768 14 412 #define TIMER_PRESCALE_DIV_65536 15 413 414 /* 415 * Interrupt Controller Registers 416 */ 417 #if defined(MT7628) 418 #define RA_INTCTL_IRQ0STAT 0x9c 419 #define RA_INTCTL_IRQ1STAT 0xa0 420 #define RA_INTCTL_TYPE 0x00 421 #define RA_INTCTL_RAW 0xa4 422 #define RA_INTCTL_ENABLE 0x80 423 #define RA_INTCTL_DISABLE 0x78 424 #else 425 #define RA_INTCTL_IRQ0STAT 0x00 426 #define RA_INTCTL_IRQ1STAT 0x04 427 #define RA_INTCTL_TYPE 0x20 428 #define RA_INTCTL_RAW 0x30 429 #define RA_INTCTL_ENABLE 0x34 430 #define RA_INTCTL_DISABLE 0x38 431 #endif 432 433 /* Interrupt controller mask bit */ 434 #define INT_GLOBAL 31 435 #define INT_GLOBAL_EN __BIT(INT_GLOBAL) 436 #if defined(MT7628) 437 #define INT_WDOG 24 438 #define INT_UART2 22 439 #define INT_UART1 21 440 #define INT_UARTL 20 441 #endif 442 #define INT_UDEV 19 443 #define INT_USB 18 444 #define INT_ETHSW 17 445 #define INT_R2P 15 446 #define INT_SDHC 14 447 #define INT_CRYPTO 13 448 #if !defined(MT7628) 449 #define INT_UARTL 12 450 #endif 451 #define INT_SPI 11 452 #define INT_I2S 10 453 #define INT_PERF 9 454 #define INT_NAND 8 455 #define INT_DMA 7 456 #define INT_PIO 6 457 #define INT_UARTF 5 458 #define INT_PCM 4 459 #define INT_ILLACC 3 460 #if !defined(MT7628) 461 #define INT_WDOG 2 462 #endif 463 #define INT_TIMER0 1 464 #define INT_SYSCTL 0 465 466 467 /* 468 * Ralink Linear CPU Interrupt Mapping For Lists 469 */ 470 enum ralink_irq { 471 /* CPU interrupts */ 472 RA_IRQ_LOW = 0, 473 RA_IRQ_HIGH, 474 RA_IRQ_PCI, 475 RA_IRQ_FENGINE, 476 RA_IRQ_WLAN, 477 RA_IRQ_TIMER, 478 479 /* pseudo IRQ for Interrupt controller */ 480 RA_IRQ_SYSCTL, 481 RA_IRQ_TIMER0, 482 RA_IRQ_WDOG, 483 RA_IRQ_ILLACC, 484 RA_IRQ_PCM, 485 RA_IRQ_UARTF, 486 RA_IRQ_PIO, 487 RA_IRQ_DMA, 488 RA_IRQ_NAND, 489 RA_IRQ_PERF, 490 RA_IRQ_I2S, 491 RA_IRQ_SPI, 492 RA_IRQ_UARTL, 493 RA_IRQ_CRYPTO, 494 RA_IRQ_SDHC, 495 RA_IRQ_R2P, 496 RA_IRQ_ETHSW, 497 RA_IRQ_USB, 498 RA_IRQ_UDEV, 499 RA_IRQ_UART1, 500 RA_IRQ_UART2, 501 RA_IRQ_MAX 502 }; 503 504 /* 505 * General Purpose I/O 506 */ 507 #if defined(MT7628) 508 #define RA_PIO_00_31_DIR 0x00 509 #define RA_PIO_32_63_DIR 0x04 510 #define RA_PIO_64_95_DIR 0x08 511 #define RA_PIO_00_31_POLARITY 0x10 512 #define RA_PIO_32_63_POLARITY 0x14 513 #define RA_PIO_64_95_POLARITY 0x18 514 #define RA_PIO_00_31_DATA 0x20 515 #define RA_PIO_32_63_DATA 0x24 516 #define RA_PIO_64_95_DATA 0x28 517 #define RA_PIO_00_31_SET_BIT 0x30 518 #define RA_PIO_32_63_SET_BIT 0x34 519 #define RA_PIO_64_95_SET_BIT 0x38 520 #define RA_PIO_00_31_CLR_BIT 0x40 521 #define RA_PIO_32_63_CLR_BIT 0x44 522 #define RA_PIO_64_95_CLR_BIT 0x48 523 #define RA_PIO_00_31_INT_RISE_EN 0x50 524 #define RA_PIO_32_63_INT_RISE_EN 0x54 525 #define RA_PIO_64_95_INT_RISE_EN 0x58 526 #define RA_PIO_00_31_INT_FALL_EN 0x60 527 #define RA_PIO_32_63_INT_FALL_EN 0x64 528 #define RA_PIO_64_95_INT_FALL_EN 0x68 529 #define RA_PIO_00_31_INT_HIGH_EN 0x70 530 #define RA_PIO_32_63_INT_HIGH_EN 0x74 531 #define RA_PIO_64_95_INT_HIGH_EN 0x78 532 #define RA_PIO_00_31_INT_LOW_EN 0x80 533 #define RA_PIO_32_63_INT_LOW_EN 0x84 534 #define RA_PIO_64_95_INT_LOW_EN 0x88 535 #define RA_PIO_00_31_INT_STAT 0x90 536 #define RA_PIO_32_63_INT_STAT 0x94 537 #define RA_PIO_64_95_INT_STAT 0x98 538 #define RA_PIO_00_31_INT_STAT_EDGE 0xA0 539 #define RA_PIO_32_63_INT_STAT_EDGE 0xA4 540 #define RA_PIO_64_95_INT_STAT_EDGE 0xA8 541 #else 542 #define RA_PIO_00_23_INT 0x00 543 #define RA_PIO_00_23_EDGE_INT 0x04 544 #define RA_PIO_00_23_INT_RISE_EN 0x08 545 #define RA_PIO_00_23_INT_FALL_EN 0x0C 546 #define RA_PIO_00_23_DATA 0x20 547 #define RA_PIO_00_23_DIR 0x24 548 #define RA_PIO_00_23_POLARITY 0x28 549 #define RA_PIO_00_23_SET_BIT 0x2C 550 #define RA_PIO_00_23_CLR_BIT 0x30 551 #define RA_PIO_00_23_TGL_BIT 0x34 552 #define RA_PIO_24_39_INT 0x38 553 #define RA_PIO_24_39_EDGE_INT 0x3C 554 #define RA_PIO_24_39_INT_RISE_EN 0x40 555 #define RA_PIO_24_39_INT_FALL_EN 0x44 556 #define RA_PIO_24_39_DATA 0x48 557 #define RA_PIO_24_39_DIR 0x4C 558 #define RA_PIO_24_39_POLARITY 0x50 559 #define RA_PIO_24_39_SET_BIT 0x54 560 #define RA_PIO_24_39_CLR_BIT 0x58 561 #define RA_PIO_24_39_TGL_BIT 0x5C 562 #define RA_PIO_40_51_INT 0x60 563 #define RA_PIO_40_51_EDGE_INT 0x64 564 #define RA_PIO_40_51_INT_RISE_EN 0x68 565 #define RA_PIO_40_51_INT_FALL_EN 0x6C 566 #define RA_PIO_40_51_DATA 0x70 567 #define RA_PIO_40_51_DIR 0x74 568 #define RA_PIO_40_51_POLARITY 0x78 569 #define RA_PIO_40_51_SET_BIT 0x7C 570 #define RA_PIO_40_51_CLR_BIT 0x80 571 #define RA_PIO_40_51_TGL_BIT 0x84 572 #define RA_PIO_72_95_INT 0x88 573 #define RA_PIO_72_95_EDGE_INT 0x8c 574 #define RA_PIO_72_95_INT_RISE_EN 0x90 575 #define RA_PIO_72_95_INT_FALL_EN 0x94 576 #define RA_PIO_72_95_DATA 0x98 577 #define RA_PIO_72_95_DIR 0x9c 578 #define RA_PIO_72_95_POLARITY 0xa0 579 #define RA_PIO_72_95_SET_BIT 0xa4 580 #define RA_PIO_72_95_CLR_BIT 0xa8 581 #define RA_PIO_72_95_TGL_BIT 0xac 582 #endif 583 584 /* 585 * UART registers 586 */ 587 588 #if defined(MT7628) 589 #define RA_UART_RBR 0x00 590 #define RA_UART_TBR 0x00 591 #define RA_UART_IER 0x04 592 #define RA_UART_IIR 0x08 593 #define RA_UART_FCR 0x08 594 #define RA_UART_LCR 0x0c 595 #define RA_UART_MCR 0x10 596 #define RA_UART_LSR 0x14 597 #define RA_UART_MSR 0x18 598 #define RA_UART_DLL 0x00 599 #define RA_UART_DLM 0x04 600 #else 601 #define RA_UART_RBR 0x00 602 #define RA_UART_TBR 0x04 603 #define RA_UART_IER 0x08 604 #define RA_UART_IIR 0x0C 605 #define RA_UART_FCR 0x10 606 #define RA_UART_LCR 0x14 607 #define RA_UART_MCR 0x18 608 #define RA_UART_LSR 0x1C 609 #define RA_UART_MSR 0x20 610 #define RA_UART_DLL 0x28 611 #endif 612 613 614 #define UART_IER_ELSI __BIT(2) /* RX Line Status Interrupt Enable */ 615 #define UART_IER_ETBEI __BIT(1) /* TX Buffer Empty Interrupt Enable */ 616 #define UART_IER_ERBFI __BIT(0) 617 /* Data Ready or Character Time-Out Interrupt Enable */ 618 619 #define UART_IIR_FIFOES1 __BIT(7) /* FIFO Mode Enable Status */ 620 #define UART_IIR_FIFOES0 __BIT(6) /* FIFO Mode Enable Status */ 621 #define UART_IIR_IID3 __BIT(3) /* Interrupt Source Encoded */ 622 #define UART_IIR_IID2 __BIT(2) /* Interrupt Source Encoded */ 623 #define UART_IIR_IID1 __BIT(1) /* Interrupt Source Encoded */ 624 #define UART_IIR_IP __BIT(0) /* Interrupt Pending (active low) */ 625 626 #define UART_FCR_RXTRIG1 __BIT(7) /* RX Interrupt Trigger Level */ 627 #define UART_FCR_RXTRIG0 __BIT(6) /* RX Interrupt Trigger Level */ 628 #define UART_FCR_TXTRIG1 __BIT(5) /* TX Interrupt Trigger Level */ 629 #define UART_FCR_TXTRIG0 __BIT(4) /* TX Interrupt Trigger Level */ 630 #define UART_FCR_DMAMODE __BIT(3) /* Enable DMA transfers */ 631 #define UART_FCR_TXRST __BIT(2) /* Reset Transmitter FIFO */ 632 #define UART_FCR_RXRST __BIT(1) /* Reset Receiver FIFO */ 633 #define UART_FCR_FIFOE __BIT(0) /* Transmit and Receive FIFO Enable */ 634 635 #define UART_LCR_DLAB __BIT(7) /* Divisor Latch Access Bit */ 636 #define UART_LCR_SB __BIT(6) /* Set Break */ 637 #define UART_LCR_STKYP __BIT(5) /* Sticky Parity */ 638 #define UART_LCR_EPS __BIT(4) /* Even Parity Select */ 639 #define UART_LCR_PEN __BIT(3) /* Parity Enable */ 640 #define UART_LCR_STB __BIT(2) /* Stop Bit */ 641 #define UART_LCR_WLS1 __BIT(1) /* Word Length Select */ 642 #define UART_LCR_WLS0 __BIT(0) /* Word Length Select */ 643 644 #define UART_MCR_LOOP __BIT(4) /* Loop-back Mode Enable */ 645 646 #define UART_MSR_DCD __BIT(7) /* Data Carrier Detect */ 647 #define UART_MSR_RI __BIT(6) /* Ring Indicator */ 648 #define UART_MSR_DSR __BIT(5) /* Data Set Ready */ 649 #define UART_MSR_CTS __BIT(4) /* Clear To Send */ 650 #define UART_MSR_DDCD __BIT(3) /* Delta Data Carrier Detect */ 651 #define UART_MSR_TERI __BIT(2) /* Trailing Edge Ring Indicator */ 652 #define UART_MSR_DDSR __BIT(1) /* Delta Data Set Ready */ 653 #define UART_MSR_DCTS __BIT(0) /* Delta Clear To Send */ 654 655 #define UART_LSR_FIFOE __BIT(7) /* FIFO Error Status */ 656 #define UART_LSR_TEMT __BIT(6) /* Transmitter Empty */ 657 #define UART_LSR_TDRQ __BIT(5) /* Transmit Data Request */ 658 #define UART_LSR_BI __BIT(4) /* Break Interrupt */ 659 #define UART_LSR_FE __BIT(3) /* Framing Error */ 660 #define UART_LSR_PE __BIT(2) /* Parity Error */ 661 #define UART_LSR_OE __BIT(1) /* Overrun Error */ 662 #define UART_LSR_DR __BIT(0) /* Data Ready */ 663 664 /* 665 * I2C registers 666 */ 667 #define RA_I2C_CONFIG 0x00 668 #define RA_I2C_CLKDIV 0x04 669 #define RA_I2C_DEVADDR 0x08 670 #define RA_I2C_ADDR 0x0C 671 #define RA_I2C_DATAOUT 0x10 672 #define RA_I2C_DATAIN 0x14 673 #define RA_I2C_STATUS 0x18 674 #define RA_I2C_STARTXFR 0x1C 675 #define RA_I2C_BYTECNT 0x20 676 677 #define I2C_CONFIG_ADDRLEN(x) (((x) & 0x7) << 5) 678 #define I2C_CONFIG_ADDRLEN_7 6 679 #define I2C_CONFIG_ADDRLEN_8 7 680 #define I2C_CONFIG_DEVADLEN(x) (((x) & 0x7) << 2) 681 #define I2C_CONFIG_DEVADLEN_6 5 682 #define I2C_CONFIG_DEVADLEN_7 6 683 #define I2C_CONFIG_ADDRDIS __BIT(1) 684 #define I2C_CONFIG_DEVDIS __BIT(0) 685 #define I2C_STATUS_STARTERR __BIT(4) 686 #define I2C_STATUS_ACKERR __BIT(3) 687 #define I2C_STATUS_DATARDY __BIT(2) 688 #define I2C_STATUS_SDOEMPTY __BIT(1) 689 #define I2C_STATUS_BUSY __BIT(0) 690 691 /* 692 * SPI registers 693 */ 694 #define RA_SPI_STATUS 0x00 695 #define RA_SPI_CONFIG 0x10 696 #define RA_SPI_CONTROL 0x14 697 #define RA_SPI_DATA 0x20 698 699 #define SPI_STATUS_BUSY __BIT(0) 700 #define SPI_CONFIG_MSBFIRST __BIT(8) 701 #define SPI_CONFIG_CLK __BIT(6) 702 #define SPI_CONFIG_RXCLKEDGE_FALL __BIT(5) 703 #define SPI_CONFIG_TXCLKEDGE_FALL __BIT(4) 704 #define SPI_CONFIG_TRISTATE __BIT(3) 705 #define SPI_CONFIG_RATE(x) ((x) & 0x7) 706 #define SPI_CONFIG_RATE_DIV_2 0 707 #define SPI_CONFIG_RATE_DIV_4 1 708 #define SPI_CONFIG_RATE_DIV_8 2 709 #define SPI_CONFIG_RATE_DIV_16 3 710 #define SPI_CONFIG_RATE_DIV_32 4 711 #define SPI_CONFIG_RATE_DIV_64 5 712 #define SPI_CONFIG_RATE_DIV_128 6 713 #define SPI_CONFIG_RATE_DIV_NONE 7 714 #define SPI_CONTROL_TRISTATE __BIT(3) 715 #define SPI_CONTROL_STARTWR __BIT(2) 716 #define SPI_CONTROL_STARTRD __BIT(1) 717 #define SPI_CONTROL_ENABLE_LOW (0 << 0) 718 #define SPI_CONTROL_ENABLE_HIGH __BIT(0) 719 #define SPI_DATA_VAL(x) ((x) & 0xff) 720 721 /* 722 * Frame Engine registers 723 */ 724 #if defined(MT7628) 725 #define RA_FE_TX_BASE_PTR_0 0x800 /* TX Ring #0 Base Pointer */ 726 #define RA_FE_TX_MAX_CNT_0 0x804 /* TX Ring #0 Maximum Count */ 727 #define RA_FE_TX_CTX_IDX_0 0x808 /* TX Ring #0 CPU pointer */ 728 #define RA_FE_TX_DTX_IDX_0 0x80c /* TX Ring #0 DMA pointer */ 729 #define RA_FE_PDMA_TX0_PTR RA_FE_TX_BASE_PTR_0 730 #define RA_FE_PDMA_TX0_COUNT RA_FE_TX_MAX_CNT_0 731 #define RA_FE_PDMA_TX0_CPU_IDX RA_FE_TX_CTX_IDX_0 732 #define RA_FE_PDMA_TX0_DMA_IDX RA_FE_TX_DTX_IDX_0 733 #define RA_FE_TX_BASE_PTR_1 0x810 /* TX Ring #1 Base Pointer */ 734 #define RA_FE_TX_MAX_CNT_1 0x814 /* TX Ring #1 Maximum Count */ 735 #define RA_FE_TX_CTX_IDX_1 0x818 /* TX Ring #1 CPU pointer */ 736 #define RA_FE_TX_DTX_IDX_1 0x81c /* TX Ring #1 DMA pointer */ 737 #define RA_FE_TX_BASE_PTR_2 0x820 /* TX Ring #2 Base Pointer */ 738 #define RA_FE_TX_MAX_CNT_2 0x824 /* TX Ring #2 Maximum Count */ 739 #define RA_FE_TX_CTX_IDX_2 0x828 /* TX Ring #2 CPU pointer */ 740 #define RA_FE_TX_DTX_IDX_2 0x82c /* TX Ring #2 DMA pointer */ 741 #define RA_FE_TX_BASE_PTR_3 0x830 /* TX Ring #3 Base Pointer */ 742 #define RA_FE_TX_MAX_CNT_3 0x834 /* TX Ring #3 Maximum Count */ 743 #define RA_FE_TX_CTX_IDX_3 0x838 /* TX Ring #3 CPU pointer */ 744 #define RA_FE_TX_DTX_IDX_3 0x83c /* TX Ring #3 DMA pointer */ 745 #define RA_FE_RX_BASE_PTR_0 0x900 /* RX Ring #0 Base Pointer */ 746 #define RA_FE_RX_MAX_CNT_0 0x904 /* RX Ring #0 Maximum Count */ 747 #define RA_FE_RX_CRX_IDX_0 0x908 /* RX Ring #0 CPU pointer */ 748 #define RA_FE_RX_DRX_IDX_0 0x90c /* RX Ring #0 DMA pointer */ 749 #define RA_FE_PDMA_RX0_PTR RA_FE_RX_BASE_PTR_0 750 #define RA_FE_PDMA_RX0_COUNT RA_FE_RX_MAX_CNT_0 751 #define RA_FE_PDMA_RX0_CPU_IDX RA_FE_RX_CRX_IDX_0 752 #define RA_FE_PDMA_RX0_DMA_IDX RA_FE_RX_DRX_IDX_0 753 #define RA_FE_RX_BASE_PTR_1 0x910 /* RX Ring #1 Base Pointer */ 754 #define RA_FE_RX_MAX_CNT_1 0x914 /* RX Ring #1 Maximum Count */ 755 #define RA_FE_RX_CRX_IDX_1 0x918 /* RX Ring #1 CPU pointer */ 756 #define RA_FE_RX_DRX_IDX_1 0x91c /* RX Ring #1 DMA pointer */ 757 #define RA_FE_PDMA_INFO 0xa00 /* PDMA Information */ 758 #define RA_FE_PDMA_GLOBAL_CFG 0xa04 /* PDMA Global Configuration */ 759 #define RA_FE_DELAY_INT_CFG 0xa0c /* Delay Interrupt Configuration */ 760 #define RA_FE_FREEQ_THRES 0xa10 /* Free Queue Threshold */ 761 #define RA_FE_INT_STATUS 0xa20 /* Interrupt Status */ 762 #define RA_FE_INT_MASK 0xa28 /* Interrupt Mask */ 763 #define RA_FE_INT_RX_COHERENT __BIT(31) 764 #define RA_FE_INT_RX_DLY __BIT(30) 765 #define RA_FE_INT_TX_COHERENT __BIT(29) 766 #define RA_FE_INT_TX_DLY_INT __BIT(28) 767 #define RA_FE_INT_RX_DONE_INT1 __BIT(17) 768 #define RA_FE_INT_RX_DONE_INT0 __BIT(16) 769 #define RA_FE_INT_TX_DONE_INT3 __BIT(3) 770 #define RA_FE_INT_TX_DONE_INT2 __BIT(2) 771 #define RA_FE_INT_TX_DONE_INT1 __BIT(1) 772 #define RA_FE_INT_TX_DONE_INT0 __BIT(0) 773 774 #define RA_FE_PDMA_SCH 0xa80 /* Scheduler Configuration for Q0&Q1 */ 775 #define RA_FE_PDMA_WRR 0xa84 /* Scheduler Configuration for Q2&Q3 */ 776 #define RA_FE_SDM_CON 0xc00 /* Switch DMA Control */ 777 #define RA_FE_SDM_RING 0xc04 /* Switch DMA Rx Ring */ 778 #define RA_FE_SDM_TRING 0xc08 /* Switch DMA TX Ring */ 779 #define RA_FE_SDM_MAC_ADRL 0xc0c /* Switch MAC Address LSB */ 780 #define RA_FE_SDM_MAC_ADRH 0xc10 /* Switch MAC Address MSB */ 781 #define RA_FE_GDMA1_MAC_LSB RA_FE_SDM_MAC_ADRL 782 #define RA_FE_GDMA1_MAC_MSB RA_FE_SDM_MAC_ADRH 783 #define RA_FE_SDM_TPCNT 0xd00 /* Switch DMA Tx Packet Count */ 784 #define RA_FE_SDM_TBCNT 0xd04 /* Switch DMA TX Byte Count */ 785 #define RA_FE_SDM_RPCNT 0xd08 /* Switch DMA RX Packet Count */ 786 #define RA_FE_SDM_RBCNT 0xd0c /* Switch DMA RX Byte Count */ 787 #define RA_FE_SDM_CS_ERR 0xd10 /* Switch DMA RX Checksum Error */ 788 #else /* !MT7628 */ 789 #define RA_FE_MDIO_ACCESS 0x000 790 #define RA_FE_MDIO_CFG1 0x004 791 #define RA_FE_GLOBAL_CFG 0x008 792 #define RA_FE_GLOBAL_RESET 0x00C 793 #define RA_FE_INT_STATUS 0x010 794 #define RA_FE_INT_ENABLE 0x014 795 #define RA_FE_MDIO_CFG2 0x018 796 #define RA_FE_TIME_STAMP 0x01C 797 #define RA_FE_GDMA1_FWD_CFG 0x020 798 #define RA_FE_GDMA1_SCHED_CFG 0x024 799 #define RA_FE_GDMA1_SHAPE_CFG 0x028 800 #define RA_FE_GDMA1_MAC_LSB 0x02C 801 #define RA_FE_GDMA1_MAC_MSB 0x030 802 #define RA_FE_PSE_FQ_CFG 0x040 803 #define RA_FE_CDMA_FC_CFG 0x044 804 #define RA_FE_GDMA1_FC_CFG 0x048 805 #define RA_FE_GDMA2_FC_CFG 0x04C 806 #define RA_FE_CDMA_OQ_STA 0x050 807 #define RA_FE_GDMA1_OQ_STA 0x054 808 #define RA_FE_GDMA2_OQ_STA 0x058 809 #define RA_FE_PSE_IQ_STA 0x05C 810 #define RA_FE_GDMA2_FWD_CFG 0x060 811 #define RA_FE_GDMA2_SCHED_CFG 0x064 812 #define RA_FE_GDMA2_SHAPE_CFG 0x068 813 #define RA_FE_GDMA2_MAC_LSB 0x06C 814 #define RA_FE_GDMA2_MAC_MSB 0x070 815 #define RA_FE_CDMA_CSG_CFG 0x080 816 #define RA_FE_CDMA_SCHED_CFG 0x084 817 #define RA_FE_PPPOE_SID_0001 0x088 818 #define RA_FE_PPPOE_SID_0203 0x08C 819 #define RA_FE_PPPOE_SID_0405 0x090 820 #define RA_FE_PPPOE_SID_0607 0x094 821 #define RA_FE_PPPOE_SID_0809 0x098 822 #define RA_FE_PPPOE_SID_1011 0x09C 823 #define RA_FE_PPPOE_SID_1213 0x0A0 824 #define RA_FE_PPPOE_SID_1415 0x0A4 825 #define RA_FE_VLAN_ID_0001 0x0A8 826 #define RA_FE_VLAN_ID_0203 0x0AC 827 #define RA_FE_VLAN_ID_0405 0x0B0 828 #define RA_FE_VLAN_ID_0607 0x0B4 829 #define RA_FE_VLAN_ID_0809 0x0B8 830 #define RA_FE_VLAN_ID_1011 0x0BC 831 #define RA_FE_VLAN_ID_1213 0x0C0 832 #define RA_FE_VLAN_ID_1415 0x0C4 833 #define RA_FE_PDMA_GLOBAL_CFG 0x100 834 #define RA_FE_PDMA_RESET_IDX 0x104 835 #define RA_FE_PDMA_SCHED_CFG 0x108 836 #define RA_FE_PDMA_DLY_INT_CFG 0x10C 837 #define RA_FE_PDMA_TX0_PTR 0x110 838 #define RA_FE_PDMA_TX0_COUNT 0x114 839 #define RA_FE_PDMA_TX0_CPU_IDX 0x118 840 #define RA_FE_PDMA_TX0_DMA_IDX 0x11C 841 #define RA_FE_PDMA_TX1_PTR 0x120 842 #define RA_FE_PDMA_TX1_COUNT 0x124 843 #define RA_FE_PDMA_TX1_CPU_IDX 0x128 844 #define RA_FE_PDMA_TX1_DMA_IDX 0x12C 845 #define RA_FE_PDMA_RX0_PTR 0x130 846 #define RA_FE_PDMA_RX0_COUNT 0x134 847 #define RA_FE_PDMA_RX0_CPU_IDX 0x138 848 #define RA_FE_PDMA_RX0_DMA_IDX 0x13C 849 #define RA_FE_PDMA_TX2_PTR 0x140 850 #define RA_FE_PDMA_TX2_COUNT 0x144 851 #define RA_FE_PDMA_TX2_CPU_IDX 0x148 852 #define RA_FE_PDMA_TX2_DMA_IDX 0x14C 853 #define RA_FE_PDMA_TX3_PTR 0x150 854 #define RA_FE_PDMA_TX3_COUNT 0x154 855 #define RA_FE_PDMA_TX3_CPU_IDX 0x158 856 #define RA_FE_PDMA_TX3_DMA_IDX 0x15C 857 #define RA_FE_PDMA_FC_CFG 0x1F0 858 #endif /* !MT7628 */ 859 /* TODO: FE_COUNTERS */ 860 861 #define MDIO_ACCESS_TRG __BIT(31) 862 #define MDIO_ACCESS_WR __BIT(30) 863 #define MDIO_ACCESS_PHY_ADDR(x) (((x) & 0x1f) << 24) 864 #define MDIO_ACCESS_REG(x) (((x) & 0x1f) << 16) 865 #define MDIO_ACCESS_DATA(x) ((x) & 0xffff) 866 #define MDIO_CFG_AUTO_POLL __BIT(29) 867 #define MDIO_CFG_PHY_ADDR(x) (((x) & 0x1f) << 24) 868 #define MDIO_CFG_BP_EN __BIT(16) 869 #define MDIO_CFG_FORCE_CFG __BIT(15) 870 #define MDIO_CFG_SPEED(x) (((x) & 0x3) << 13) 871 #define MDIO_CFG_SPEED_1000M 2 872 #define MDIO_CFG_SPEED_100M 1 873 #define MDIO_CFG_SPEED_10M 0 874 #define MDIO_CFG_FULL_DUPLEX __BIT(12) 875 #define MDIO_CFG_FC_TX __BIT(11) 876 #define MDIO_CFG_FC_RX __BIT(10) 877 #define MDIO_CFG_LINK_DOWN __BIT(9) 878 #define MDIO_CFG_AUTO_DONE __BIT(8) 879 #define MDIO_CFG_MDC_CLKDIV(x) (((x) & 0x3) << 6) 880 #define MDIO_CFG_MDC_512KHZ 3 881 #define MDIO_CFG_MDC_1MHZ 2 882 #define MDIO_CFG_MDC_2MHZ 1 883 #define MDIO_CFG_MDC_4MHZ 0 884 #define MDIO_CFG_TURBO_50MHZ __BIT(5) 885 #define MDIO_CFG_TURBO_EN __BIT(4) 886 #define MDIO_CFG_RX_CLK_SKEW (((x) & 0x3) << 2) 887 #define MDIO_CFG_RX_SKEW_INV 3 888 #define MDIO_CFG_RX_SKEW_400PS 2 889 #define MDIO_CFG_RX_SKEW_200PS 1 890 #define MDIO_CFG_RX_SKEW_ZERO 0 891 #define MDIO_CFG_TX_CLK_MODE(x) (((x) & 0x1) << 0) 892 #define MDIO_CFG_TX_CLK_MODE_3COM 1 893 #define MDIO_CFG_TX_CLK_MODE_HP 0 894 #define FE_GLOBAL_CFG_EXT_VLAN(x) (((x) & 0xffff) << 16) 895 #define FE_GLOBAL_CFG_US_CLK(x) (((x) & 0xff) << 8) 896 #define FE_GLOBAL_CFG_L2_SPACE(x) (((x) & 0xf) << 4) 897 #define FE_GLOBAL_RESET_PSE __BIT(0) 898 #define FE_INT_PPE_COUNT_HIGH __BIT(31) 899 #define FE_INT_DMA_COUNT_HIGH __BIT(29) 900 #define FE_INT_PSE_P2_FC_ASSERT __BIT(26) 901 #define FE_INT_PSE_FC_DROP __BIT(24) 902 #define FE_INT_GDMA_DROP_OTHER __BIT(23) 903 #define FE_INT_PSE_P1_FC_ASSERT __BIT(22) 904 #define FE_INT_PSE_P0_FC_ASSERT __BIT(21) 905 #define FE_INT_PSE_FQ_EMPTY __BIT(20) 906 #define FE_INT_TX_COHERENT __BIT(17) 907 #define FE_INT_RX_COHERENT __BIT(16) 908 #define FE_INT_TX3 __BIT(11) 909 #define FE_INT_TX2 __BIT(10) 910 #define FE_INT_TX1 __BIT(9) 911 #define FE_INT_TX0 __BIT(8) 912 #define FE_INT_RX __BIT(2) 913 #define FE_INT_TX_DELAY __BIT(1) 914 #define FE_INT_RX_DELAY __BIT(0) 915 #define FE_GDMA_FWD_CFG_JUMBO_LEN(x) (((x) & 0xf) << 28) 916 #define FE_GDMA_FWD_CFG_DROP_256B __BIT(23) 917 #define FE_GDMA_FWD_CFG_IP4_CRC_EN __BIT(22) 918 #define FE_GDMA_FWD_CFG_TCP_CRC_EN __BIT(21) 919 #define FE_GDMA_FWD_CFG_UDP_CRC_EN __BIT(20) 920 #define FE_GDMA_FWD_CFG_JUMBO_EN __BIT(19) 921 #define FE_GDMA_FWD_CFG_DIS_TX_PAD __BIT(18) 922 #define FE_GDMA_FWD_CFG_DIS_TX_CRC __BIT(17) 923 #define FE_GDMA_FWD_CFG_STRIP_RX_CRC __BIT(16) 924 #define FE_GDMA_FWD_CFG_UNICA_PORT(x) (((x) & 0x3) << 12) 925 #define FE_GDMA_FWD_CFG_BROAD_PORT(x) (((x) & 0x3) << 8) 926 #define FE_GDMA_FWD_CFG_MULTI_PORT(x) (((x) & 0x3) << 6) 927 #define FE_GDMA_FWD_CFG_OTHER_PORT(x) (((x) & 0x3) << 0) 928 #define FE_GDMA_FWD_CFG_PORT_DROP 7 929 #define FE_GDMA_FWD_CFG_PORT_PPE 6 930 #define FE_GDMA_FWD_CFG_PORT_GDMA2 2 931 #define FE_GDMA_FWD_CFG_PORT_GDMA1 1 932 #define FE_GDMA_FWD_CFG_PORT_CPU 0 933 #define FE_PSE_FQ_MAX_COUNT(x) (((x) & 0xff) << 24) 934 #define FE_PSE_FQ_FC_RELEASE(x) (((x) & 0xff) << 16) 935 #define FE_PSE_FQ_FC_ASSERT(x) (((x) & 0xff) << 8) 936 #define FE_PSE_FQ_FC_DROP(x) (((x) & 0xff) << 0) 937 #define FE_CDMA_CSG_CFG_VLAN_TAG(x) (((x) & 0xffff) << 16) 938 #define FE_CDMA_CSG_CFG_IP4_CRC_EN __BIT(2) 939 #define FE_CDMA_CSG_CFG_UDP_CRC_EN __BIT(1) 940 #define FE_CDMA_CSG_CFG_TCP_CRC_EN __BIT(0) 941 #define FE_PDMA_GLOBAL_CFG_HDR_SEG_LEN __BIT(16) 942 #define FE_PDMA_GLOBAL_CFG_TX_WB_DDONE __BIT(6) 943 #define FE_PDMA_GLOBAL_CFG_BURST_SZ(x) (((x) & 0x3) << 4) 944 #define FE_PDMA_GLOBAL_CFG_BURST_SZ_4 (0 << 4) 945 #define FE_PDMA_GLOBAL_CFG_BURST_SZ_8 __BIT(4) 946 #define FE_PDMA_GLOBAL_CFG_BURST_SZ_16 (2 << 4) 947 #define FE_PDMA_GLOBAL_CFG_RX_DMA_BUSY __BIT(3) 948 #define FE_PDMA_GLOBAL_CFG_RX_DMA_EN __BIT(2) 949 #define FE_PDMA_GLOBAL_CFG_TX_DMA_BUSY __BIT(1) 950 #define FE_PDMA_GLOBAL_CFG_TX_DMA_EN __BIT(0) 951 #define PDMA_RST_RX0 __BIT(16) 952 #define PDMA_RST_TX3 __BIT(3) 953 #define PDMA_RST_TX2 __BIT(2) 954 #define PDMA_RST_TX1 __BIT(1) 955 #define PDMA_RST_TX0 __BIT(0) 956 957 /* 958 * 10/100 Switch registers 959 */ 960 #define RA_ETH_SW_ISR 0x00 961 #define RA_ETH_SW_IMR 0x04 962 #define RA_ETH_SW_FCT0 0x08 963 #define RA_ETH_SW_FCT0_FC_RLS_TH(x) (((x) & 0xff) << 24) 964 #define RA_ETH_SW_FCT0_FC_SET_TH(x) (((x) & 0xff) << 16) 965 #define RA_ETH_SW_FCT0_DROP_RLS_TH(x) (((x) & 0xff) << 8) 966 #define RA_ETH_SW_FCT0_DROP_SET_TH(x) (((x) & 0xff) << 0) 967 #define RA_ETH_SW_FCT1 0x0C 968 #define RA_ETH_SW_FCT1_PORT_TH(x) (((x) & 0xff) << 0) 969 #define RA_ETH_SW_PFC0 0x10 970 #define RA_ETH_SW_PFC1 0x14 971 #define RA_ETH_SW_PFC2 0x18 972 #define RA_ETH_SW_QCS0 0x1C 973 #define RA_ETH_SW_QCS1 0x20 974 #define RA_ETH_SW_ATS 0x24 975 #define RA_ETH_SW_ATS0 0x28 976 #define RA_ETH_SW_ATS1 0x2C 977 #define RA_ETH_SW_ATS2 0x30 978 #define RA_ETH_SW_WMAD0 0x34 979 #define RA_ETH_SW_WMAD1 0x38 980 #define RA_ETH_SW_WMAD2 0x3C 981 #define RA_ETH_SW_PVIDC0 0x40 982 #define RA_ETH_SW_PVIDC1 0x44 983 #define RA_ETH_SW_PVIDC2 0x48 984 #define RA_ETH_SW_PVIDC3 0x4C 985 #define RA_ETH_SW_VLANI0 0x50 986 #define RA_ETH_SW_VLANI1 0x54 987 #define RA_ETH_SW_VLANI2 0x58 988 #define RA_ETH_SW_VLANI3 0x5C 989 #define RA_ETH_SW_VLANI4 0x60 990 #define RA_ETH_SW_VLANI5 0x64 991 #define RA_ETH_SW_VLANI6 0x68 992 #define RA_ETH_SW_VLANI7 0x6C 993 #define RA_ETH_SW_VMSC0 0x70 994 #define RA_ETH_SW_VMSC1 0x74 995 #define RA_ETH_SW_VMSC2 0x78 996 #define RA_ETH_SW_VMSC3 0x7C 997 #define RA_ETH_SW_POA 0x80 998 #define RA_ETH_SW_FPA 0x84 999 #define RA_ETH_SW_PTS 0x88 1000 #define RA_ETH_SW_SOCPC 0x8C 1001 #define RA_ETH_SW_POC0 0x90 1002 #define RA_ETH_SW_POC1 0x94 1003 #define RA_ETH_SW_POC2 0x98 1004 #define RA_ETH_SW_SWGC 0x9C 1005 #define RA_ETH_SW_RST 0xA0 1006 #define RA_ETH_SW_LEDP0 0xA4 1007 #define RA_ETH_SW_LEDP1 0xA8 1008 #define RA_ETH_SW_LEDP2 0xAC 1009 #define RA_ETH_SW_LEDP3 0xB0 1010 #define RA_ETH_SW_LEDP4 0xB4 1011 #define RA_ETH_SW_WDOG 0xB8 1012 #define RA_ETH_SW_DBG 0xBC 1013 #define RA_ETH_SW_PCTL0 0xC0 /* PCR0 */ 1014 #define RA_ETH_SW_PCTL1 0xC4 /* PCR1 */ 1015 #define RA_ETH_SW_FPORT 0xC8 1016 #define RA_ETH_SW_FTC2 0xCC 1017 #define RA_ETH_SW_QSS0 0xD0 1018 #define RA_ETH_SW_QSS1 0xD4 1019 #define RA_ETH_SW_DBGC 0xD8 1020 #define RA_ETH_SW_MTI1 0xDC 1021 #define RA_ETH_SW_PPC 0xE0 1022 #define RA_ETH_SW_SGC2 0xE4 1023 #define RA_ETH_SW_PCNT0 0xE8 1024 #define RA_ETH_SW_PCNT1 0xEC 1025 #define RA_ETH_SW_PCNT2 0xF0 1026 #define RA_ETH_SW_PCNT3 0xF4 1027 #define RA_ETH_SW_PCNT4 0xF8 1028 #define RA_ETH_SW_PCNT5 0xFC 1029 1030 #define ISR_WDOG1_EXPIRED __BIT(29) 1031 #define ISR_WDOG0_EXPIRED __BIT(28) 1032 #define ISR_HAS_INTRUDER __BIT(27) 1033 #define ISR_PORT_STS_CHNG __BIT(26) 1034 #define ISR_BRDCAST_STORM __BIT(25) 1035 #define ISR_MUST_DROP_LAN __BIT(24) 1036 #define ISR_GLOB_QUE_FULL __BIT(23) 1037 #define ISR_LAN_QUE6_FULL __BIT(20) 1038 #define ISR_LAN_QUE5_FULL __BIT(19) 1039 #define ISR_LAN_QUE4_FULL __BIT(18) 1040 #define ISR_LAN_QUE3_FULL __BIT(17) 1041 #define ISR_LAN_QUE2_FULL __BIT(16) 1042 #define ISR_LAN_QUE1_FULL __BIT(15) 1043 #define ISR_LAN_QUE0_FULL __BIT(14) 1044 #define FTC0_REL_THR 24 1045 #define FTC0_SET_THR 16 1046 #define FTC0_DROP_REL_THR 8 1047 #define FTC0_DROP_SET_THR 0 1048 #define FTC1_PER_PORT_THR 0 1049 #define PCTL0_WR_VAL(x) (((x) & 0xffff) << 16) 1050 #define PCTL0_RD_CMD __BIT(14) 1051 #define PCTL0_WR_CMD __BIT(13) 1052 #define PCTL0_REG(x) (((x) & 0x1f) << 8) 1053 #define PCTL0_ADDR(x) (((x) & 0x1f) << 0) 1054 #define PCTL1_RD_VAL(x) (((x) >> 16) & 0xffff) 1055 #define PCTL1_RD_DONE __BIT(1) /* read clear */ 1056 #define PCTL1_WR_DONE __BIT(0) /* read clear */ 1057 #define SGC2_WL_FC_EN __BIT(30) 1058 #define SGC2_PORT5_IS_LAN __BIT(29) 1059 #define SGC2_PORT4_IS_LAN __BIT(28) 1060 #define SGC2_PORT3_IS_LAN __BIT(27) 1061 #define SGC2_PORT2_IS_LAN __BIT(26) 1062 #define SGC2_PORT1_IS_LAN __BIT(25) 1063 #define SGC2_PORT0_IS_LAN __BIT(24) 1064 #define SGC2_TX_CPU_TPID(x) ((x) << 16) 1065 #define SGC2_ARBITER_LAN_EN __BIT(11) 1066 #define SGC2_CPU_TPID_EN __BIT(10) 1067 #define SGC2_DBL_TAG_EN5 __BIT(5) 1068 #define SGC2_DBL_TAG_EN4 __BIT(4) 1069 #define SGC2_DBL_TAG_EN3 __BIT(3) 1070 #define SGC2_DBL_TAG_EN2 __BIT(2) 1071 #define SGC2_DBL_TAG_EN1 __BIT(1) 1072 #define SGC2_DBL_TAG_EN0 __BIT(0) 1073 1074 1075 #define FTC_THR_MSK 0xff 1076 1077 #define PFC0_MTCC_LIMIT 24 1078 #define PFC0_TURN_OFF_CF 16 1079 #define PFC0_TURN_OFF_CF_MSK 0xff 1080 #define PFC0_VO_NUM 12 1081 #define PFC0_CL_NUM 8 1082 #define PFC0_BE_NUM 4 1083 #define PFC0_BK_NUM 0 1084 #define PFC0_NUM_MSK 0xf 1085 1086 #define PFC1_P6_Q1_EN __BIT(31) 1087 #define PFC1_P6_TOS_EN __BIT(30) 1088 #define PFC1_P5_TOS_EN __BIT(29) 1089 #define PFC1_P4_TOS_EN __BIT(28) 1090 #define PFC1_P3_TOS_EN __BIT(27) 1091 1092 #define PFC1_P1_TOS_EN __BIT(25) 1093 #define PFC1_P0_TOS_EN __BIT(24) 1094 #define PFC1_PORT_PRI6 12 1095 #define PFC1_PORT_PRI5 10 1096 #define PFC1_PORT_PRI4 8 1097 #define PFC1_PORT_PRI3 6 1098 #define PFC1_PORT_PRI2 4 1099 #define PFC1_PORT_PRI1 2 1100 #define PFC1_PORT_PRI0 0 1101 #define PFC1_PORT_MSK 0x3 1102 1103 #define PFC2_PRI_THR_VO 24 1104 #define PFC2_PRI_THR_CL 16 1105 #define PFC2_PRI_THR_BE 8 1106 #define PFC2_PRI_THR_BK 0 1107 #define PFC2_PRI_THR_MSK 0xff 1108 1109 #define GQC0_EMPTY_BLOCKS 0 1110 #define GQC0_EMPTY_BLOCKS_MSK 0xff 1111 1112 /* 1113 * USB OTG Registers 1114 */ 1115 #define RA_USB_OTG_OTG_CNTRL 0x000 1116 #define RA_USB_OTG_OTG_INT 0x004 1117 #define RA_USB_OTG_AHB_CFG 0x008 1118 #define RA_USB_OTG_CFG 0x00C 1119 #define RA_USB_OTG_RESET 0x010 1120 #define RA_USB_OTG_INT 0x014 1121 #define RA_USB_OTG_INT_MASK 0x018 1122 #define RA_USB_OTG_RX_STAT 0x01C 1123 #define RA_USB_OTG_RX_POP_STAT 0x020 1124 #define RA_USB_OTG_RX_FIFO_SZ 0x024 1125 #define RA_USB_OTG_TX_FIFO_SZ 0x028 1126 #define RA_USB_OTG_TX_FIFO_STAT 0x02C 1127 #define RA_USB_OTG_I2C_ACCESS 0x030 1128 #define RA_USB_OTG_PHY_CTL 0x034 1129 #define RA_USB_OTG_GPIO 0x038 1130 #define RA_USB_OTG_GUID 0x03C 1131 #define RA_USB_OTG_SNPSID 0x040 1132 #define RA_USB_OTG_HWCFG1 0x044 1133 #define RA_USB_OTG_HWCFG2 0x048 1134 #define RA_USB_OTG_HWCFG3 0x04C 1135 #define RA_USB_OTG_HWCFG4 0x050 1136 #define RA_USB_OTG_HC_TX_FIFO_SZ 0x100 1137 #define RA_USB_OTG_DV_TX_FIFO_SZ 0x104 1138 #define RA_USB_OTG_HC_CFG 0x400 1139 #define RA_USB_OTG_HC_FRM_INTRVL 0x404 1140 #define RA_USB_OTG_HC_FRM_NUM 0x408 1141 #define RA_USB_OTG_HC_TX_STAT 0x410 1142 #define RA_USB_OTG_HC_INT 0x414 1143 #define RA_USB_OTG_HC_INT_MASK 0x418 1144 #define RA_USB_OTG_HC_PORT 0x440 1145 #define RA_USB_OTG_HC_CH_CFG 0x500 1146 #define RA_USB_OTG_HC_CH_SPLT 0x504 1147 #define RA_USB_OTG_HC_CH_INT 0x508 1148 #define RA_USB_OTG_HC_CH_INT_MASK 0x50C 1149 #define RA_USB_OTG_HC_CH_XFER 0x510 1150 #define RA_USB_OTG_HC_CH_DMA_ADDR 0x514 1151 #define RA_USB_OTG_DV_CFG 0x800 1152 #define RA_USB_OTG_DV_CTL 0x804 1153 #define RA_USB_OTG_DV_STAT 0x808 1154 #define RA_USB_OTG_DV_IN_INT_MASK 0x810 1155 #define RA_USB_OTG_DV_OUT_INT_MASK 0x814 1156 #define RA_USB_OTG_DV_ALL_INT 0x818 1157 #define RA_USB_OTG_DV_EP_INT_MASK 0x81c 1158 #define RA_USB_OTG_DV_IN_SEQ_RQ1 0x820 1159 #define RA_USB_OTG_DV_IN_SEQ_RQ2 0x824 1160 #define RA_USB_OTG_DV_IN_SEQ_RQ3 0x830 1161 #define RA_USB_OTG_DV_IN_SEQ_RQ4 0x834 1162 #define RA_USB_OTG_DV_VBUS_DISCH 0x828 1163 #define RA_USB_OTG_DV_VBUS_PULSE 0x82c 1164 #define RA_USB_OTG_DV_THRESH_CTL 0x830 1165 #define RA_USB_OTG_DV_IN_FIFO_INT 0x834 1166 #define RA_USB_OTG_DV_IN0_CTL 0x900 1167 1168 #define OTG_OTG_CNTRL_B_SESS_VALID __BIT(19) 1169 #define OTG_OTG_CNTRL_A_SESS_VALID __BIT(18) 1170 #define OTG_OTG_CNTRL_DEBOUNCE_SHORT __BIT(17) 1171 #define OTG_OTG_CNTRL_CONNID_STATUS __BIT(16) 1172 #define OTG_OTG_CNTRL_DV_HNP_EN __BIT(11) 1173 #define OTG_OTG_CNTRL_HC_SET_HNP_EN __BIT(10) 1174 #define OTG_OTG_CNTRL_HNP_REQ __BIT(9) 1175 #define OTG_OTG_CNTRL_HNP_SUCCESS __BIT(8) 1176 #define OTG_OTG_CNTRL_SESS_REQ __BIT(1) 1177 #define OTG_OTG_CNTRL_SESS_REQ_SUCCESS __BIT(0) 1178 #define OTG_OTG_INT_DEBOUNCE_DONE __BIT(19) 1179 #define OTG_OTG_INT_ADEV_TIMEOUT __BIT(18) 1180 #define OTG_OTG_INT_HOST_NEG_DETECT __BIT(17) 1181 #define OTG_OTG_INT_HOST_NEG_STATUS __BIT(9) 1182 #define OTG_OTG_INT_SESSION_REQ_STATUS __BIT(8) 1183 #define OTG_OTG_INT_SESSION_END_STATUS __BIT(2) 1184 #define OTG_AHB_CFG_TX_PFIFO_EMPTY_INT_EN __BIT(8) 1185 #define OTG_AHB_CFG_TX_NPFIFO_EMPTY_INT_EN __BIT(7) 1186 #define OTG_AHB_CFG_DMA_EN __BIT(5) 1187 #define OTG_AHB_CFG_BURST(x) (((x) & 0xf) << 1) 1188 #define OTG_AHB_CFG_BURST_SINGLE 0 1189 #define OTG_AHB_CFG_BURST_INCR 1 1190 #define OTG_AHB_CFG_BURST_INCR4 3 1191 #define OTG_AHB_CFG_BURST_INCR8 5 1192 #define OTG_AHB_CFG_BURST_INCR16 7 1193 #define OTG_AHB_CFG_GLOBAL_INT_EN __BIT(0) 1194 #define OTG_CFG_CORRUPT_TX __BIT(31) 1195 #define OTG_CFG_FORCE_DEVICE __BIT(30) 1196 #define OTG_CFG_FORCE_HOST __BIT(29) 1197 #define OTG_CFG_ULPI_EXT_VBUS_IND_SEL __BIT(22) 1198 #define OTG_CFG_ULPI_EXT_VBUS_IND __BIT(21) 1199 #define OTG_CFG_ULPI_EXT_VBUS_DRV __BIT(20) 1200 #define OTG_CFG_ULPI_CLOCK_SUSPEND __BIT(19) 1201 #define OTG_CFG_ULPI_AUTO_RESUME __BIT(18) 1202 #define OTG_CFG_ULPI_FS_LS_SEL __BIT(17) 1203 #define OTG_CFG_UTMI_I2C_SEL __BIT(16) 1204 #define OTG_CFG_TURNAROUND_TIME(x) (((x) & 0xf) << 10) 1205 #define OTG_CFG_HNP_CAP __BIT(9) 1206 #define OTG_CFG_SRP_CAP __BIT(8) 1207 #define OTG_CFG_ULPI_DDR_SEL __BIT(7) 1208 #define OTG_CFG_HS_PHY_SEL __BIT(6) 1209 #define OTG_CFG_FS_IF_SEL __BIT(5) 1210 #define OTG_CFG_ULPI_UTMI_SEL __BIT(4) 1211 #define OTG_CFG_PHY_IF __BIT(3) 1212 #define OTG_CFG_TIMEOUT(x) (((x) & 0x7) << 0) 1213 #define OTG_RST_AHB_IDLE __BIT(31) 1214 #define OTG_RST_DMA_ACTIVE __BIT(30) 1215 #define OTG_RST_TXQ_TO_FLUSH(x) (((x) & 0x1f) << 6) 1216 #define OTG_RST_TXQ_FLUSH_ALL 0x10 1217 #define OTG_RST_TXQ_FLUSH __BIT(5) 1218 #define OTG_RST_RXQ_FLUSH __BIT(4) 1219 #define OTG_RST_INQ_FLUSH __BIT(3) 1220 #define OTG_RST_HC_FRAME __BIT(2) 1221 #define OTG_RST_AHB __BIT(1) 1222 #define OTG_RST_CORE __BIT(0) 1223 #define OTG_INT_RESUME __BIT(31) 1224 #define OTG_INT_SESSION_REQ __BIT(30) 1225 #define OTG_INT_DISCONNECT __BIT(29) 1226 #define OTG_INT_CONNID_STATUS __BIT(28) 1227 #define OTG_INT_PTX_EMPTY __BIT(26) 1228 #define OTG_INT_HOST_CHANNEL __BIT(25) 1229 #define OTG_INT_PORT_STATUS __BIT(24) 1230 #define OTG_INT_DMA_FETCH_SUSPEND __BIT(22) 1231 #define OTG_INT_INCOMPLETE_PERIODIC __BIT(21) 1232 #define OTG_INT_INCOMPLETE_ISOC __BIT(20) 1233 #define OTG_INT_DV_OUT_EP __BIT(19) 1234 #define OTG_INT_DV_IN_EP __BIT(18) 1235 #define OTG_INT_DV_EP_MISMATCH __BIT(17) 1236 #define OTG_INT_DV_PERIODIC_END __BIT(15) 1237 #define OTG_INT_DV_ISOC_OUT_DROP __BIT(14) 1238 #define OTG_INT_DV_ENUM_COMPLETE __BIT(13) 1239 #define OTG_INT_DV_USB_RESET __BIT(12) 1240 #define OTG_INT_DV_USB_SUSPEND __BIT(11) 1241 #define OTG_INT_DV_USB_EARLY_SUSPEND __BIT(10) 1242 #define OTG_INT_I2C __BIT(9) 1243 #define OTG_INT_ULPI_CARKIT __BIT(8) 1244 #define OTG_INT_DV_OUT_NAK_EFFECTIVE __BIT(7) 1245 #define OTG_INT_DV_IN_NAK_EFFECTIVE __BIT(6) 1246 #define OTG_INT_NPTX_EMPTY __BIT(5) 1247 #define OTG_INT_RX_FIFO __BIT(4) 1248 #define OTG_INT_SOF __BIT(3) 1249 #define OTG_INT_OTG __BIT(2) 1250 #define OTG_INT_MODE_MISMATCH __BIT(1) 1251 #define OTG_INT_MODE __BIT(0) 1252 #define USB_OTG_SNPSID_CORE_REV_2_00 0x4F542000 1253 #define OTG_HC_CFG_FORCE_NO_HS __BIT(2) 1254 #define OTG_HC_CFG_FSLS_CLK_SEL(x) (((x) & 0x3) << 0) 1255 #define OTG_HC_CFG_FS_CLK_3060 0 1256 #define OTG_HC_CFG_FS_CLK_48 1 1257 #define OTG_HC_CFG_LS_CLK_3060 0 1258 #define OTG_HC_CFG_LS_CLK_48 1 1259 #define OTG_HC_CFG_LS_CLK_6 2 1260 #define USB_OTG_HC_FRM_NUM(x) (x & 0x3fff) 1261 #define USB_OTG_HC_FRM_REM(x) (x >> 16) 1262 #define USB_OTG_HC_PORT_SPEED(x) (((x) >> 17) & 0x3) 1263 #define USB_OTG_HC_PORT_SPEED_HS 0 1264 #define USB_OTG_HC_PORT_SPEED_FS 1 1265 #define USB_OTG_HC_PORT_SPEED_LS 2 1266 #define USB_OTG_HC_PORT_TEST(x) (((x) & 0xf) << 13) 1267 #define USB_OTG_HC_PORT_TEST_DISABLED 0 1268 #define USB_OTG_HC_PORT_TEST_J_MODE 1 1269 #define USB_OTG_HC_PORT_TEST_K_MODE 2 1270 #define USB_OTG_HC_PORT_TEST_NAK_MODE 3 1271 #define USB_OTG_HC_PORT_TEST_PKT_MODE 4 1272 #define USB_OTG_HC_PORT_TEST_FORCE_MODE 5 1273 #define USB_OTG_HC_PORT_POWER __BIT(12) 1274 #define USB_OTG_HC_PORT_LINE_STAT (((x) >> 10) & 0x3) 1275 #define USB_OTG_HC_PORT_LINE_STAT_DP 1 1276 #define USB_OTG_HC_PORT_LINE_STAT_DM 3 1277 #define USB_OTG_HC_PORT_RESET __BIT(8) 1278 #define USB_OTG_HC_PORT_SUSPEND __BIT(7) 1279 #define USB_OTG_HC_PORT_RESUME __BIT(6) 1280 #define USB_OTG_HC_PORT_OVCURR_CHANGE __BIT(5) 1281 #define USB_OTG_HC_PORT_OVCURR __BIT(4) 1282 #define USB_OTG_HC_PORT_ENABLE_CHANGE __BIT(3) 1283 #define USB_OTG_HC_PORT_ENABLE __BIT(2) 1284 #define USB_OTG_HC_PORT_CONNECT_CHANGE __BIT(1) 1285 #define USB_OTG_HC_PORT_STATUS __BIT(0) 1286 #define USB_OTG_HC_CH_CFG_ENABLE __BIT(31) 1287 #define USB_OTG_HC_CH_CFG_DISABLE __BIT(30) 1288 #define USB_OTG_HC_CH_CFG_ODD_FRAME __BIT(29) 1289 #define USB_OTG_HC_CH_CFG_DEV_ADDR(x) (((x) & 0x7f) << 22) 1290 #define USB_OTG_HC_CH_CFG_MULTI_CNT(x) (((x) & 0x3) << 20) 1291 #define USB_OTG_HC_CH_CFG_EP_TYPE(x) (((x) & 0x3) << 18) 1292 #define USB_OTG_HC_CH_CFG_EP_TYPE_CTRL 0 1293 #define USB_OTG_HC_CH_CFG_EP_TYPE_ISOC 1 1294 #define USB_OTG_HC_CH_CFG_EP_TYPE_BULK 2 1295 #define USB_OTG_HC_CH_CFG_EP_TYPE_INTR 3 1296 #define USB_OTG_HC_CH_CFG_LS __BIT(17) 1297 #define USB_OTG_HC_CH_CFG_EP_DIR(x) (((x) & 0x1) << 15) 1298 #define USB_OTG_HC_CH_CFG_EP_DIR_OUT 0 1299 #define USB_OTG_HC_CH_CFG_EP_DIR_IN 1 1300 #define USB_OTG_HC_CH_CFG_EP_NUM(x) (((x) & 0xf) << 11) 1301 #define USB_OTG_HC_CH_CFG_MAX_PKT_SZ(x) (((x) & 0x7ff) << 0) 1302 #define USB_OTG_HC_CH_SPLT_EN __BIT(31) 1303 #define USB_OTG_HC_CH_SPLT_COMPLETE __BIT(16) 1304 #define USB_OTG_HC_CH_SPLT_POS(x) (((x) & 0x3) << 14) 1305 #define USB_OTG_HC_CH_SPLT_POS_MID 0 1306 #define USB_OTG_HC_CH_SPLT_POS_END 1 1307 #define USB_OTG_HC_CH_SPLT_POS_BEGIN 2 1308 #define USB_OTG_HC_CH_SPLT_POS_ALL 3 1309 #define USB_OTG_HC_CH_SPLT_HUB_ADDR(x) (((x) & 0x7f) << 7) 1310 #define USB_OTG_HC_CH_SPLT_PORT_ADDR(x) (((x) & 0x7f) << 0) 1311 #define USB_OTG_HC_CH_INT_ALL 0x7ff 1312 #define USB_OTG_HC_CH_INT_TOGGLE_ERROR __BIT(10) 1313 #define USB_OTG_HC_CH_INT_FRAME_OVERRUN __BIT(9) 1314 #define USB_OTG_HC_CH_INT_BABBLE_ERROR __BIT(8) 1315 #define USB_OTG_HC_CH_INT_XACT_ERROR __BIT(7) 1316 #define USB_OTG_HC_CH_INT_NYET __BIT(6) 1317 #define USB_OTG_HC_CH_INT_ACK __BIT(5) 1318 #define USB_OTG_HC_CH_INT_NAK __BIT(4) 1319 #define USB_OTG_HC_CH_INT_STALL __BIT(3) 1320 #define USB_OTG_HC_CH_INT_DMA_ERROR __BIT(2) 1321 #define USB_OTG_HC_CH_INT_HALTED __BIT(1) 1322 #define USB_OTG_HC_CH_INT_XFER_COMPLETE __BIT(0) 1323 #define USB_OTG_HC_CH_XFER_DO_PING __BIT(31) 1324 #define USB_OTG_HC_CH_WR_XFER_PID(x) (((x) & 0x3) << 29) 1325 #define USB_OTG_HC_CH_RD_XFER_PID(x) (((x) >> 29) & 0x3) 1326 #define USB_OTG_HC_CH_XFER_PID_DATA0 0 1327 #define USB_OTG_HC_CH_XFER_PID_DATA2 1 1328 #define USB_OTG_HC_CH_XFER_PID_DATA1 2 1329 #define USB_OTG_HC_CH_XFER_PID_SETUP 3 1330 #define USB_OTG_HC_CH_XFER_PID_MDATA 3 1331 #define USB_OTG_HC_CH_XFER_SET_PKT_CNT(x) (((x) & 0x3ff) << 19) 1332 #define USB_OTG_HC_CH_XFER_SET_BYTES(x) ((x) & 0x7ffff) 1333 #define USB_OTG_HC_CH_XFER_GET_PKT_CNT(x) (((x) >> 19) & 0x3ff) 1334 #define USB_OTG_HC_CH_XFER_GET_BYTES(x) ((x) & 0x7ffff) 1335 1336 /* PCIe Registers - 0x10140000 */ 1337 #define RA_PCI_PCICFG 0x0000 1338 #define PCICFG_P2P_BR_DEVNUM1 __BITS(23,20) 1339 #define PCICFG_P2P_BR_DEVNUM0 __BITS(19,16) 1340 #define PCICFG_PSIRST __BIT(1) 1341 #define RA_PCI_PCIINT 0x0008 1342 #define PCIINT_INT3 __BIT(21) /* PCIe1 interrupt */ 1343 #define PCIINT_INT2 __BIT(20) /* PCIe0 interrupt */ 1344 #define PCIINT_INT1 __BIT(19) 1345 #define PCIINT_INT0 __BIT(18) 1346 #define RA_PCI_PCIENA 0x000c 1347 #define RA_PCI_CFGADDR 0x0020 1348 #define CFGADDR_EXTREG __BITS(27,24) 1349 #define CFGADDR_BUS __BITS(23,16) 1350 #define CFGADDR_DEV __BITS(15,11) 1351 #define CFGADDR_FUN __BITS(10,8) 1352 #define CFGADDR_REG __BITS(7,0) 1353 #define RA_PCI_CFGDATA 0x0024 1354 #define RA_PCI_MEMBASE 0x0028 1355 #define MEMBASE_ADDR __BITS(31,16) 1356 #define RA_PCI_IOBASE 0x002c 1357 #define IOBASE_ADDR __BITS(31,16) 1358 #define RA_PCI_PHY0CFG 0x0090 1359 #define PHY0CFG_SPI_BUSY __BIT(31) 1360 #define PHY0CFG_SPI_WR __BIT(23) 1361 #define PHY0CFG_SPI_ADDR __BITS(15,8) 1362 #define PHY0CFG_SPI_DATA __BITS(7,0) 1363 1364 /* PCIe0 RC Control Registers - 0x10142000 */ 1365 #define RA_PCIE0_BAR0SETUP 0x0010 1366 #define BARSETUP_BARMSK __BITS(31,16) 1367 #define BARSETUP_BARENB __BIT(0) 1368 #define RA_PCIE0_BAR1SETUP 0x0014 1369 #define RA_PCIE0_IMBASEBAR0 0x0018 1370 #define IMBASEBAR0 __BITS(31,16) 1371 #define RA_PCIE0_ID 0x0010 1372 #define RA_PCIE0_CLASS 0x0014 1373 #define RA_PCIE0_SUBID 0x0018 1374 #define RA_PCIE0_STATUS 0x0018 1375 #define PCIE_STATUS_LINK_UP __BIT(0) 1376 1377 #endif /* _RALINK_REG_H_ */ 1378
Indexes created Wed Oct 01 15:09:59 GMT 2025