ralink_reg.h revision 1.3.6.1
1 /* $NetBSD: ralink_reg.h,v 1.3.6.1 2012/02/18 07:32:41 mrg Exp $ */ 2 /*- 3 * Copyright (c) 2011 CradlePoint Technology, Inc. 4 * All rights reserved. 5 * 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY CRADLEPOINT TECHNOLOGY, INC. AND CONTRIBUTORS 17 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 18 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 19 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS 20 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 21 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 22 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 23 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 24 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 25 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 26 * POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 /* 30 * This file contains the configuration parameters for the RT3052 board. 31 */ 32 33 #ifndef _RALINK_REG_H_ 34 #define _RALINK_REG_H_ 35 36 #include <mips/cpuregs.h> 37 38 #if defined(RT3050) 39 #define RA_CLOCK_RATE 320000000 40 #define RA_BUS_FREQ (RA_CLOCK_RATE / 3) 41 #define RA_UART_FREQ RA_BUS_FREQ 42 #elif defined(RT3052) 43 #define RA_CLOCK_RATE 384000000 44 #define RA_BUS_FREQ (RA_CLOCK_RATE / 3) 45 #define RA_UART_FREQ RA_BUS_FREQ 46 #elif defined(RT3883) 47 #if 0 48 #define RA_CLOCK_RATE 480000000 49 #else 50 #define RA_CLOCK_RATE 500000000 51 #endif 52 #define RA_BUS_FREQ 166000000 /* DDR speed */ 53 #define RA_UART_FREQ 40000000 54 #else 55 /* Ralink dev board */ 56 #define RA_CLOCK_RATE 384000000 57 #define RA_BUS_FREQ (RA_CLOCK_RATE / 3) 58 #define RA_UART_FREQ RA_BUS_FREQ 59 #endif 60 61 #define RA_BAUDRATE CONSPEED 62 #define RA_SERIAL_CLKDIV 16 63 64 #define RA_SRAM_BASE 0x00000000 65 #define RA_SRAM_END 0x0FFFFFFF 66 #define RA_SYSCTL_BASE 0x10000000 67 #define RA_TIMER_BASE 0x10000100 68 #define RA_INTCTL_BASE 0x10000200 69 #define RA_MEMCTL_BASE 0x10000300 70 #if defined(RT3052) || defined(RT3050) 71 #define RA_PCM_BASE 0x10000400 72 #endif 73 #define RA_UART_BASE 0x10000500 74 #define RA_PIO_BASE 0x10000600 75 #if defined(RT3052) || defined(RT3050) 76 #define RA_GDMA_BASE 0x10000700 77 #elif defined(RT3883) 78 #define RA_FLASHCTL_BASE 0x10000700 79 #endif 80 #define RA_NANDCTL_BASE 0x10000800 81 #define RA_I2C_BASE 0x10000900 82 #define RA_I2S_BASE 0x10000A00 83 #define RA_SPI_BASE 0x10000B00 84 #define RA_UART_LITE_BASE 0x10000C00 85 #if defined(RT3883) 86 #define RA_PCM_BASE 0x10002000 87 #define RA_GDMA_BASE 0x10002800 88 #define RA_CODEC1_BASE 0x10003000 89 #define RA_CODEC2_BASE 0x10003800 90 #endif 91 #define RA_FRAME_ENGINE_BASE 0x10100000 92 #define RA_ETH_SW_BASE 0x10110000 93 #define RA_ROM_BASE 0x10118000 94 #if defined(RT3883) 95 #define RA_USB_DEVICE_BASE 0x10120000 96 #define RA_PCI_BASE 0x10140000 97 #endif 98 #define RA_11N_MAC_BASE 0x10180000 99 #define RA_USB_OTG_BASE 0x101C0000 100 #if defined(RT3883) 101 #define RA_USB_HOST_BASE 0x101C0000 102 #endif 103 #if defined(RT3052) || defined(RT3050) 104 #define RA_FLASH_BASE 0x1F000000 105 #define RA_FLASH_END 0x1F7FFFFF 106 #elif defined(RT3883) 107 #define RA_FLASH_BASE 0x1C000000 108 #define RA_FLASH_END 0x1DFFFFFF 109 #endif 110 111 #define RA_IOREG_VADDR(base, offset) \ 112 (volatile uint32_t *)MIPS_PHYS_TO_KSEG1((base) + (offset)) 113 114 #define FLD_GET(val,pos,mask) (((val) >> (pos)) & (mask)) 115 #define FLD_SET(val,pos,mask) (((val) & (mask)) << (pos)) 116 117 /* 118 * System Control Registers 119 */ 120 #define RA_SYSCTL_ID0 0x00 121 #define RA_SYSCTL_ID1 0x04 122 #define RA_SYSCTL_CFG0 0x10 123 #define RA_SYSCTL_CFG1 0x14 124 #define RA_SYSCTL_CLKCFG0 0x2C 125 #define RA_SYSCTL_CLKCFG1 0x30 126 #define RA_SYSCTL_RST 0x34 127 #define RA_SYSCTL_RSTSTAT 0x38 128 #define RA_SYSCTL_GPIOMODE 0x60 129 130 #if defined(RT3050) || defined(RT3052) 131 #define SYSCTL_CFG0_INIC_EE_SDRAM __BIT(29) 132 #define SYSCTL_CFG0_INIC_8MB_SDRAM __BIT(28) 133 #define SYSCTL_CFG0_GE0_MODE __BITS(24,25) 134 #define SYSCTL_CFG0_BYPASS_PLL __BIT(21) 135 #define SYSCTL_CFG0_BE __BIT(20) 136 #define SYSCTL_CFG0_CPU_CLK_SEL __BIT(18) 137 #define SYSCTL_CFG0_BOOT_FROM __BITS(16,17) 138 #define SYSCTL_CFG0_TEST_CODE __BITS(8,15) 139 #define SYSCTL_CFG0_SRAM_CS_MODE __BITS(2,3) 140 #define SYSCTL_CFG0_SDRAM_CLK_DRV __BIT(0) 141 #else 142 #define SYSCTL_CFG0_BE __BIT(19) 143 #define SYSCTL_CFG0_DRAM_SIZE __BITS(12,14) 144 #define SYSCTL_CFG0_DRAM_2MB 0 145 #define SYSCTL_CFG0_DRAM_8MB 1 146 #define SYSCTL_CFG0_DRAM_16MB 2 147 #define SYSCTL_CFG0_DRAM_32MB 3 148 #define SYSCTL_CFG0_DRAM_64MB 4 149 #define SYSCTL_CFG0_DRAM_128MB 5 150 #define SYSCTL_CFG0_DRAM_256MB 6 151 #endif 152 153 #if defined(RT3883) 154 /* 3883 doesn't have memo regs, use teststat instead */ 155 #define RA_SYSCTL_MEMO0 0x18 156 #define RA_SYSCTL_MEMO1 0x1C 157 #else 158 #define RA_SYSCTL_MEMO0 0x68 159 #define RA_SYSCTL_MEMO1 0x6C 160 #endif 161 162 #define RST_SW (1 << 23) 163 #define RST_OTG (1 << 22) 164 #define RST_FE (1 << 21) 165 #define RST_WLAN (1 << 20) 166 #define RST_UARTL (1 << 19) 167 #define RST_SPI (1 << 18) 168 #define RST_I2S (1 << 17) 169 #define RST_I2C (1 << 16) 170 #define RST_NAND (1 << 15) 171 #define RST_DMA (1 << 14) 172 #define RST_PIO (1 << 13) 173 #define RST_UART (1 << 12) 174 #define RST_PCM (1 << 11) 175 #define RST_MC (1 << 10) 176 #define RST_INTC (1 << 9) 177 #define RST_TIMER (1 << 8) 178 #define RST_SYS (1 << 0) 179 #define GPIOMODE_RGMII (1 << 9) 180 #define GPIOMODE_SDRAM (1 << 8) 181 #define GPIOMODE_MDIO (1 << 7) 182 #define GPIOMODE_JTAG (1 << 6) 183 #define GPIOMODE_UARTL (1 << 5) 184 #define GPIOMODE_UARTF2 (1 << 4) 185 #define GPIOMODE_UARTF1 (1 << 3) 186 #define GPIOMODE_UARTF0 (1 << 2) 187 #define GPIOMODE_UARTF_0_2 \ 188 (GPIOMODE_UARTF0|GPIOMODE_UARTF1|GPIOMODE_UARTF2) 189 #define GPIOMODE_SPI (1 << 1) 190 #define GPIOMODE_I2C (1 << 0) 191 192 /* 193 * Timer Registers 194 */ 195 #define RA_TIMER_STAT 0x00 196 #define RA_TIMER_0_LOAD 0x10 197 #define RA_TIMER_0_VALUE 0x14 198 #define RA_TIMER_0_CNTRL 0x18 199 #define RA_TIMER_1_LOAD 0x20 200 #define RA_TIMER_1_VALUE 0x24 201 #define RA_TIMER_1_CNTRL 0x28 202 203 #define TIMER_1_RESET (1 << 5) 204 #define TIMER_0_RESET (1 << 4) 205 #define TIMER_1_INT_STATUS (1 << 1) 206 #define TIMER_0_INT_STATUS (1 << 0) 207 #define TIMER_TEST_EN (1 << 15) 208 #define TIMER_EN (1 << 7) 209 #define TIMER_MODE(x) (((x) & 0x3) << 4) 210 #define TIMER_MODE_FREE 0 211 #define TIMER_MODE_PERIODIC 1 212 #define TIMER_MODE_TIMEOUT 2 213 #define TIMER_MODE_WDOG 3 /* only valid for TIMER_1 */ 214 #define TIMER_PRESCALE(x) (((x) & 0xf) << 0) 215 #define TIMER_PRESCALE_DIV_1 0 216 #define TIMER_PRESCALE_DIV_4 1 217 #define TIMER_PRESCALE_DIV_8 2 218 #define TIMER_PRESCALE_DIV_16 3 219 #define TIMER_PRESCALE_DIV_32 4 220 #define TIMER_PRESCALE_DIV_64 5 221 #define TIMER_PRESCALE_DIV_128 6 222 #define TIMER_PRESCALE_DIV_256 7 223 #define TIMER_PRESCALE_DIV_512 8 224 #define TIMER_PRESCALE_DIV_1024 9 225 #define TIMER_PRESCALE_DIV_2048 10 226 #define TIMER_PRESCALE_DIV_4096 11 227 #define TIMER_PRESCALE_DIV_8192 12 228 #define TIMER_PRESCALE_DIV_16384 13 229 #define TIMER_PRESCALE_DIV_32768 14 230 #define TIMER_PRESCALE_DIV_65536 15 231 232 /* 233 * Interrupt Controller Registers 234 */ 235 #define RA_INTCTL_IRQ0STAT 0x00 236 #define RA_INTCTL_IRQ1STAT 0x04 237 #define RA_INTCTL_TYPE 0x20 238 #define RA_INTCTL_RAW 0x30 239 #define RA_INTCTL_ENABLE 0x34 240 #define RA_INTCTL_DISABLE 0x38 241 242 243 #define INT_GLOBAL (1 << 31) 244 #define INT_USB (1 << 18) 245 #define INT_ETHSW (1 << 17) 246 #define INT_UARTL (1 << 12) 247 #define INT_I2S (1 << 10) 248 #define INT_PERF (1 << 9) 249 #define INT_NAND (1 << 8) 250 #define INT_DMA (1 << 7) 251 #define INT_PIO (1 << 6) 252 #define INT_UARTF (1 << 5) 253 #define INT_PCM (1 << 4) 254 #define INT_ILLACC (1 << 3) 255 #define INT_WDOG (1 << 2) 256 #define INT_TIMER0 (1 << 1) 257 #define INT_SYSCTL (1 << 0) 258 259 /* 260 * Ralink Linear CPU Interrupt Mapping For Lists 261 */ 262 #define RA_IRQ_LOW 0 263 #define RA_IRQ_HIGH 1 264 #define RA_IRQ_PCI 2 265 #define RA_IRQ_FENGINE 3 266 #define RA_IRQ_WLAN 4 267 #define RA_IRQ_TIMER 5 268 #define RA_IRQ_SYSCTL 6 269 #define RA_IRQ_TIMER0 7 270 #define RA_IRQ_WDOG 8 271 #define RA_IRQ_ILLACC 9 272 #define RA_IRQ_PCM 10 273 #define RA_IRQ_UARTF 11 274 #define RA_IRQ_PIO 12 275 #define RA_IRQ_DMA 13 276 #define RA_IRQ_NAND 14 277 #define RA_IRQ_PERF 15 278 #define RA_IRQ_I2S 16 279 #define RA_IRQ_UARTL 17 280 #define RA_IRQ_ETHSW 18 281 #define RA_IRQ_USB 19 282 #define RA_IRQ_MAX 20 283 284 /* 285 * General Purpose I/O 286 */ 287 #define RA_PIO_00_23_INT 0x00 288 #define RA_PIO_00_23_EDGE_INT 0x04 289 #define RA_PIO_00_23_INT_RISE_EN 0x08 290 #define RA_PIO_00_23_INT_FALL_EN 0x0C 291 #define RA_PIO_00_23_DATA 0x20 292 #define RA_PIO_00_23_DIR 0x24 293 #define RA_PIO_00_23_POLARITY 0x28 294 #define RA_PIO_00_23_SET_BIT 0x2C 295 #define RA_PIO_00_23_CLR_BIT 0x30 296 #define RA_PIO_00_23_TGL_BIT 0x34 297 #define RA_PIO_24_39_INT 0x38 298 #define RA_PIO_24_39_EDGE_INT 0x3C 299 #define RA_PIO_24_39_INT_RISE_EN 0x40 300 #define RA_PIO_24_39_INT_FALL_EN 0x44 301 #define RA_PIO_24_39_DATA 0x48 302 #define RA_PIO_24_39_DIR 0x4C 303 #define RA_PIO_24_39_POLARITY 0x50 304 #define RA_PIO_24_39_SET_BIT 0x54 305 #define RA_PIO_24_39_CLR_BIT 0x58 306 #define RA_PIO_24_39_TGL_BIT 0x5C 307 #define RA_PIO_40_51_INT 0x60 308 #define RA_PIO_40_51_EDGE_INT 0x64 309 #define RA_PIO_40_51_INT_RISE_EN 0x68 310 #define RA_PIO_40_51_INT_FALL_EN 0x6C 311 #define RA_PIO_40_51_DATA 0x70 312 #define RA_PIO_40_51_DIR 0x74 313 #define RA_PIO_40_51_POLARITY 0x78 314 #define RA_PIO_40_51_SET_BIT 0x7C 315 #define RA_PIO_40_51_CLR_BIT 0x80 316 #define RA_PIO_40_51_TGL_BIT 0x84 317 #define RA_PIO_72_95_INT 0x88 318 #define RA_PIO_72_95_EDGE_INT 0x8c 319 #define RA_PIO_72_95_INT_RISE_EN 0x90 320 #define RA_PIO_72_95_INT_FALL_EN 0x94 321 #define RA_PIO_72_95_DATA 0x98 322 #define RA_PIO_72_95_DIR 0x9c 323 #define RA_PIO_72_95_POLARITY 0xa0 324 #define RA_PIO_72_95_SET_BIT 0xa4 325 #define RA_PIO_72_95_CLR_BIT 0xa8 326 #define RA_PIO_72_95_TGL_BIT 0xac 327 328 329 /* 330 * UART registers 331 */ 332 333 #define RA_UART_RBR 0x00 334 #define RA_UART_TBR 0x04 335 #define RA_UART_IER 0x08 336 #define RA_UART_IIR 0x0C 337 #define RA_UART_FCR 0x10 338 #define RA_UART_LCR 0x14 339 #define RA_UART_MCR 0x18 340 #define RA_UART_LSR 0x1C 341 #define RA_UART_MSR 0x20 342 #define RA_UART_DLL 0x28 343 344 345 #define UART_IER_ELSI (1 << 2) 346 /* Receiver Line Status Interrupt Enable */ 347 #define UART_IER_ETBEI (1 << 1) 348 /* Transmit Buffer Empty Interrupt Enable */ 349 #define UART_IER_ERBFI (1 << 0) 350 /* Data Ready or Character Time-Out Interrupt Enable */ 351 352 #define UART_IIR_FIFOES1 (1 << 7) /* FIFO Mode Enable Status */ 353 #define UART_IIR_FIFOES0 (1 << 6) /* FIFO Mode Enable Status */ 354 #define UART_IIR_IID3 (1 << 3) /* Interrupt Source Encoded */ 355 #define UART_IIR_IID2 (1 << 2) /* Interrupt Source Encoded */ 356 #define UART_IIR_IID1 (1 << 1) /* Interrupt Source Encoded */ 357 #define UART_IIR_IP (1 << 0) /* Interrupt Pending (active low) */ 358 359 #define UART_FCR_RXTRIG1 (1 << 7) /* Receiver Interrupt Trigger Level */ 360 #define UART_FCR_RXTRIG0 (1 << 6) /* Receiver Interrupt Trigger Level */ 361 #define UART_FCR_TXTRIG1 (1 << 5) /* Transmitter Interrupt Trigger Level */ 362 #define UART_FCR_TXTRIG0 (1 << 4) /* Transmitter Interrupt Trigger Level */ 363 #define UART_FCR_DMAMODE (1 << 3) /* Enable DMA transfers */ 364 #define UART_FCR_TXRST (1 << 2) /* Reset Transmitter FIFO */ 365 #define UART_FCR_RXRST (1 << 1) /* Reset Receiver FIFO */ 366 #define UART_FCR_FIFOE (1 << 0) /* Transmit and Receive FIFO Enable */ 367 368 #define UART_LCR_DLAB (1 << 7) /* Divisor Latch Access Bit */ 369 #define UART_LCR_SB (1 << 6) /* Set Break */ 370 #define UART_LCR_STKYP (1 << 5) /* Sticky Parity */ 371 #define UART_LCR_EPS (1 << 4) /* Even Parity Select */ 372 #define UART_LCR_PEN (1 << 3) /* Parity Enable */ 373 #define UART_LCR_STB (1 << 2) /* Stop Bit */ 374 #define UART_LCR_WLS1 (1 << 1) /* Word Length Select */ 375 #define UART_LCR_WLS0 (1 << 0) /* Word Length Select */ 376 377 #define UART_MCR_LOOP (1 << 4) /* Loop-back Mode Enable */ 378 379 #define UART_MSR_DCD (1 << 7) /* Data Carrier Detect */ 380 #define UART_MSR_RI (1 << 6) /* Ring Indicator */ 381 #define UART_MSR_DSR (1 << 5) /* Data Set Ready */ 382 #define UART_MSR_CTS (1 << 4) /* Clear To Send */ 383 #define UART_MSR_DDCD (1 << 3) /* Delta Data Carrier Detect */ 384 #define UART_MSR_TERI (1 << 2) /* Trailing Edge Ring Indicator */ 385 #define UART_MSR_DDSR (1 << 1) /* Delta Data Set Ready */ 386 #define UART_MSR_DCTS (1 << 0) /* Delta Clear To Send */ 387 388 #define UART_LSR_FIFOE (1 << 7) /* FIFO Error Status */ 389 #define UART_LSR_TEMT (1 << 6) /* Transmitter Empty */ 390 #define UART_LSR_TDRQ (1 << 5) /* Transmit Data Request */ 391 #define UART_LSR_BI (1 << 4) /* Break Interrupt */ 392 #define UART_LSR_FE (1 << 3) /* Framing Error */ 393 #define UART_LSR_PE (1 << 2) /* Parity Error */ 394 #define UART_LSR_OE (1 << 1) /* Overrun Error */ 395 #define UART_LSR_DR (1 << 0) /* Data Ready */ 396 397 /* 398 * I2C registers 399 */ 400 #define RA_I2C_CONFIG 0x00 401 #define RA_I2C_CLKDIV 0x04 402 #define RA_I2C_DEVADDR 0x08 403 #define RA_I2C_ADDR 0x0C 404 #define RA_I2C_DATAOUT 0x10 405 #define RA_I2C_DATAIN 0x14 406 #define RA_I2C_STATUS 0x18 407 #define RA_I2C_STARTXFR 0x1C 408 #define RA_I2C_BYTECNT 0x20 409 410 #define I2C_CONFIG_ADDRLEN(x) (((x) & 0x7) << 5) 411 #define I2C_CONFIG_ADDRLEN_7 6 412 #define I2C_CONFIG_ADDRLEN_8 7 413 #define I2C_CONFIG_DEVADLEN(x) (((x) & 0x7) << 2) 414 #define I2C_CONFIG_DEVADLEN_6 5 415 #define I2C_CONFIG_DEVADLEN_7 6 416 #define I2C_CONFIG_ADDRDIS (1 << 1) 417 #define I2C_CONFIG_DEVDIS (1 << 0) 418 #define I2C_STATUS_STARTERR (1 << 4) 419 #define I2C_STATUS_ACKERR (1 << 3) 420 #define I2C_STATUS_DATARDY (1 << 2) 421 #define I2C_STATUS_SDOEMPTY (1 << 1) 422 #define I2C_STATUS_BUSY (1 << 0) 423 424 /* 425 * SPI registers 426 */ 427 #define RA_SPI_STATUS 0x00 428 #define RA_SPI_CONFIG 0x10 429 #define RA_SPI_CONTROL 0x14 430 #define RA_SPI_DATA 0x20 431 432 #define SPI_STATUS_BUSY (1 << 0) 433 #define SPI_CONFIG_MSBFIRST (1 << 8) 434 #define SPI_CONFIG_CLK (1 << 6) 435 #define SPI_CONFIG_RXCLKEDGE_FALL (1 << 5) 436 #define SPI_CONFIG_TXCLKEDGE_FALL (1 << 4) 437 #define SPI_CONFIG_TRISTATE (1 << 3) 438 #define SPI_CONFIG_RATE(x) ((x) & 0x7) 439 #define SPI_CONFIG_RATE_DIV_2 0 440 #define SPI_CONFIG_RATE_DIV_4 1 441 #define SPI_CONFIG_RATE_DIV_8 2 442 #define SPI_CONFIG_RATE_DIV_16 3 443 #define SPI_CONFIG_RATE_DIV_32 4 444 #define SPI_CONFIG_RATE_DIV_64 5 445 #define SPI_CONFIG_RATE_DIV_128 6 446 #define SPI_CONFIG_RATE_DIV_NONE 7 447 #define SPI_CONTROL_TRISTATE (1 << 3) 448 #define SPI_CONTROL_STARTWR (1 << 2) 449 #define SPI_CONTROL_STARTRD (1 << 1) 450 #define SPI_CONTROL_ENABLE_LOW (0 << 0) 451 #define SPI_CONTROL_ENABLE_HIGH (1 << 0) 452 #define SPI_DATA_VAL(x) ((x) & 0xff) 453 454 /* 455 * Frame Engine registers 456 */ 457 #define RA_FE_MDIO_ACCESS 0x000 458 #define RA_FE_MDIO_CFG1 0x004 459 #define RA_FE_GLOBAL_CFG 0x008 460 #define RA_FE_GLOBAL_RESET 0x00C 461 #define RA_FE_INT_STATUS 0x010 462 #define RA_FE_INT_ENABLE 0x014 463 #define RA_FE_MDIO_CFG2 0x018 464 #define RA_FE_TIME_STAMP 0x01C 465 #define RA_FE_GDMA1_FWD_CFG 0x020 466 #define RA_FE_GDMA1_SCHED_CFG 0x024 467 #define RA_FE_GDMA1_SHAPE_CFG 0x028 468 #define RA_FE_GDMA1_MAC_LSB 0x02C 469 #define RA_FE_GDMA1_MAC_MSB 0x030 470 #define RA_FE_PSE_FQ_CFG 0x040 471 #define RA_FE_CDMA_FC_CFG 0x044 472 #define RA_FE_GDMA1_FC_CFG 0x048 473 #define RA_FE_GDMA2_FC_CFG 0x04C 474 #define RA_FE_CDMA_OQ_STA 0x050 475 #define RA_FE_GDMA1_OQ_STA 0x054 476 #define RA_FE_GDMA2_OQ_STA 0x058 477 #define RA_FE_PSE_IQ_STA 0x05C 478 #define RA_FE_GDMA2_FWD_CFG 0x060 479 #define RA_FE_GDMA2_SCHED_CFG 0x064 480 #define RA_FE_GDMA2_SHAPE_CFG 0x068 481 #define RA_FE_GDMA2_MAC_LSB 0x06C 482 #define RA_FE_GDMA2_MAC_MSB 0x070 483 #define RA_FE_CDMA_CSG_CFG 0x080 484 #define RA_FE_CDMA_SCHED_CFG 0x084 485 #define RA_FE_PPPOE_SID_0001 0x088 486 #define RA_FE_PPPOE_SID_0203 0x08C 487 #define RA_FE_PPPOE_SID_0405 0x090 488 #define RA_FE_PPPOE_SID_0607 0x094 489 #define RA_FE_PPPOE_SID_0809 0x098 490 #define RA_FE_PPPOE_SID_1011 0x09C 491 #define RA_FE_PPPOE_SID_1213 0x0A0 492 #define RA_FE_PPPOE_SID_1415 0x0A4 493 #define RA_FE_VLAN_ID_0001 0x0A8 494 #define RA_FE_VLAN_ID_0203 0x0AC 495 #define RA_FE_VLAN_ID_0405 0x0B0 496 #define RA_FE_VLAN_ID_0607 0x0B4 497 #define RA_FE_VLAN_ID_0809 0x0B8 498 #define RA_FE_VLAN_ID_1011 0x0BC 499 #define RA_FE_VLAN_ID_1213 0x0C0 500 #define RA_FE_VLAN_ID_1415 0x0C4 501 #define RA_FE_PDMA_GLOBAL_CFG 0x100 502 #define RA_FE_PDMA_RESET_IDX 0x104 503 #define RA_FE_PDMA_SCHED_CFG 0x108 504 #define RA_FE_PDMA_DLY_INT_CFG 0x10C 505 #define RA_FE_PDMA_TX0_PTR 0x110 506 #define RA_FE_PDMA_TX0_COUNT 0x114 507 #define RA_FE_PDMA_TX0_CPU_IDX 0x118 508 #define RA_FE_PDMA_TX0_DMA_IDX 0x11C 509 #define RA_FE_PDMA_TX1_PTR 0x120 510 #define RA_FE_PDMA_TX1_COUNT 0x124 511 #define RA_FE_PDMA_TX1_CPU_IDX 0x128 512 #define RA_FE_PDMA_TX1_DMA_IDX 0x12C 513 #define RA_FE_PDMA_RX0_PTR 0x130 514 #define RA_FE_PDMA_RX0_COUNT 0x134 515 #define RA_FE_PDMA_RX0_CPU_IDX 0x138 516 #define RA_FE_PDMA_RX0_DMA_IDX 0x13C 517 #define RA_FE_PDMA_TX2_PTR 0x140 518 #define RA_FE_PDMA_TX2_COUNT 0x144 519 #define RA_FE_PDMA_TX2_CPU_IDX 0x148 520 #define RA_FE_PDMA_TX2_DMA_IDX 0x14C 521 #define RA_FE_PDMA_TX3_PTR 0x150 522 #define RA_FE_PDMA_TX3_COUNT 0x154 523 #define RA_FE_PDMA_TX3_CPU_IDX 0x158 524 #define RA_FE_PDMA_TX3_DMA_IDX 0x15C 525 #define RA_FE_PDMA_FC_CFG 0x1F0 526 /* TODO: FE_COUNTERS */ 527 528 #define MDIO_ACCESS_TRG (1 << 31) 529 #define MDIO_ACCESS_WR (1 << 30) 530 #define MDIO_ACCESS_PHY_ADDR(x) (((x) & 0x1f) << 24) 531 #define MDIO_ACCESS_REG(x) (((x) & 0x1f) << 16) 532 #define MDIO_ACCESS_DATA(x) ((x) & 0xffff) 533 #define MDIO_CFG_AUTO_POLL (1 << 29) 534 #define MDIO_CFG_PHY_ADDR(x) (((x) & 0x1f) << 24) 535 #define MDIO_CFG_BP_EN (1 << 16) 536 #define MDIO_CFG_FORCE_CFG (1 << 15) 537 #define MDIO_CFG_SPEED(x) (((x) & 0x3) << 13) 538 #define MDIO_CFG_SPEED_1000M 2 539 #define MDIO_CFG_SPEED_100M 1 540 #define MDIO_CFG_SPEED_10M 0 541 #define MDIO_CFG_FULL_DUPLEX (1 << 12) 542 #define MDIO_CFG_FC_TX (1 << 11) 543 #define MDIO_CFG_FC_RX (1 << 10) 544 #define MDIO_CFG_LINK_DOWN (1 << 9) 545 #define MDIO_CFG_AUTO_DONE (1 << 8) 546 #define MDIO_CFG_MDC_CLKDIV(x) (((x) & 0x3) << 6) 547 #define MDIO_CFG_MDC_512KHZ 3 548 #define MDIO_CFG_MDC_1MHZ 2 549 #define MDIO_CFG_MDC_2MHZ 1 550 #define MDIO_CFG_MDC_4MHZ 0 551 #define MDIO_CFG_TURBO_50MHZ (1 << 5) 552 #define MDIO_CFG_TURBO_EN (1 << 4) 553 #define MDIO_CFG_RX_CLK_SKEW (((x) & 0x3) << 2) 554 #define MDIO_CFG_RX_SKEW_INV 3 555 #define MDIO_CFG_RX_SKEW_400PS 2 556 #define MDIO_CFG_RX_SKEW_200PS 1 557 #define MDIO_CFG_RX_SKEW_ZERO 0 558 #define MDIO_CFG_TX_CLK_MODE(x) (((x) & 0x1) << 0) 559 #define MDIO_CFG_TX_CLK_MODE_3COM 1 560 #define MDIO_CFG_TX_CLK_MODE_HP 0 561 #define FE_GLOBAL_CFG_EXT_VLAN(x) (((x) & 0xffff) << 16) 562 #define FE_GLOBAL_CFG_US_CLK(x) (((x) & 0xff) << 8) 563 #define FE_GLOBAL_CFG_L2_SPACE(x) (((x) & 0xf) << 4) 564 #define FE_GLOBAL_RESET_PSE (1 << 0) 565 #define FE_INT_PPE_COUNT_HIGH (1 << 31) 566 #define FE_INT_DMA_COUNT_HIGH (1 << 29) 567 #define FE_INT_PSE_P2_FC_ASSERT (1 << 26) 568 #define FE_INT_PSE_FC_DROP (1 << 24) 569 #define FE_INT_GDMA_DROP_OTHER (1 << 23) 570 #define FE_INT_PSE_P1_FC_ASSERT (1 << 22) 571 #define FE_INT_PSE_P0_FC_ASSERT (1 << 21) 572 #define FE_INT_PSE_FQ_EMPTY (1 << 20) 573 #define FE_INT_TX_COHERENT (1 << 17) 574 #define FE_INT_RX_COHERENT (1 << 16) 575 #define FE_INT_TX3 (1 << 11) 576 #define FE_INT_TX2 (1 << 10) 577 #define FE_INT_TX1 (1 << 9) 578 #define FE_INT_TX0 (1 << 8) 579 #define FE_INT_RX (1 << 2) 580 #define FE_INT_TX_DELAY (1 << 1) 581 #define FE_INT_RX_DELAY (1 << 0) 582 #define FE_GDMA_FWD_CFG_JUMBO_LEN(x) (((x) & 0xf) << 28) 583 #define FE_GDMA_FWD_CFG_DROP_256B (1 << 23) 584 #define FE_GDMA_FWD_CFG_IP4_CRC_EN (1 << 22) 585 #define FE_GDMA_FWD_CFG_TCP_CRC_EN (1 << 21) 586 #define FE_GDMA_FWD_CFG_UDP_CRC_EN (1 << 20) 587 #define FE_GDMA_FWD_CFG_JUMBO_EN (1 << 19) 588 #define FE_GDMA_FWD_CFG_DIS_TX_PAD (1 << 18) 589 #define FE_GDMA_FWD_CFG_DIS_TX_CRC (1 << 17) 590 #define FE_GDMA_FWD_CFG_STRIP_RX_CRC (1 << 16) 591 #define FE_GDMA_FWD_CFG_UNICA_PORT(x) (((x) & 0x3) << 12) 592 #define FE_GDMA_FWD_CFG_BROAD_PORT(x) (((x) & 0x3) << 8) 593 #define FE_GDMA_FWD_CFG_MULTI_PORT(x) (((x) & 0x3) << 6) 594 #define FE_GDMA_FWD_CFG_OTHER_PORT(x) (((x) & 0x3) << 0) 595 #define FE_GDMA_FWD_CFG_PORT_DROP 7 596 #define FE_GDMA_FWD_CFG_PORT_PPE 6 597 #define FE_GDMA_FWD_CFG_PORT_GDMA2 2 598 #define FE_GDMA_FWD_CFG_PORT_GDMA1 1 599 #define FE_GDMA_FWD_CFG_PORT_CPU 0 600 #define FE_PSE_FQ_MAX_COUNT(x) (((x) & 0xff) << 24) 601 #define FE_PSE_FQ_FC_RELEASE(x) (((x) & 0xff) << 16) 602 #define FE_PSE_FQ_FC_ASSERT(x) (((x) & 0xff) << 8) 603 #define FE_PSE_FQ_FC_DROP(x) (((x) & 0xff) << 0) 604 #define FE_CDMA_CSG_CFG_VLAN_TAG(x) (((x) & 0xffff) << 16) 605 #define FE_CDMA_CSG_CFG_IP4_CRC_EN (1 << 2) 606 #define FE_CDMA_CSG_CFG_UDP_CRC_EN (1 << 1) 607 #define FE_CDMA_CSG_CFG_TCP_CRC_EN (1 << 0) 608 #define FE_PDMA_GLOBAL_CFG_HDR_SEG_LEN (1 << 16) 609 #define FE_PDMA_GLOBAL_CFG_TX_WB_DDONE (1 << 6) 610 #define FE_PDMA_GLOBAL_CFG_BURST_SZ(x) (((x) & 0x3) << 4) 611 #define FE_PDMA_GLOBAL_CFG_BURST_SZ_4 (0 << 4) 612 #define FE_PDMA_GLOBAL_CFG_BURST_SZ_8 (1 << 4) 613 #define FE_PDMA_GLOBAL_CFG_BURST_SZ_16 (2 << 4) 614 #define FE_PDMA_GLOBAL_CFG_RX_DMA_BUSY (1 << 3) 615 #define FE_PDMA_GLOBAL_CFG_RX_DMA_EN (1 << 2) 616 #define FE_PDMA_GLOBAL_CFG_TX_DMA_BUSY (1 << 1) 617 #define FE_PDMA_GLOBAL_CFG_TX_DMA_EN (1 << 0) 618 #define PDMA_RST_RX0 (1 << 16) 619 #define PDMA_RST_TX3 (1 << 3) 620 #define PDMA_RST_TX2 (1 << 2) 621 #define PDMA_RST_TX1 (1 << 1) 622 #define PDMA_RST_TX0 (1 << 0) 623 624 /* 625 * 10/100 Switch registers 626 */ 627 628 #define RA_ETH_SW_ISR 0x00 629 #define RA_ETH_SW_IMR 0x04 630 #define RA_ETH_SW_FCT0 0x08 631 #define RA_ETH_SW_FCT1 0x0C 632 #define RA_ETH_SW_PFC0 0x10 633 #define RA_ETH_SW_PFC1 0x14 634 #define RA_ETH_SW_PFC2 0x18 635 #define RA_ETH_SW_QCS0 0x1C 636 #define RA_ETH_SW_QCS1 0x20 637 #define RA_ETH_SW_ATS 0x24 638 #define RA_ETH_SW_ATS0 0x28 639 #define RA_ETH_SW_ATS1 0x2C 640 #define RA_ETH_SW_ATS2 0x30 641 #define RA_ETH_SW_WMAD0 0x34 642 #define RA_ETH_SW_WMAD1 0x38 643 #define RA_ETH_SW_WMAD2 0x3C 644 #define RA_ETH_SW_PVIDC0 0x40 645 #define RA_ETH_SW_PVIDC1 0x44 646 #define RA_ETH_SW_PVIDC2 0x48 647 #define RA_ETH_SW_PVIDC3 0x4C 648 #define RA_ETH_SW_VLANI0 0x50 649 #define RA_ETH_SW_VLANI1 0x54 650 #define RA_ETH_SW_VLANI2 0x58 651 #define RA_ETH_SW_VLANI3 0x5C 652 #define RA_ETH_SW_VLANI4 0x60 653 #define RA_ETH_SW_VLANI5 0x64 654 #define RA_ETH_SW_VLANI6 0x68 655 #define RA_ETH_SW_VLANI7 0x6C 656 #define RA_ETH_SW_VMSC0 0x70 657 #define RA_ETH_SW_VMSC1 0x74 658 #define RA_ETH_SW_VMSC2 0x78 659 #define RA_ETH_SW_VMSC3 0x7C 660 #define RA_ETH_SW_POA 0x80 661 #define RA_ETH_SW_FPA 0x84 662 #define RA_ETH_SW_PTS 0x88 663 #define RA_ETH_SW_SOCPC 0x8C 664 #define RA_ETH_SW_POC0 0x90 665 #define RA_ETH_SW_POC1 0x94 666 #define RA_ETH_SW_POC2 0x98 667 #define RA_ETH_SW_SWGC 0x9C 668 #define RA_ETH_SW_RST 0xA0 669 #define RA_ETH_SW_LEDP0 0xA4 670 #define RA_ETH_SW_LEDP1 0xA8 671 #define RA_ETH_SW_LEDP2 0xAC 672 #define RA_ETH_SW_LEDP3 0xB0 673 #define RA_ETH_SW_LEDP4 0xB4 674 #define RA_ETH_SW_WDOG 0xB8 675 #define RA_ETH_SW_DBG 0xBC 676 #define RA_ETH_SW_PCTL0 0xC0 677 #define RA_ETH_SW_PCTL1 0xC4 678 #define RA_ETH_SW_FPORT 0xC8 679 #define RA_ETH_SW_FTC2 0xCC 680 #define RA_ETH_SW_QSS0 0xD0 681 #define RA_ETH_SW_QSS1 0xD4 682 #define RA_ETH_SW_DBGC 0xD8 683 #define RA_ETH_SW_MTI1 0xDC 684 #define RA_ETH_SW_PPC 0xE0 685 #define RA_ETH_SW_SGC2 0xE4 686 #define RA_ETH_SW_PCNT0 0xE8 687 #define RA_ETH_SW_PCNT1 0xEC 688 #define RA_ETH_SW_PCNT2 0xF0 689 #define RA_ETH_SW_PCNT3 0xF4 690 #define RA_ETH_SW_PCNT4 0xF8 691 #define RA_ETH_SW_PCNT5 0xFC 692 693 #define ISR_WDOG1_EXPIRED (1 << 29) 694 #define ISR_WDOG0_EXPIRED (1 << 28) 695 #define ISR_HAS_INTRUDER (1 << 27) 696 #define ISR_PORT_STS_CHNG (1 << 26) 697 #define ISR_BRDCAST_STORM (1 << 25) 698 #define ISR_MUST_DROP_LAN (1 << 24) 699 #define ISR_GLOB_QUE_FULL (1 << 23) 700 #define ISR_LAN_QUE6_FULL (1 << 20) 701 #define ISR_LAN_QUE5_FULL (1 << 19) 702 #define ISR_LAN_QUE4_FULL (1 << 18) 703 #define ISR_LAN_QUE3_FULL (1 << 17) 704 #define ISR_LAN_QUE2_FULL (1 << 16) 705 #define ISR_LAN_QUE1_FULL (1 << 15) 706 #define ISR_LAN_QUE0_FULL (1 << 14) 707 #define FTC0_REL_THR 24 708 #define FTC0_SET_THR 16 709 #define FTC0_DROP_REL_THR 8 710 #define FTC0_DROP_SET_THR 0 711 #define FTC1_PER_PORT_THR 0 712 #define PCTL0_WR_VAL(x) (((x) & 0xffff) << 16) 713 #define PCTL0_RD_CMD (1 << 14) 714 #define PCTL0_WR_CMD (1 << 13) 715 #define PCTL0_REG(x) (((x) & 0x1f) << 8) 716 #define PCTL0_ADDR(x) (((x) & 0x1f) << 0) 717 #define PCTL1_RD_VAL(x) (((x) >> 16) & 0xffff) 718 #define PCTL1_RD_DONE (1 << 1) /* read clear */ 719 #define PCTL1_WR_DONE (1 << 0) /* read clear */ 720 #define SGC2_WL_FC_EN (1 << 30) 721 #define SGC2_PORT5_IS_LAN (1 << 29) 722 #define SGC2_PORT4_IS_LAN (1 << 28) 723 #define SGC2_PORT3_IS_LAN (1 << 27) 724 #define SGC2_PORT2_IS_LAN (1 << 26) 725 #define SGC2_PORT1_IS_LAN (1 << 25) 726 #define SGC2_PORT0_IS_LAN (1 << 24) 727 #define SGC2_TX_CPU_TPID(x) ((x) << 16) 728 #define SGC2_ARBITER_LAN_EN (1 << 11) 729 #define SGC2_CPU_TPID_EN (1 << 10) 730 #define SGC2_DBL_TAG_EN5 (1 << 5) 731 #define SGC2_DBL_TAG_EN4 (1 << 4) 732 #define SGC2_DBL_TAG_EN3 (1 << 3) 733 #define SGC2_DBL_TAG_EN2 (1 << 2) 734 #define SGC2_DBL_TAG_EN1 (1 << 1) 735 #define SGC2_DBL_TAG_EN0 (1 << 0) 736 737 738 #define FTC_THR_MSK 0xff 739 740 #define PFC0_MTCC_LIMIT 24 741 #define PFC0_TURN_OFF_CF 16 742 #define PFC0_TURN_OFF_CF_MSK 0xff 743 #define PFC0_VO_NUM 12 744 #define PFC0_CL_NUM 8 745 #define PFC0_BE_NUM 4 746 #define PFC0_BK_NUM 0 747 #define PFC0_NUM_MSK 0xf 748 749 #define PFC1_P6_Q1_EN (1 << 31) 750 #define PFC1_P6_TOS_EN (1 << 30) 751 #define PFC1_P5_TOS_EN (1 << 29) 752 #define PFC1_P4_TOS_EN (1 << 28) 753 #define PFC1_P3_TOS_EN (1 << 27) 754 755 #define PFC1_P1_TOS_EN (1 << 25) 756 #define PFC1_P0_TOS_EN (1 << 24) 757 #define PFC1_PORT_PRI6 12 758 #define PFC1_PORT_PRI5 10 759 #define PFC1_PORT_PRI4 8 760 #define PFC1_PORT_PRI3 6 761 #define PFC1_PORT_PRI2 4 762 #define PFC1_PORT_PRI1 2 763 #define PFC1_PORT_PRI0 0 764 #define PFC1_PORT_MSK 0x3 765 766 #define PFC2_PRI_THR_VO 24 767 #define PFC2_PRI_THR_CL 16 768 #define PFC2_PRI_THR_BE 8 769 #define PFC2_PRI_THR_BK 0 770 #define PFC2_PRI_THR_MSK 0xff 771 772 #define GQC0_EMPTY_BLOCKS 0 773 #define GQC0_EMPTY_BLOCKS_MSK 0xff 774 775 /* 776 * USB OTG Registers 777 */ 778 #define RA_USB_OTG_OTG_CNTRL 0x000 779 #define RA_USB_OTG_OTG_INT 0x004 780 #define RA_USB_OTG_AHB_CFG 0x008 781 #define RA_USB_OTG_CFG 0x00C 782 #define RA_USB_OTG_RESET 0x010 783 #define RA_USB_OTG_INT 0x014 784 #define RA_USB_OTG_INT_MASK 0x018 785 #define RA_USB_OTG_RX_STAT 0x01C 786 #define RA_USB_OTG_RX_POP_STAT 0x020 787 #define RA_USB_OTG_RX_FIFO_SZ 0x024 788 #define RA_USB_OTG_TX_FIFO_SZ 0x028 789 #define RA_USB_OTG_TX_FIFO_STAT 0x02C 790 #define RA_USB_OTG_I2C_ACCESS 0x030 791 #define RA_USB_OTG_PHY_CTL 0x034 792 #define RA_USB_OTG_GPIO 0x038 793 #define RA_USB_OTG_GUID 0x03C 794 #define RA_USB_OTG_SNPSID 0x040 795 #define RA_USB_OTG_HWCFG1 0x044 796 #define RA_USB_OTG_HWCFG2 0x048 797 #define RA_USB_OTG_HWCFG3 0x04C 798 #define RA_USB_OTG_HWCFG4 0x050 799 #define RA_USB_OTG_HC_TX_FIFO_SZ 0x100 800 #define RA_USB_OTG_DV_TX_FIFO_SZ 0x104 801 #define RA_USB_OTG_HC_CFG 0x400 802 #define RA_USB_OTG_HC_FRM_INTRVL 0x404 803 #define RA_USB_OTG_HC_FRM_NUM 0x408 804 #define RA_USB_OTG_HC_TX_STAT 0x410 805 #define RA_USB_OTG_HC_INT 0x414 806 #define RA_USB_OTG_HC_INT_MASK 0x418 807 #define RA_USB_OTG_HC_PORT 0x440 808 #define RA_USB_OTG_HC_CH_CFG 0x500 809 #define RA_USB_OTG_HC_CH_SPLT 0x504 810 #define RA_USB_OTG_HC_CH_INT 0x508 811 #define RA_USB_OTG_HC_CH_INT_MASK 0x50C 812 #define RA_USB_OTG_HC_CH_XFER 0x510 813 #define RA_USB_OTG_HC_CH_DMA_ADDR 0x514 814 #define RA_USB_OTG_DV_CFG 0x800 815 #define RA_USB_OTG_DV_CTL 0x804 816 #define RA_USB_OTG_DV_STAT 0x808 817 #define RA_USB_OTG_DV_IN_INT_MASK 0x810 818 #define RA_USB_OTG_DV_OUT_INT_MASK 0x814 819 #define RA_USB_OTG_DV_ALL_INT 0x818 820 #define RA_USB_OTG_DV_EP_INT_MASK 0x81c 821 #define RA_USB_OTG_DV_IN_SEQ_RQ1 0x820 822 #define RA_USB_OTG_DV_IN_SEQ_RQ2 0x824 823 #define RA_USB_OTG_DV_IN_SEQ_RQ3 0x830 824 #define RA_USB_OTG_DV_IN_SEQ_RQ4 0x834 825 #define RA_USB_OTG_DV_VBUS_DISCH 0x828 826 #define RA_USB_OTG_DV_VBUS_PULSE 0x82c 827 #define RA_USB_OTG_DV_THRESH_CTL 0x830 828 #define RA_USB_OTG_DV_IN_FIFO_INT 0x834 829 #define RA_USB_OTG_DV_IN0_CTL 0x900 830 831 #define OTG_OTG_CNTRL_B_SESS_VALID (1 << 19) 832 #define OTG_OTG_CNTRL_A_SESS_VALID (1 << 18) 833 #define OTG_OTG_CNTRL_DEBOUNCE_SHORT (1 << 17) 834 #define OTG_OTG_CNTRL_CONNID_STATUS (1 << 16) 835 #define OTG_OTG_CNTRL_DV_HNP_EN (1 << 11) 836 #define OTG_OTG_CNTRL_HC_SET_HNP_EN (1 << 10) 837 #define OTG_OTG_CNTRL_HNP_REQ (1 << 9) 838 #define OTG_OTG_CNTRL_HNP_SUCCESS (1 << 8) 839 #define OTG_OTG_CNTRL_SESS_REQ (1 << 1) 840 #define OTG_OTG_CNTRL_SESS_REQ_SUCCESS (1 << 0) 841 #define OTG_OTG_INT_DEBOUNCE_DONE (1 << 19) 842 #define OTG_OTG_INT_ADEV_TIMEOUT (1 << 18) 843 #define OTG_OTG_INT_HOST_NEG_DETECT (1 << 17) 844 #define OTG_OTG_INT_HOST_NEG_STATUS (1 << 9) 845 #define OTG_OTG_INT_SESSION_REQ_STATUS (1 << 8) 846 #define OTG_OTG_INT_SESSION_END_STATUS (1 << 2) 847 #define OTG_AHB_CFG_TX_PFIFO_EMPTY_INT_EN (1 << 8) 848 #define OTG_AHB_CFG_TX_NPFIFO_EMPTY_INT_EN (1 << 7) 849 #define OTG_AHB_CFG_DMA_EN (1 << 5) 850 #define OTG_AHB_CFG_BURST(x) (((x) & 0xf) << 1) 851 #define OTG_AHB_CFG_BURST_SINGLE 0 852 #define OTG_AHB_CFG_BURST_INCR 1 853 #define OTG_AHB_CFG_BURST_INCR4 3 854 #define OTG_AHB_CFG_BURST_INCR8 5 855 #define OTG_AHB_CFG_BURST_INCR16 7 856 #define OTG_AHB_CFG_GLOBAL_INT_EN (1 << 0) 857 #define OTG_CFG_CORRUPT_TX (1 << 31) 858 #define OTG_CFG_FORCE_DEVICE (1 << 30) 859 #define OTG_CFG_FORCE_HOST (1 << 29) 860 #define OTG_CFG_ULPI_EXT_VBUS_IND_SEL (1 << 22) 861 #define OTG_CFG_ULPI_EXT_VBUS_IND (1 << 21) 862 #define OTG_CFG_ULPI_EXT_VBUS_DRV (1 << 20) 863 #define OTG_CFG_ULPI_CLOCK_SUSPEND (1 << 19) 864 #define OTG_CFG_ULPI_AUTO_RESUME (1 << 18) 865 #define OTG_CFG_ULPI_FS_LS_SEL (1 << 17) 866 #define OTG_CFG_UTMI_I2C_SEL (1 << 16) 867 #define OTG_CFG_TURNAROUND_TIME(x) (((x) & 0xf) << 10) 868 #define OTG_CFG_HNP_CAP (1 << 9) 869 #define OTG_CFG_SRP_CAP (1 << 8) 870 #define OTG_CFG_ULPI_DDR_SEL (1 << 7) 871 #define OTG_CFG_HS_PHY_SEL (1 << 6) 872 #define OTG_CFG_FS_IF_SEL (1 << 5) 873 #define OTG_CFG_ULPI_UTMI_SEL (1 << 4) 874 #define OTG_CFG_PHY_IF (1 << 3) 875 #define OTG_CFG_TIMEOUT(x) (((x) & 0x7) << 0) 876 #define OTG_RST_AHB_IDLE (1 << 31) 877 #define OTG_RST_DMA_ACTIVE (1 << 30) 878 #define OTG_RST_TXQ_TO_FLUSH(x) (((x) & 0x1f) << 6) 879 #define OTG_RST_TXQ_FLUSH_ALL 0x10 880 #define OTG_RST_TXQ_FLUSH (1 << 5) 881 #define OTG_RST_RXQ_FLUSH (1 << 4) 882 #define OTG_RST_INQ_FLUSH (1 << 3) 883 #define OTG_RST_HC_FRAME (1 << 2) 884 #define OTG_RST_AHB (1 << 1) 885 #define OTG_RST_CORE (1 << 0) 886 #define OTG_INT_RESUME (1 << 31) 887 #define OTG_INT_SESSION_REQ (1 << 30) 888 #define OTG_INT_DISCONNECT (1 << 29) 889 #define OTG_INT_CONNID_STATUS (1 << 28) 890 #define OTG_INT_PTX_EMPTY (1 << 26) 891 #define OTG_INT_HOST_CHANNEL (1 << 25) 892 #define OTG_INT_PORT_STATUS (1 << 24) 893 #define OTG_INT_DMA_FETCH_SUSPEND (1 << 22) 894 #define OTG_INT_INCOMPLETE_PERIODIC (1 << 21) 895 #define OTG_INT_INCOMPLETE_ISOC (1 << 20) 896 #define OTG_INT_DV_OUT_EP (1 << 19) 897 #define OTG_INT_DV_IN_EP (1 << 18) 898 #define OTG_INT_DV_EP_MISMATCH (1 << 17) 899 #define OTG_INT_DV_PERIODIC_END (1 << 15) 900 #define OTG_INT_DV_ISOC_OUT_DROP (1 << 14) 901 #define OTG_INT_DV_ENUM_COMPLETE (1 << 13) 902 #define OTG_INT_DV_USB_RESET (1 << 12) 903 #define OTG_INT_DV_USB_SUSPEND (1 << 11) 904 #define OTG_INT_DV_USB_EARLY_SUSPEND (1 << 10) 905 #define OTG_INT_I2C (1 << 9) 906 #define OTG_INT_ULPI_CARKIT (1 << 8) 907 #define OTG_INT_DV_OUT_NAK_EFFECTIVE (1 << 7) 908 #define OTG_INT_DV_IN_NAK_EFFECTIVE (1 << 6) 909 #define OTG_INT_NPTX_EMPTY (1 << 5) 910 #define OTG_INT_RX_FIFO (1 << 4) 911 #define OTG_INT_SOF (1 << 3) 912 #define OTG_INT_OTG (1 << 2) 913 #define OTG_INT_MODE_MISMATCH (1 << 1) 914 #define OTG_INT_MODE (1 << 0) 915 #define USB_OTG_SNPSID_CORE_REV_2_00 0x4F542000 916 #define OTG_HC_CFG_FORCE_NO_HS (1 << 2) 917 #define OTG_HC_CFG_FSLS_CLK_SEL(x) (((x) & 0x3) << 0) 918 #define OTG_HC_CFG_FS_CLK_3060 0 919 #define OTG_HC_CFG_FS_CLK_48 1 920 #define OTG_HC_CFG_LS_CLK_3060 0 921 #define OTG_HC_CFG_LS_CLK_48 1 922 #define OTG_HC_CFG_LS_CLK_6 2 923 #define USB_OTG_HC_FRM_NUM(x) (x & 0x3fff) 924 #define USB_OTG_HC_FRM_REM(x) (x >> 16) 925 #define USB_OTG_HC_PORT_SPEED(x) (((x) >> 17) & 0x3) 926 #define USB_OTG_HC_PORT_SPEED_HS 0 927 #define USB_OTG_HC_PORT_SPEED_FS 1 928 #define USB_OTG_HC_PORT_SPEED_LS 2 929 #define USB_OTG_HC_PORT_TEST(x) (((x) & 0xf) << 13) 930 #define USB_OTG_HC_PORT_TEST_DISABLED 0 931 #define USB_OTG_HC_PORT_TEST_J_MODE 1 932 #define USB_OTG_HC_PORT_TEST_K_MODE 2 933 #define USB_OTG_HC_PORT_TEST_NAK_MODE 3 934 #define USB_OTG_HC_PORT_TEST_PKT_MODE 4 935 #define USB_OTG_HC_PORT_TEST_FORCE_MODE 5 936 #define USB_OTG_HC_PORT_POWER (1 << 12) 937 #define USB_OTG_HC_PORT_LINE_STAT (((x) >> 10) & 0x3) 938 #define USB_OTG_HC_PORT_LINE_STAT_DP 1 939 #define USB_OTG_HC_PORT_LINE_STAT_DM 3 940 #define USB_OTG_HC_PORT_RESET (1 << 8) 941 #define USB_OTG_HC_PORT_SUSPEND (1 << 7) 942 #define USB_OTG_HC_PORT_RESUME (1 << 6) 943 #define USB_OTG_HC_PORT_OVCURR_CHANGE (1 << 5) 944 #define USB_OTG_HC_PORT_OVCURR (1 << 4) 945 #define USB_OTG_HC_PORT_ENABLE_CHANGE (1 << 3) 946 #define USB_OTG_HC_PORT_ENABLE (1 << 2) 947 #define USB_OTG_HC_PORT_CONNECT_CHANGE (1 << 1) 948 #define USB_OTG_HC_PORT_STATUS (1 << 0) 949 #define USB_OTG_HC_CH_CFG_ENABLE (1 << 31) 950 #define USB_OTG_HC_CH_CFG_DISABLE (1 << 30) 951 #define USB_OTG_HC_CH_CFG_ODD_FRAME (1 << 29) 952 #define USB_OTG_HC_CH_CFG_DEV_ADDR(x) (((x) & 0x7f) << 22) 953 #define USB_OTG_HC_CH_CFG_MULTI_CNT(x) (((x) & 0x3) << 20) 954 #define USB_OTG_HC_CH_CFG_EP_TYPE(x) (((x) & 0x3) << 18) 955 #define USB_OTG_HC_CH_CFG_EP_TYPE_CTRL 0 956 #define USB_OTG_HC_CH_CFG_EP_TYPE_ISOC 1 957 #define USB_OTG_HC_CH_CFG_EP_TYPE_BULK 2 958 #define USB_OTG_HC_CH_CFG_EP_TYPE_INTR 3 959 #define USB_OTG_HC_CH_CFG_LS (1 << 17) 960 #define USB_OTG_HC_CH_CFG_EP_DIR(x) (((x) & 0x1) << 15) 961 #define USB_OTG_HC_CH_CFG_EP_DIR_OUT 0 962 #define USB_OTG_HC_CH_CFG_EP_DIR_IN 1 963 #define USB_OTG_HC_CH_CFG_EP_NUM(x) (((x) & 0xf) << 11) 964 #define USB_OTG_HC_CH_CFG_MAX_PKT_SZ(x) (((x) & 0x7ff) << 0) 965 #define USB_OTG_HC_CH_SPLT_EN (1 << 31) 966 #define USB_OTG_HC_CH_SPLT_COMPLETE (1 << 16) 967 #define USB_OTG_HC_CH_SPLT_POS(x) (((x) & 0x3) << 14) 968 #define USB_OTG_HC_CH_SPLT_POS_MID 0 969 #define USB_OTG_HC_CH_SPLT_POS_END 1 970 #define USB_OTG_HC_CH_SPLT_POS_BEGIN 2 971 #define USB_OTG_HC_CH_SPLT_POS_ALL 3 972 #define USB_OTG_HC_CH_SPLT_HUB_ADDR(x) (((x) & 0x7f) << 7) 973 #define USB_OTG_HC_CH_SPLT_PORT_ADDR(x) (((x) & 0x7f) << 0) 974 #define USB_OTG_HC_CH_INT_ALL 0x7ff 975 #define USB_OTG_HC_CH_INT_TOGGLE_ERROR (1 << 10) 976 #define USB_OTG_HC_CH_INT_FRAME_OVERRUN (1 << 9) 977 #define USB_OTG_HC_CH_INT_BABBLE_ERROR (1 << 8) 978 #define USB_OTG_HC_CH_INT_XACT_ERROR (1 << 7) 979 #define USB_OTG_HC_CH_INT_NYET (1 << 6) 980 #define USB_OTG_HC_CH_INT_ACK (1 << 5) 981 #define USB_OTG_HC_CH_INT_NAK (1 << 4) 982 #define USB_OTG_HC_CH_INT_STALL (1 << 3) 983 #define USB_OTG_HC_CH_INT_DMA_ERROR (1 << 2) 984 #define USB_OTG_HC_CH_INT_HALTED (1 << 1) 985 #define USB_OTG_HC_CH_INT_XFER_COMPLETE (1 << 0) 986 #define USB_OTG_HC_CH_XFER_DO_PING (1 << 31) 987 #define USB_OTG_HC_CH_WR_XFER_PID(x) (((x) & 0x3) << 29) 988 #define USB_OTG_HC_CH_RD_XFER_PID(x) (((x) >> 29) & 0x3) 989 #define USB_OTG_HC_CH_XFER_PID_DATA0 0 990 #define USB_OTG_HC_CH_XFER_PID_DATA2 1 991 #define USB_OTG_HC_CH_XFER_PID_DATA1 2 992 #define USB_OTG_HC_CH_XFER_PID_SETUP 3 993 #define USB_OTG_HC_CH_XFER_PID_MDATA 3 994 #define USB_OTG_HC_CH_XFER_SET_PKT_CNT(x) (((x) & 0x3ff) << 19) 995 #define USB_OTG_HC_CH_XFER_SET_BYTES(x) ((x) & 0x7ffff) 996 #define USB_OTG_HC_CH_XFER_GET_PKT_CNT(x) (((x) >> 19) & 0x3ff) 997 #define USB_OTG_HC_CH_XFER_GET_BYTES(x) ((x) & 0x7ffff) 998 999 #endif /* _RALINK_REG_H_ */ 1000
Indexes created Thu Oct 23 22:10:10 GMT 2025